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1. 发明申请

WO2013134051A1 COMPOSED MEMORY ARRAY COMPRISING A FLASH ARRAY AND A RAM ARRAY WITH DATA WRITE TO THE RAM ARRAY AND DATA READ FROM THE FLASH ARRAY 审中-公开
标题翻译：组合的存储阵列包含一个闪存阵列和一个RAM阵列，数据写入RAM阵列，并从闪存阵列读取数据
公开(公告)号：WO2013134051A1
公开(公告)日：2013-09-12
申请号：PCT/US2013/028513
申请日：2013-03-01
申请人： MEDTRONIC, INC.
发明人： WALSH, Kevin K. , BIGELOW, Duane R. , REILAND, Jerry D. , SOLHEIM, Paul R. , MUSTO, Robert D. , GORDON, Charles R.
IPC分类号： G11C11/00 , G11C16/10
CPC分类号： G11C11/005 , G06F3/0601 , G06F3/0646 , G06F3/0668 , G06F3/0679 , G06F12/0238 , G06F12/0246 , G06F12/0623 , G06F12/0868 , G06F13/387 , G06F13/42 , G06F13/4234 , G11C16/10
摘要： Memory array, system and method for storing data. The memory array has a flash memory array, a random access memory array coupled to the flash memory and configured to receive the data, a memory management module and a data bus. The memory management module is coupled to the random access memory array and to the flash memory array, the memory management module being configured to transfer at least a portion of the data stored in the random access memory array to the flash memory array. The data bus is coupled to the flash memory array and configured to output at least a portion of the data originally stored in the random access memory array from the flash memory array.
摘要翻译：用于存储数据的存储器阵列，系统和方法。存储器阵列具有闪存阵列，耦合到闪存并被配置为接收数据的随机存取存储器阵列，存储器管理模块和数据总线。存储器管理模块耦合到随机存取存储器阵列和闪速存储器阵列，存储器管理模块被配置为将存储在随机存取存储器阵列中的数据的至少一部分传送到闪存阵列。数据总线耦合到闪速存储器阵列并且被配置为从闪速存储器阵列输出原始存储在随机存取存储器阵列中的数据的至少一部分。

2. 发明申请

WO2013103624A1 STABLE MEMORY SOURCE BIAS OVER TEMPERATURE AND METHOD 审中-公开
标题翻译：稳定的存储源偏离温度和方法
公开(公告)号：WO2013103624A1
公开(公告)日：2013-07-11
申请号：PCT/US2013/020004
申请日：2013-01-03
申请人： MEDTRONIC, INC.
发明人： WALSH, Kevin K. , TYLER, Larry E. , SCOTT, Brandon P.
IPC分类号： G11C11/417
CPC分类号： G11C11/417
摘要： Random access memory having a plurality of memory cells, each of the plurality of memory cells having a memory element and a first electrical characteristic being variable based, at least in part, on temperature and a bias circuit operatively coupled to at least one of the plurality of memory cells, the bias circuit being configured to generate a bias voltage for the at least one of the plurality of memory cells. The bias circuit has a second electrical characteristic being variable based, at least in part, on temperature. The first electrical characteristic is approximately proportional to the second electrical characteristic over a predetermined range of temperatures, the predetermined range of temperatures being greater than zero. The bias voltage on each of the plurality of memory cells is approximately proportional with variations in the first electrical characteristic over the predetermined range of temperatures.
摘要翻译：具有多个存储器单元的随机存取存储器，所述多个存储器单元中的每一个具有存储元件和第一电特性，所述第一电特性至少部分地基于温度和可操作地耦合到所述多个存储单元中的至少一个的偏置电路而变化; 所述偏置电路被配置为产生所述多个存储器单元中的所述至少一个存储器单元的偏置电压。偏置电路具有至少部分地基于温度变化的第二电特性。在预定温度范围内，第一电特性与第二电特性近似成比例，预定温度范围大于零。多个存储单元中的每一个上的偏置电压大约与预定温度范围内的第一电特性的变化成比例。

3. 发明申请

WO2013134053A1 VOLTAGE MODE SENSING FOR LOW POWER FLASH MEMORY 审中-公开
标题翻译：低功耗闪存存储器的电压模式检测
公开(公告)号：WO2013134053A1
公开(公告)日：2013-09-12
申请号：PCT/US2013/028517
申请日：2013-03-01
申请人： MEDTRONIC, INC.
发明人： WALSH, Kevin K. , PATTERSON, Paul B. , BENTON, Glen W. , WILKINSON, Jeffrey D.
IPC分类号： G11C16/28 , G11C16/26 , G11C7/08 , G11C7/22 , G11C7/14 , G11C11/00 , G11C17/12 , G11C29/50
CPC分类号： G11C16/30 , G11C7/065 , G11C7/08 , G11C7/14 , G11C7/227 , G11C11/005 , G11C16/26 , G11C16/28 , G11C17/12 , G11C29/50 , G11C29/50004
摘要： An electrically erasable flash memory has a memory array (50) comprising at least one row (24, 44) of memory cells (10, 30). Each memory cell has a data state. A voltage sensing circuit (54) is selectively coupled to individual ones of memory cells and configured to bias them with at least one of a bias current and a bias resistance in order to read the data states of the individual selected memory cells. A reference bit Nine (66) provides an indication to the sensing circuit (54) that data on a selected bit line (26) may be accurately read.
摘要翻译：电可擦除闪存具有包括存储器单元（10,30）的至少一行（24,44）的存储器阵列（50）。每个存储单元都具有数据状态。电压感测电路（54）被选择性地耦合到各个存储器单元，并且被配置为利用偏置电流和偏置电阻中的至少一个来偏置它们，以便读取各个选择的存储单元的数据状态。参考位九（66）向感测电路（54）提供指示，可以精确地读取所选位线（26）上的数据。

4. 发明申请

WO2007016564A3 IMPLANTABLE MEDICAL DEVICE BUS SYSTEM AND METHOD 审中-公开
公开(公告)号：WO2007016564A3
公开(公告)日：2007-02-08
申请号：PCT/US2006/029936
申请日：2006-07-31
申请人： MEDTRONIC, INC. , KALLMYER, Todd A. , WALSH, Kevin K. , HUELSKAMP, Paul, J. , ERICKSEN, James, H. , MASOUD, Javaid , STROEBEL, John, C. , STOCKBURGER, Mark, A. , EVERS, Xander
发明人： KALLMYER, Todd A. , WALSH, Kevin K. , HUELSKAMP, Paul, J. , ERICKSEN, James, H. , MASOUD, Javaid , STROEBEL, John, C. , STOCKBURGER, Mark, A. , EVERS, Xander
IPC分类号： A61N1/372 , G06F13/37
摘要： A bus system is provided for implantable medical devices. The bus system provides for flexible and reliable communication between subsystems in an implantable medical device. The bus system facilitates a wide variety of communications between various subsystems. These various subsystems can include one or more sensing devices, processors, data storage devices, patient alert devices, power management devices, signal processing and other devices implemented to perform a variety of different functions.

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