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1. 发明申请

WO2007016626A3 LOW-NOISE FINE-FREQUENCY TUNING 审中-公开
标题翻译：低噪声微调调谐
公开(公告)号：WO2007016626A3
公开(公告)日：2007-11-15
申请号：PCT/US2006030091
申请日：2006-08-01
申请人： MARVELL WORLD TRADE LTD , GREENBERG JODY , SUTARDJA SEHAT
发明人： GREENBERG JODY , SUTARDJA SEHAT
IPC分类号： H03L7/00 , H03B1/00
CPC分类号： H03H19/008 , H03L1/00 , H03L1/026
摘要： Figure 3 is an exemplary embodiment of a free running oscillator (310) that is calibrated, the calibration circuit includes the reference oscillator (320), calibration control circuit (330), programmable look-up table (340), transistor (350), capacitor (360), and PWM circuit (370). The invention adjusts a capacitance value by pulse width modulating a control voltage for a switch in series with a capacitor. The PWM signal can be adjusted by using entry values found in a look up table, by using analog or digital control signals, or other approppate methods. The capacitance value tunes a frequency response or characteristic of an electronic circuit The response can be made to be insensitive to conditions such as temperature, power supply voltage or processing.
摘要翻译：图3是经校准的自由振荡器（310）的示例性实施例，校准电路包括参考振荡器（320），校准控制电路（330），可编程查找表（340），晶体管（350）电容器（360）和PWM电路（370）。本发明通过对与电容器串联的开关的控制电压进行脉宽调制来调整电容值。可以通过使用查询表中的输入值，使用模拟或数字控制信号或其他适用方法来调整PWM信号。电容值调节电子电路的频率响应或特性可以使响应对温度，电源电压或处理等条件不敏感。

2. 发明申请

WO2007016601A3 ON-DIE HEATING CIRCUIT AND CONTROL LOOP FOR RAPID HEATING OF THE DIE 审中-公开
标题翻译：加热加热电路和控制环用于快速加热DIE
公开(公告)号：WO2007016601A3
公开(公告)日：2007-04-26
申请号：PCT/US2006030015
申请日：2006-08-01
申请人： MARVELL WORLD TRADE LTD , GREENBERG JODY , SUTARDJA SEHAT
发明人： GREENBERG JODY , SUTARDJA SEHAT
IPC分类号： G01R23/00 , G05D23/20 , H03B1/00
CPC分类号： H01L23/345 , H01L23/34 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes a heating circuit configured to heat the integrated circuit under the control of a controller. A transfer function with adjustable pole (P), zero (Z) and overall gain (Gain) is implemented in the controller such that a temperature response of the integrated circuit can be changed by adjusting one or more of the adjustable pole (P), zero (Z) and overall gain (Gain).
摘要翻译：集成电路包括被配置为在控制器的控制下加热集成电路的加热电路。在控制器中实现具有可调极（P），零（Z）和总增益（Gain）的传递函数，使得可以通过调节可调节极（P）中的一个或多个来改变集成电路的温度响应，零（Z）和总增益（增益）。

3. 发明申请

WO2014026006A2 CONTROLLING FAN MOTORS USING CAPACITIVE SENSING 审中-公开
标题翻译：用电容式感应控制风扇电机
公开(公告)号：WO2014026006A2
公开(公告)日：2014-02-13
申请号：PCT/US2013054144
申请日：2013-08-08
申请人： MARVELL WORLD TRADE LTD , SUTARDJA SEHAT
发明人： SUTARDJA SEHAT
IPC分类号： H02K11/00
CPC分类号： H02K11/0015 , G01D5/2412 , G01P3/483 , G01P13/045 , H02K11/21
摘要： A motor having a rotor, the rotor including a first metal plate having a first size and a second metal plate having a second size arranged on a first surface associated with the rotor. The first metal plate and the second metal plate are arranged adjacent to each other at a predetermined distance from an axis of rotation of the rotor. The first surface rotates perpendicularly about the axis in response to the rotor being rotated about the axis. A stator includes a third metal plate arranged on a second surface associated with the stator. The third metal plate is arranged on the second surface at the predetermined distance from the axis. The second surface is parallel to the first surface and faces the first surface.
摘要翻译：一种具有转子的电动机，转子包括具有第一尺寸的第一金属板和具有第二尺寸的第二金属板，该第二尺寸被布置在与转子相关联的第一表面上。第一金属板和第二金属板相对于转子的旋转轴线以预定的距离彼此相邻布置。响应于转子围绕轴线旋转，第一表面围绕轴线垂直旋转。定子包括布置在与定子相关联的第二表面上的第三金属板。第三金属板以距轴线预定的距离布置在第二表面上。第二表面平行于第一表面并面向第一表面。

4. 发明申请

WO2012154720A3 METAL OXIDE METAL CAPACITOR STRUCTURES 审中-公开
标题翻译：金属氧化物金属电容器结构
公开(公告)号：WO2012154720A3
公开(公告)日：2013-04-25
申请号：PCT/US2012036897
申请日：2012-05-08
申请人： MARVELL WORLD TRADE LTD , SUTARDJA SEHAT
发明人： SUTARDJA SEHAT
IPC分类号： H01L29/92 , H01G4/005 , H01G4/10 , H01G4/228
CPC分类号： H01G4/10 , H01G4/005 , H01G4/228 , H01L23/5223 , H01L28/60 , H01L28/86 , H01L28/90 , H01L2924/0002 , H01L2924/00
摘要： A metal oxide metal (MOM) capacitor includes an outer conducting structure defined in a plurality of metal layers and a plurality of via layers of an integrated circuit including first opposing side walls, second opposing side walls, a cavity with first and second openings, and openings in the first opposing side walls. An inner conducting structure is defined in the plurality of metal layers and the plurality of via layers of the integrated circuit. The inner conducting structure is arranged in the cavity of the outer conducting structure and includes a body, and conducting extensions that extend from the body through the openings in the first opposing side walls. Oxide is arranged between the outer conducting structure and the inner conducting structure.
摘要翻译：金属氧化物金属（MOM）电容器包括限定在多个金属层中的外部导电结构和包括第一相对侧壁，第二相对侧壁，具有第一和第二开口的空腔的集成电路的多个通孔层，以及在第一相对侧壁中的开口。内部导电结构限定在集成电路的多个金属层和多个通孔层中。内部导电结构被布置在外部导电结构的空腔中，并且包括主体以及从主体穿过第一相对侧壁中的开口延伸的导电延伸部。氧化物布置在外部导电结构和内部导电结构之间。

5. 发明申请

WO2013067137A3 SCALABLE SUCCESSIVE-APPROXIMATION-REGISTER ANALOG-TO-DIGITAL CONVERTERS 审中-公开
标题翻译：可扩展的连续近似注册模拟数字转换器
公开(公告)号：WO2013067137A3
公开(公告)日：2013-07-18
申请号：PCT/US2012062990
申请日：2012-11-01
申请人： MARVELL WORLD TRADE LTD , SUTARDJA SEHAT , CESURA GIOVANNI ANTONIO , REZZI FRANCESCO , CASTELLO RINALDO
发明人： SUTARDJA SEHAT , CESURA GIOVANNI ANTONIO , REZZI FRANCESCO , CASTELLO RINALDO
IPC分类号： H03M1/00
CPC分类号： H03M1/20 , A01K79/00 , A23K50/80 , H03M1/002 , H03M1/0643 , H03M1/0678 , H03M1/1076 , H03M1/121 , H03M1/468
摘要： A system including a clock generator configured to generate a clock; a plurality of analog-to-digital converters each configured to convert a signal based on the clock, and to output a first number of bits in response to converting the signal based on the clock; and an averaging module configured to receive the first number of bits from each of the plurality of analog-to-digital converters, and to output a second number of bits. The second number of bits is greater than the first number of bits.
摘要翻译：一种系统，包括被配置为生成时钟的时钟发生器; 多个模数转换器，每个模数转换器被配置为基于时钟转换信号，并且响应于基于时钟转换信号而输出第一数量的比特; 以及平均模块，被配置为从所述多个模数转换器中的每一个接收所述第一数量的比特，并且输出第二数量的比特。第二位数大于第一位数。

6. 发明申请

WO2013002941A1 INTEGRATED CIRCUIT COMPRISING A MOSFET HAVING BALLAST RESISTORS AND CORRESPONDING MANUFACTURING METHOD 审中-公开
标题翻译：包括具有压阻电阻器的MOSFET的集成电路及相应的制造方法
公开(公告)号：WO2013002941A1
公开(公告)日：2013-01-03
申请号：PCT/US2012040059
申请日：2012-05-31
申请人： MARVELL WORLD TRADE LTD , SUTARDJA SEHAT , KRISHNAMOORTHY RAVISHANKER , CHUI SIEW YONG
发明人： SUTARDJA SEHAT , KRISHNAMOORTHY RAVISHANKER , CHUI SIEW YONG
IPC分类号： H01L29/78 , H01L21/336 , H01L29/08
CPC分类号： H01L27/0266 , H01L27/0288 , H01L29/0847 , H01L29/0878 , H01L29/66659 , H01L29/66681 , H01L29/7817 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit including a well region (156) having a first doping level and a plurality of semiconductor regions (154) implanted in the well region. Each of the plurality of semiconductor regions has a second doping level greater than the first doping level. A plurality of polysilicon regions (202-1, 202-2, 204-1, 204-2; 302-1, 302-2, 304-1, 304-2) arranged on the plurality of semiconductor regions forms a plurality of ballast resistors. The polysilicon regions are respectively connected to the semiconductor regions, which are degenerated below said polysilicon regions so as to create an additional resistivity. The plurality of semiconductor regions constitutes a drain region of a metal-oxide semiconductor field-effect transistor (MOSFET).
摘要翻译：一种集成电路，包括具有第一掺杂水平的阱区（156）和注入阱区中的多个半导体区（154）。多个半导体区域中的每一个具有大于第一掺杂水平的第二掺杂水平。布置在所述多个半导体区域上的多个多晶硅区域（202-1,202-2,204-1,204-2; 302-1,302-2,304-1,304-2）形成多个镇流器电阻器。多晶硅区域分别连接到半导体区域，半导体区域在所述多晶硅区域下方退化，从而产生附加的电阻率。多个半导体区域构成金属氧化物半导体场效应晶体管（MOSFET）的漏极区域。

7. 发明申请

WO2012054711A3 POWER/GROUND LAYOUT FOR CHIPS 审中-公开
标题翻译：电源/接地布局
公开(公告)号：WO2012054711A3
公开(公告)日：2012-06-14
申请号：PCT/US2011057069
申请日：2011-10-20
申请人： MARVELL WORLD TRADE LTD , SUTARDJA SEHAT , HAN CHUNG CHYUNG , LI WEIDAN , YU SHUHUA , CHENG CHUAN-CHENG , WU ALBERT
发明人： SUTARDJA SEHAT , HAN CHUNG CHYUNG , LI WEIDAN , YU SHUHUA , CHENG CHUAN-CHENG , WU ALBERT
IPC分类号： H01L23/522 , H01L21/98 , H01L23/50 , H01L23/528 , H01L25/065
CPC分类号： H01L21/76885 , H01L23/3107 , H01L23/5226 , H01L23/5286 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05624 , H01L2224/05647 , H01L2224/061 , H01L2224/16145 , H01L2224/16245 , H01L2224/45111 , H01L2224/45116 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48247 , H01L2224/48624 , H01L2224/48647 , H01L2224/48724 , H01L2224/48747 , H01L2224/48824 , H01L2224/48847 , H01L2224/731 , H01L2224/85 , H01L2225/0651 , H01L2225/06513 , H01L2225/06527 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： Embodiments of the present disclosure provide a chip that comprises a base metal layer (102) formed over a first semiconductor die (104) and a first metal layer (110) formed over the base metal layer. The first metal layer includes a plurality of islands (112) configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer (118) formed over the first metal layer. The second metal layer includes a plurality of islands (120) configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.
摘要翻译：本公开的实施例提供一种芯片，其包括形成在第一半导体管芯（104）上的基底金属层（102）和形成在基底金属层上的第一金属层（110）。第一金属层包括配置成路由芯片中的（i）接地信号或（ii）功率信号中的至少一个的多个岛（112）。芯片还包括形成在第一金属层上的第二金属层（118）。第二金属层包括多个岛（120），其配置成路由（i）地面信号或（ii）芯片中的功率信号中的至少一个。

8. 发明申请

WO2009029643A3 DYNAMIC CORE SWITCHING 审中-公开
标题翻译：动态芯切换
公开(公告)号：WO2009029643A3
公开(公告)日：2009-12-30
申请号：PCT/US2008074416
申请日：2008-08-27
申请人： MARVELL WORLD TRADE LTD , SUTARDJA SEHAT , CHEN HONG-YI , SAKARDA PREMANAND , FULLERTON MARK N , HEEB JAY
发明人： SUTARDJA SEHAT , CHEN HONG-YI , SAKARDA PREMANAND , FULLERTON MARK N , HEEB JAY
IPC分类号： G06F1/32
CPC分类号： G06F1/3293 , G06F1/3203 , G06F1/3287 , G06F1/329 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/38 , G06F9/3885 , G06F9/461 , G06F9/4856 , G06F9/4893 , Y02B60/121 , Y02B60/1282 , Y02B60/144 , Y02B60/162 , Y02B60/32 , Y02D10/122 , Y02D10/171 , Y02D10/24 , Y02D10/32 , Y02D50/20
摘要： A system includes a first asymmetric core, a second asymmetric core, and a core switching module. The first asymmetric core executes an application when the system operates in a first mode and is inactive when the system operates in a second mode. The second asymmetric core executes the application when the system operates in the second mode. The core switching module switches operation of the system between the first mode and the second mode. The core switching module selectively stops processing of the application by the first asymmetric core after receiving a first control signal. The core switching module transfers a first state of the first asymmetric core to the second asymmetric core. The second asymmetric core resumes executing the application in the second mode.
摘要翻译：系统包括第一不对称核心，第二非对称核心和核心交换模块。当系统以第一模式操作时，第一非对称核执行应用，并且当系统以第二模式操作时，该状态不活动。当系统以第二模式运行时，第二个非对称核心执行应用程序。核心交换模块在第一模式和第二模式之间切换系统的操作。核心交换模块在接收到第一控制信号之后选择性地停止第一非对称核心处理应用程序。核心交换模块将第一不对称核心的第一状态传送到第二不对称核心。第二非对称核心在第二模式中恢复执行应用程序。

9. 发明申请

WO2008085501A4 TIME UPDATING AND LOAD MANAGEMENT SYSTEMS 审中-公开
标题翻译：时间更新和负载管理系统
公开(公告)号：WO2008085501A4
公开(公告)日：2009-01-08
申请号：PCT/US2007026388
申请日：2007-12-28
申请人： MARVELL WORLD TRADE LTD , SUTARDJA SEHAT
发明人： SUTARDJA SEHAT
IPC分类号： G08C19/00
CPC分类号： G08C19/00
摘要： A master generator that updates time data of remote devices comprises an acquisition module, a clock module, an encoding module, and a transmission module. The acquisition module acquires time data representing current time of day. The clock module receives and stores the time data from the acquisition module and periodically updates the time data. The encoding module encodes the time data from the clock module into time messages. The transmission module selectively superimposes the time messages onto a power signal.
摘要翻译：更新远程设备的时间数据的主发生器包括采集模块，时钟模块，编码模块和传输模块。采集模块获取代表当前时间的时间数据。时钟模块接收并存储来自采集模块的时间数据并周期性地更新时间数据。编码模块将来自时钟模块的时间数据编码成时间消息。传输模块选择性地将时间消息叠加到功率信号上。

10. 发明申请

WO2008048644A3 CRYSTAL OSCILLATOR EMULATOR 审中-公开
标题翻译：晶体振荡器仿真器
公开(公告)号：WO2008048644A3
公开(公告)日：2008-09-25
申请号：PCT/US2007022168
申请日：2007-10-17
申请人： MARVELL WORLD TRADE LTD , SUTARDJA SEHAT
发明人： SUTARDJA SEHAT
IPC分类号： H03B5/30 , H03L1/02
CPC分类号： H03B5/30 , H03L1/026 , H03L7/07 , H03L7/197 , H03L7/1976
摘要： An integrated circuit comprises a microelectromechanical (MEMS) resonator circuit that generates a reference frequency. A temperature sensor senses a temperature of the integrated circuit. Memory stores calibration parameters and selects at least one of the calibration parameters as a function of the sensed temperature. A phase locked loop module receives the reference signal, comprises a feedback loop having a feedback loop parameter and selectively adjusts the feedback loop parameter based on the at least one of the calibration parameters.
摘要翻译：集成电路包括产生参考频率的微机电（MEMS）谐振器电路。温度传感器感测集成电路的温度。存储器存储校准参数，并根据检测到的温度选择至少一个校准参数。锁相环模块接收参考信号，包括具有反馈回路参数的反馈回路，并基于至少一个校准参数选择性地调节反馈回路参数。

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