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1. 发明申请

WO2005064614A1 NON-VOLATILE FERROELECTRIC THIN FILM DEVICE USING AN ORGANIC AMBIPOLAR SEMICONDUCTOR AND METHOD FOR PROCESSING SUCH A DEVICE 审中-公开
标题翻译：使用有机环形半导体的非挥发性薄膜薄膜器件及其处理方法
公开(公告)号：WO2005064614A1
公开(公告)日：2005-07-14
申请号：PCT/IB2004/052613
申请日：2004-12-01
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , GELINCK, Gerwin, H. , MARSMAN, Albert, W. , TOUWSLAGER, Fredericus, J. , DE LEEUW, Dagobert, M.
发明人： GELINCK, Gerwin, H. , MARSMAN, Albert, W. , TOUWSLAGER, Fredericus, J. , DE LEEUW, Dagobert, M.
IPC分类号： G11C11/22
CPC分类号： H01L27/281 , B82Y10/00 , G11C11/22 , H01L21/28291 , H01L29/516 , H01L29/6684 , H01L29/78391
摘要： A non-volatile ferroelectric memory device is proposed which comprises a combination of an organic ferroelectric polymer with an organic ambipolar semiconductor. The devices of the present invention are compatible with - and fully exploit the benefits of polymers, i.e. solution processing, low-cost, low temperature layer deposition and compatibility with flexible substrates.
摘要翻译：提出了一种非挥发性铁电存储器件，其包括有机铁电聚合物与有机双极半导体的组合。本发明的装置与 - 并充分利用聚合物的优点，即溶液处理，低成本，低温层沉积和与柔性基底的相容性相容。

2. 发明申请

WO2005064681A2 METHOD FOR THE MANUFACTURE OF A NON-VOLATILE FERROELECTRIC MEMORY DEVICE AND MEMORY DEVICE THUS OBTAINED 审中-公开
标题翻译：制造非易失性电磁存储器件的方法和获得的存储器件
公开(公告)号：WO2005064681A2
公开(公告)日：2005-07-14
申请号：PCT/IB2004/052580
申请日：2004-11-29
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MARSMAN, Albert, W. , DE LEEUW, Dagobert, M. , GELINCK, Gerwin, H.
发明人： MARSMAN, Albert, W. , DE LEEUW, Dagobert, M. , GELINCK, Gerwin, H.
IPC分类号： H01L27/115
CPC分类号： H01L27/1052 , H01L21/0212 , H01L21/3127 , H01L21/31691 , H01L27/11502 , H01L27/11507 , H01L27/1255 , H01L28/55 , H01L51/0037 , H01L51/0055 , H01L51/052
摘要： The present invention relates to non-volatile ferroelectric memory devices (30) comprising a transistor (22) and a capacitor (23), and more particularly to non-volatile electrically erasable programmable ferroelectric memory elements, and a method for processing such non-volatile ferroelectric memory devices (30). The method according to the invention comprises a limited number of mask steps because a gate dielectric layer of the transistor (22) and a dielectric layer of the capacitor (23) are made from the same organic or inorganic ferroelectric layer (14).
摘要翻译：本发明涉及包括晶体管（22）和电容器（23）的非挥发性铁电存储器件（30），更具体地涉及非易失性电可擦除可编程铁电存储元件，以及用于处理非易失性铁电存储器件（30）。根据本发明的方法包括有限数量的掩模步骤，因为晶体管（22）的栅极电介质层和电容器（23）的电介质层由相同的有机或无机铁电层（14）制成。

3. 发明申请

WO2005064705A1 INCREASING THE WETTABILITY OF POLYMER SOLUTIONS TO BE DEPOSITED ON HYDROPHOBIC FERROELECRIC POLYMERB LAYERS 审中-公开
标题翻译：增加聚合物溶液在疏水性高分子聚合物层上沉积的可湿性
公开(公告)号：WO2005064705A1
公开(公告)日：2005-07-14
申请号：PCT/IB2004/052799
申请日：2004-12-14
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MARSMAN, Albert, W. , TOUWSLAGER, Fredericus, J.
发明人： MARSMAN, Albert, W. , TOUWSLAGER, Fredericus, J.
IPC分类号： H01L51/40
CPC分类号： B82Y10/00 , H01L21/0212 , H01L21/02282 , H01L21/02348 , H01L21/3127 , H01L51/0003 , H01L51/0037
摘要： The present invention to a method for depositing a conductive polymer layer onto a hydrophobic polymer layer and the devices thus obtained. Deposition of a conductive polymer layer onto a hydrophobic polymer layer is not trivial, because the hydrophobic polymer possess poor wetting properties and have low adhesion to other materials. To overcome this problem, a surface tension reducing agent is added to the solution from which the conductive polymer layer is then deposited. The method of the present invention may be used for processing all-polymer devices such as all-polymer transistors, all-polymer capacitors, etc.
摘要翻译：本发明涉及一种在疏水性聚合物层上沉积导电聚合物层的方法和由此获得的器件。导电聚合物层沉积在疏水聚合物层上并不是微不足道的，因为疏水性聚合物具有差的润湿性能并且对其它材料具有低粘附性。为了克服这个问题，将表面张力降低剂添加到然后沉积导电聚合物层的溶液中。本发明的方法可用于加工全聚合物器件，例如全聚合物晶体管，全聚合物电容器等。

4. 发明申请

WO2006051455A1 MEMORY INTEGRATED CIRCUIT 审中-公开
标题翻译：内存集成电路
公开(公告)号：WO2006051455A1
公开(公告)日：2006-05-18
申请号：PCT/IB2005/053604
申请日：2005-11-04
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN ACHT, Victor, M., G. , MARSMAN, Albert, W. , CHONG, Boon, K. , LAMBERT, Nicolaas , WOERLEE, Pierre, H. , IKKINK, Teunis, J.
发明人： VAN ACHT, Victor, M., G. , MARSMAN, Albert, W. , CHONG, Boon, K. , LAMBERT, Nicolaas , WOERLEE, Pierre, H. , IKKINK, Teunis, J.
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1036 , G11C7/1063 , G11C11/56
摘要： A memory integrated circuit contains a sensing circuit (12) that receives signals from addressed memory cells. The sensing circuit determines in which of a number of ranges the signals fall, the number of ranges being greater than the number values to which the cells can be programmed. An output circuit is provided that is arranged to supply either only data words that have been inferred from the detection, or also further information that provides more information about the ranges that have been detected than the data words only. Dependent on a control signal from external terminals of the memory integrated circuit the output circuit supplies the data words only to the external terminals or also the further information about the detected ranges in addition to the data words.
摘要翻译：存储器集成电路包含从寻址的存储器单元接收信号的感测电路（12）。感测电路确定信号下降的范围中的哪一个，范围的数量大于可以编程单元的数字值。提供了一种输出电路，其被布置为仅提供从检测中推断出的数据字，或者还提供了与仅数据字相比已经被检测的范围的更多信息的其他信息。取决于来自存储器集成电路的外部端子的控制信号，输出电路仅将数据字提供给外部端子，或者除了数据字之外还提供关于检测范围的进一步信息。

5. 发明申请

WO2006095278A1 DRIVING OF A MEMORY MATRIX OF RESISTANCE HYSTERESIS ELEMENTS 审中-公开
标题翻译：驱动电阻滞后元件的记忆矩阵
公开(公告)号：WO2006095278A1
公开(公告)日：2006-09-14
申请号：PCT/IB2006/050617
申请日：2006-02-28
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , IKKINK, Teunis, J. , WOERLEE, Pierre, H. , VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , MARSMAN, Albert, W.
发明人： IKKINK, Teunis, J. , WOERLEE, Pierre, H. , VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , MARSMAN, Albert, W.
IPC分类号： G11C16/02
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/0028 , G11C2213/15 , G11C2213/72
摘要： A memory matrix (10) comprises rows and columns of cells, each cell comprising a resistance hysteresis element (24) and a threshold element (22) coupled in series between a row terminal and a column terminal of the cell (20). The resistance hysteresis element (24) has a mutually larger and smaller hysteresis thresholds of mutually opposite polarity respectively. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform read actions. These voltage differences have a read polarity so that the voltage across the cell (20) is in a direction corresponding to the larger hysteresis threshold. Voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform erase actions, all cells (20) of a selected row being erased collectively in the erase action. The voltage differences for erase actions have the read polarity. Furthermore voltage differences are applied between the column terminals and the row terminals of cells (20) in a selected row, so as to perform write actions. The voltage differences for the write actions have a write polarity corresponding to the smaller hysteresis threshold, for updating cells (20) that are selected dependent on write data.
摘要翻译：存储器矩阵（10）包括单元的行和列，每个单元包括串联耦合在单元（20）的行端子和列端子之间的电阻滞后元件（24）和阈值元件（22）。电阻滞后元件（24）分别具有相互相反极性的相互较大和较小的滞后阈值。电压差在列选择行中的单元（20）的列端子和行端子之间施加，以便执行读取动作。这些电压差具有读取极性，使得电池（20）两端的电压处于对应于较大滞后阈值的方向。电压差在列选择行中的单元（20）的列端子和行端子之间施加，以便执行擦除动作，所选行的所有单元（20）在擦除动作中被共同擦除。擦除动作的电压差具有读取极性。此外，在列端子和选定行中的单元（20）的行端子之间施加电压差，以便执行写入动作。写入动作的电压差具有对应于较小滞后阈值的写入极性，用于更新根据写入数据选择的单元（20）。

6. 发明申请

WO2005064653A1 METHOD FOR PATTERNING A FERROELECTRIC POLYMER LAYER 审中-公开
标题翻译：用于描绘电介质聚合物层的方法
公开(公告)号：WO2005064653A1
公开(公告)日：2005-07-14
申请号：PCT/IB2004/052688
申请日：2004-12-07
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MARSMAN, Albert, W. , WILLARD, Nicolaas, P.
发明人： MARSMAN, Albert, W. , WILLARD, Nicolaas, P.
IPC分类号： H01L21/02
CPC分类号： H01L21/0212 , H01L21/02282 , H01L21/02348 , H01L21/28291 , H01L21/31133 , H01L21/3127 , H01L27/11507 , H01L28/55
摘要： Ferroelectric polymers such as for example copolymers of vinylidenedifluoride (VDF) and trifluoroethylene (TrFE) may be patterned by spincoating the ferroelectric polymer layer from a ferroelectric spincoating solution, which comprises a photosensitive crosslinker, onto a substrate followed by irradiating the ferroelectric polymer layer through a mask and removing the unexposed parts of the ferroelectric polymer layer.
摘要翻译：铁电聚合物，例如二氯乙烯（VDF）和三氟乙烯（TrFE）的共聚物可以通过将铁电聚合物层从包含光敏交联剂的铁电纺丝溶液旋涂在基材上，然后通过一个光致聚合物层掩模并除去铁电聚合物层的未曝光部分。

7. 发明申请

WO2005124787A3 ELECTRICAL DEVICE HAVING A PROGRAMMABLE RESISTOR CONNECTED IN SERIES TO A PUNCH-THROUGH DIODE AND METHOD OF MANUFACTURING THEREFOR 审中-公开
公开(公告)号：WO2005124787A3
公开(公告)日：2005-12-29
申请号：PCT/IB2005/051893
申请日：2005-06-09
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , WOERLEE, Pierre, H. , WIDDERSHOVEN, Franciscus, P. , VAN ACHT, Victor, M., G. , IKKINK, Teunis, J. , LAMBERT, Nicolaas , MARSMAN, Albert, W.
发明人： WOERLEE, Pierre, H. , WIDDERSHOVEN, Franciscus, P. , VAN ACHT, Victor, M., G. , IKKINK, Teunis, J. , LAMBERT, Nicolaas , MARSMAN, Albert, W.
IPC分类号： G11C16/02
摘要： The present invention relates to an electrical device (Fig. 6) having a programmable resistor (PR) connected in series to a punch-through diode (S). The invention also relates to a method of manufacturing such an electrical device. The method comprises the steps of: providing a stack comprising a first layer of a semiconductor material of a first conductivity type arranged between a second layer and a third layer of a semiconductor material of a second conductivity type opposite to the first conductivity type, and providing a layer of material having a programmable resistivity, the layer of material having the programmable resistivity being in electrical contact with one of the second and third layer of the semiconductor material.

8. 发明申请

WO2006030362A1 OVERVOLTAGE PROTECTION DEVICE AND RADIO FREQUENCY RECEIVER AND RADIO FREQUENCY IDENTIFICATION TAG COMPRISING SUCH A DEVICE 审中-公开
标题翻译：覆盖保护设备和无线电频率接收器以及包含这种设备的无线电频率标识
公开(公告)号：WO2006030362A1
公开(公告)日：2006-03-23
申请号：PCT/IB2005/052960
申请日：2005-09-09
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , CANTATORE, Eugenio , MARSMAN, Albert, W. , GELINCK, Gerwin
发明人： CANTATORE, Eugenio , MARSMAN, Albert, W. , GELINCK, Gerwin
IPC分类号： G06K19/07
CPC分类号： G06K19/0701 , G06K19/0715 , G06K19/0723
摘要： An overvoltage protection device on a radio frequency identification tag or in a radio frequency receiver comprises electro-magnetic coupling means between a base station and the radio frequency identification tag or radio frequency receiver. At least one ferroelectric capacitor is electrically connected to the coupling means. As long as the voltage across the ferroelectric capacitor remains below its coercive voltage, its capacitance will be linear and the tag or radio frequency receiver will behave normally. However, if the voltage across the ferroelectric capacitor exceeds the coercive voltage, the ferroelectric capacitance will experience polarization reversal and exhibit its non-linear and dissipative behavior. Connecting the ferroelectric capacitor in suitable ways to the coupling means will result in dumping of the voltage transferred to the electronics present on the tag or in the radio frequency receiver. As a result, the electronics is protected against excessive voltages that could cause damage thereto.
摘要翻译：射频识别标签或射频接收机中的过电压保护装置包括基站与射频识别标签或射频接收机之间的电磁耦合装置。至少一个铁电电容器电连接到耦合装置。只要铁电电容器两端的电压保持低于其矫顽电压，其电容将是线性的，并且标签或射频接收器将表现正常。然而，如果铁电电容器两端的电压超过矫顽电压，则铁电电容将经历极化反转并呈现其非线性和耗散性能。将铁电电容器以适当的方式连接到耦合装置将导致转移到存在于标签上或射频接收器中的电子装置的电压。因此，电子器件可以防止可能对其造成损害的过大电压。

9. 发明申请

WO2006095295A1 CONTROL OF A MEMORY MATRIX WITH RESISTANCE HYSTERESIS ELEMENTS 审中-公开
标题翻译：具有电阻HYSTERESIS元件的记忆矩阵的控制
公开(公告)号：WO2006095295A1
公开(公告)日：2006-09-14
申请号：PCT/IB2006/050672
申请日：2006-03-03
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , IKKINK, Teunis, J. , WOERLEE, Pierre, H. , VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , MARSMAN, Albert, W.
发明人： IKKINK, Teunis, J. , WOERLEE, Pierre, H. , VAN ACHT, Victor, M., G. , LAMBERT, Nicolaas , MARSMAN, Albert, W.
IPC分类号： G11C16/02
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2213/72
摘要： A control circuit (1, 11) for a memory matrix is used that defines a write process that uses circuit state transitions between at least two idle circuit states, an all column update circuit state and a column selective update state. In the second . During access the control circuit switches back and forth to the column selective update state (W) from the first idle state (II) during execution of a column selective update command and back and forth to the all-column update state (E) from the second idle state (12) during execution of an all column update command. The control circuit (1, 11) is retained in the first and second idle state (II, 12) , without switching to the second and first idle state (12, II) between execution of successive column selective update commands and all column update commands respectively.
摘要翻译：使用用于存储矩阵的控制电路（1,11），其定义了在至少两个空闲电路状态，全列更新电路状态和列选择性更新状态之间使用电路状态转换的写入处理。在第二个在访问期间，控制电路在执行列选择性更新命令期间来自第一空闲状态（II）来回切换到列选择性更新状态（W），并且从列选择性更新状态（E）来回切换到全列更新状态在执行全部列更新命令期间的第二空闲状态（12）。控制电路（1,11）被保持在第一和第二空闲状态（II，12）中，而在连续列选择性更新命令的执行和所有列更新命令之间没有切换到第二和第一空闲状态（12，II）分别。

10. 发明申请

WO2005101207A1 DATA HANDLING DEVICE THAT CORRECTS ERRORS IN A DATA MEMORY 审中-公开
标题翻译：数据处理设备，用于校正数据存储器中的错误
公开(公告)号：WO2005101207A1
公开(公告)日：2005-10-27
申请号：PCT/IB2005/051106
申请日：2005-04-04
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN ACHT, Victor, M., G. , MARSMAN, Albert, W. , CHONG, Boon, K. , LAMBERT, Nicolaas , WOERLEE, Pierre, H. , IKKINK, Teunis, J.
发明人： VAN ACHT, Victor, M., G. , MARSMAN, Albert, W. , CHONG, Boon, K. , LAMBERT, Nicolaas , WOERLEE, Pierre, H. , IKKINK, Teunis, J.
IPC分类号： G06F11/10
CPC分类号： G06F11/1008
摘要： A data handling device is provided with a data memory (10) with an address input and a data output, for outputting multi-bit words. The data memory (10) has a structure that gives rise to potential errors at correlated positions in words from a group of words. An erasure memory unit (16) stores bit position information associated with a group of the words, and outputs the bit position information when a word from the group for which bit position information is stored is addressed in the data memory (10). An error correction and detection unit (12) is arranged to correct words from the data memory (10), using error erasure for bits at bit positions selected by the bit position information from the erasure memory unit (16) for the groups to which the words belong.
摘要翻译：数据处理装置具有用于输出多位字的地址输入和数据输出的数据存储器（10）。数据存储器（10）具有在一组单词中产生相关位置上的潜在错误的结构。擦除存储器单元（16）存储与一组字相关联的位位置信息，并且当来自存储位位置信息的组中的字被寻址到数据存储器（10）中时，输出位位置信息。错误校正和检测单元（12）被布置为使用对来自擦除存储器单元（16）的位位置信息选择的比特位置处的比特的错误擦除来校正来自数据存储器（10）的单词，词属于

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