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1. 发明申请

WO2008094626A8 COMMON-MODE INSENSITIVE SAMPLER 审中-公开
公开(公告)号：WO2008094626A8
公开(公告)日：2008-11-06
申请号：PCT/US2008001263
申请日：2008-01-29
申请人： KENET INC , KUSHNER LAWRENCE J , ANTHONY MICHAEL P , FISHER JOHN S
发明人： KUSHNER LAWRENCE J , ANTHONY MICHAEL P , FISHER JOHN S
IPC分类号： H03M1/34
CPC分类号： H03M1/0636 , H03M1/1245
摘要： An approach to rejecting input common-mode voltage variations in a sampler/converter that avoids the use of a differential amplifier in the signal path, and without introducing added distortion or noise. In one embodiment, the input common-mode variations are sensed on a pair of matched resistors that straddle the common mode analog inputs, on a node 'Vcmi'. An alternative, switched-capaci tor- based sensing scheme is also possible. Using this measured Vcmi, adjustments are then made to the rest of the sampler/converter to take out any variations observed at Vcmi.

2. 发明申请

WO2008094626A3 COMMON-MODE INSENSITIVE SAMPLER 审中-公开
标题翻译：共模不敏感采样器
公开(公告)号：WO2008094626A3
公开(公告)日：2008-09-25
申请号：PCT/US2008001263
申请日：2008-01-29
申请人： KENET INC , KUSHNER LAWRENCE J , ANTHONY MICHAEL P , FISHER JOHN S
发明人： KUSHNER LAWRENCE J , ANTHONY MICHAEL P , FISHER JOHN S
IPC分类号： H03M1/34
CPC分类号： H03M1/0636 , H03M1/1245
摘要： An approach to rejecting input common-mode voltage variations in a sampler/converter that avoids the use of a differential amplifier in the signal path, and without introducing added distortion or noise. In one embodiment, the input common-mode variations are sensed on a pair of matched resistors that straddle the common mode analog inputs, on a node 'Vcmi'. An alternative, switched-capaci tor- based sensing scheme is also possible. Using this measured Vcmi, adjustments are then made to the rest of the sampler/converter to take out any variations observed at Vcmi.
摘要翻译：一种在采样器/转换器中抑制输入共模电压变化的方法，避免在信号路径中使用差分放大器，并且不会引入额外的失真或噪声。在一个实施例中，在节点'Vcmi'上在跨越共模模拟输入的一对匹配电阻器上感测输入共模变化。另一种基于开关电容的感测方案也是可能的。使用这个测量的Vcmi，然后对采样器/转换器的其余部分进行调整，以取出在Vcmi处观察到的任何变化。

3. 发明申请

WO2006009966A3 DEVICE FOR SUBTRACTING/ADDING A CONSTANT AMOUNT OF CHARGE IN A CHARGE-COUPLED DEVICE 审中-公开
标题翻译：用于在充电耦合器件中放置/添加恒定电量的装置
公开(公告)号：WO2006009966A3
公开(公告)日：2006-05-04
申请号：PCT/US2005021688
申请日：2005-06-20
申请人： KENET INC , KUSHNER LAWRENCE J , ANTHONY MICHAEL P , KOHLER EDWARD
发明人： KUSHNER LAWRENCE J , ANTHONY MICHAEL P , KOHLER EDWARD
IPC分类号： G11C19/28 , H01L27/148
CPC分类号： G11C19/282 , G11C19/287 , H01L27/14806
摘要： A circuit for adding or subtracting an amount of charge from a charge sample, such as in a Charge Coupled Device (CCD), by portioning and pipelining the processing stages, to avoid introducing a memory effect. The operation, such as subtraction, is split into multiple stages, with each stage responsible for removing only a portion of the total amount of charge that is desired to be removed. The subtraction pipeline stages operate together to remove the total desired charge amount. In one embodiment each successive subtraction stage removes a corresponding lesser amount of charge. As a result, greater accuracy in the amount of charge removed is achieved as well operation at higher frequencies than previous charge subtraction approaches.
摘要翻译：一种用于通过分配和流水线处理级来从电荷样本（例如电荷耦合器件（CCD））中增加或减少电荷量的电路，以避免引入记忆效应。诸如减法的操作被分成多个阶段，每个阶段负责仅去除期望被移除的总计费用的一部分。减法流水线段一起工作，以消除总的所需电荷量。在一个实施例中，每个连续的减法阶段去除相应较少量的电荷。结果，除了先前的电荷减法方法之外，在更高的频率下也实现更高的去除电荷量的精度。

4. 发明申请

WO2006014558A9 VOLTAGE RANDOM ACCESS MEMORY (VRAM) 审中-公开
标题翻译：电压随机存取存储器（VRAM）
公开(公告)号：WO2006014558A9
公开(公告)日：2007-03-08
申请号：PCT/US2005024137
申请日：2005-07-06
申请人： KENET INC , ANTHONY MICHAEL P , KUSHNER LAWRENCE J
发明人： ANTHONY MICHAEL P , KUSHNER LAWRENCE J
IPC分类号： H03M1/78 , H03M7/00
CPC分类号： H03M1/785 , G11C7/02 , G11C7/16 , G11C11/412 , G11C11/413 , G11C27/00 , H03M1/1009 , H03M1/662 , H03M1/682 , H03M1/76 , H03M1/765
摘要： An integrated circuit memory cell and voltage ladder design that adapts techniques typically applied to Static Random Access Memory (SRAM) circuits to implement a compact array of analog Voltage Random Access Memory (VRAM) locations. The memory cells in the VRAM each store a digital value that controls a corresponding switch. The switch couple a particular voltage from a set of voltages generated by the ladder, to be output when that location is enabled. Multiple analog output voltages are provided by simply providing additional rows of cells.
摘要翻译：集成电路存储单元和电压梯形图设计，适应通常应用于静态随机存取存储器（SRAM）电路的技术，以实现紧凑型模拟电压随机存取存储器（VRAM）阵列。 VRAM中的存储单元存储控制相应开关的数字值。该开关从梯形图产生的一组电压耦合特定电压，以在该位置被使能时被输出。通过简单地提供额外的单元行来提供多个模拟输出电压。

5. 发明申请

WO2006104578A2 MANUFACTURING CCDS IN A CONVENTIONAL CMOS PROCESS 审中-公开
标题翻译：制作常规CMOS工艺中的CCD
公开(公告)号：WO2006104578A2
公开(公告)日：2006-10-05
申请号：PCT/US2006004799
申请日：2006-02-09
申请人： KENET INC , SOLLNER GERHARD , KUSHNER LAWRENCE J , ANTHONY MICHAEL P , KOHLER EDWARD , GRANT WESLEY
发明人： SOLLNER GERHARD , KUSHNER LAWRENCE J , ANTHONY MICHAEL P , KOHLER EDWARD , GRANT WESLEY
IPC分类号： H01L21/339
CPC分类号： H01L29/66954 , H01L27/14689 , H01L27/14806
摘要： A technique for forming Charge-Coupled Devices (CCDs) in a conventional Complementary Metal Oxide Semiconductor (CMOS) process. A number of single- layer polysilicon gates are formed on an as-grown, native doped silicon substrate, with gaps between them. Masking is used to selectively dope the gates while preventing doping of the silicon in the gaps. Masking may likewise be used to selectively silicide the gates while preventing suicide formation in the gaps. Conventional source-drain processing produces input/output diffusions for the CCD.
摘要翻译：在常规互补金属氧化物半导体（CMOS）工艺中形成电荷耦合器件（CCD）的技术。在生长的天然掺杂硅衬底上形成多个单层多晶硅栅极，它们之间有间隙。掩蔽用于选择性地掺杂栅极，同时防止硅在间隙中的掺杂。同样可以使用掩蔽来选择性地硅化栅极，同时防止间隙中的自杀形成。常规的源极 - 漏极处理产生CCD的输入/输出扩散。

6. 发明申请

WO2006014558A2 VOLTAGE RANDOM ACCESS MEMORY (VRAM) 审中-公开
标题翻译：电压随机存取存储器（VRAM）
公开(公告)号：WO2006014558A2
公开(公告)日：2006-02-09
申请号：PCT/US2005024137
申请日：2005-07-06
申请人： KENET INC , ANTHONY MICHAEL P , KUSHNER LAWRENCE J
发明人： ANTHONY MICHAEL P , KUSHNER LAWRENCE J
IPC分类号： H03M7/00
CPC分类号： H03M1/785 , G11C7/02 , G11C7/16 , G11C11/412 , G11C11/413 , G11C27/00 , H03M1/1009 , H03M1/662 , H03M1/682 , H03M1/76 , H03M1/765
摘要： An integrated circuit memory cell and voltage ladder design that adapts techniques typically applied to Static Random Access Memory (SRAM) circuits to implement a compact array of analog Voltage Random Access Memory (VRAM) locations. The memory cells in the VRAM each store a digital value that controls a corresponding switch. The switch couple a particular voltage from a set of voltages generated by the ladder, to be output when that location is enabled. Multiple analog output voltages are provided by simply providing additional rows of cells.
摘要翻译：集成电路存储单元和电压梯形图设计，适应通常应用于静态随机存取存储器（SRAM）电路的技术，以实现紧凑型模拟电压随机存取存储器（VRAM）阵列。 VRAM中的存储单元存储控制相应开关的数字值。该开关从梯形图产生的一组电压耦合特定电压，以在该位置被使能时被输出。通过简单地提供额外的单元行来提供多个模拟输出电压。

7. 发明申请

WO2006009896A3 ANALOG TO DIGITAL CONVERTER CALIBRATION VIA SYNCHRONOUS DEMODULATION 审中-公开
标题翻译：通过同步解调模拟数字转换器校准
公开(公告)号：WO2006009896A3
公开(公告)日：2007-11-08
申请号：PCT/US2005021568
申请日：2005-06-17
申请人： KENET INC , KUSHNER LAWRENCE J , ANTHONY MICHAEL P
发明人： KUSHNER LAWRENCE J , ANTHONY MICHAEL P
IPC分类号： H03M1/10
CPC分类号： H03M1/1061 , H03M1/0682 , H03M1/44
摘要： A technique for dynamically calibrating a successive approximation charge to digital converter by toggling at least some portion of the converter between two predetermined states, with the design goal of balancing the voltage and/or charge that is output in the two states. The two states are chosen such that they are expected to generate the same output voltage when the converter is in "normal" operation mode, e.g., within a fraction of the Least Significant Bit (LSB) resolution of the converter. If there is an imbalance, switching between the two calibration states invariably generates a square wave signal that toggles between two distinct values. A synchronous demodulator having a bandwidth centered at the toggle frequency can then be used to accurately detect an amount of error, which is then feedback to generate correction signals. If there are undesirable static offsets introduced by the synchronous demodulator or by the signal and/or charge levels output by the two differential halves of the converter, a properly timed latch can be used to further stabilize the error signal.
摘要翻译：通过在两个预定状态之间切换转换器的至少一部分来动态校准逐次逼近电荷到数字转换器的技术，其设计目的是平衡在两种状态下输出的电压和/或电荷。选择这两个状态使得当转换器处于“正常”操作模式时，例如在转换器的最低有效位（LSB）分辨率的一小部分内，它们被期望产生相同的输出电压。如果存在不平衡，则在两个校准状态之间切换总是产生在两个不同值之间切换的方波信号。具有以切换频率为中心的带宽的同步解调器然后可以用于精确地检测误差量，然后反馈以产生校正信号。如果由同步解调器引入不期望的静态偏移或由转换器的两个差分半部输出的信号和/或电荷电平，则可以使用适当定时的锁存器来进一步稳定误差信号。

8. 发明申请

WO2007143073A3 DOPED PLUG FOR CCD GAPS 审中-公开
公开(公告)号：WO2007143073A3
公开(公告)日：2008-03-20
申请号：PCT/US2007012905
申请日：2007-05-31
申请人： KENET INC , WASHKURAK WILLIAM D , ANTHONY MICHAEL P , SOLLNER GERHARD
发明人： WASHKURAK WILLIAM D , ANTHONY MICHAEL P , SOLLNER GERHARD
IPC分类号： H01L21/339 , H01L29/768
CPC分类号： H01L29/768 , G11C19/282 , G11C19/285 , H01L29/66954
摘要： A method and structure of providing a doped plug to improve the performance of CCD gaps is discussed. A highly-doped region is implemented in a semiconductor, aligned beneath a gap. The plug provides a highly-conductive region at the semiconductor surface, therefore preventing the development of a region where potential is significantly influenced by surface charges.
摘要翻译：讨论了提供掺杂插塞以提高CCD间隙性能的方法和结构。在半导体中实现高掺杂区域，在间隙下对齐。插头在半导体表面提供了高导电性区域，因此防止了电位受到表面电荷的显着影响的区域的发展。

9. 发明申请

WO2006014500A2 A CHARGE COMPARATOR WITH LOW INPUT OFFSET 审中-公开
标题翻译：具有低输入偏置的电荷比较器
公开(公告)号：WO2006014500A2
公开(公告)日：2006-02-09
申请号：PCT/US2005024007
申请日：2005-07-06
申请人： KENET INC , DEMIRDAG CUNEYT , ANTHONY MICHAEL P
发明人： DEMIRDAG CUNEYT , ANTHONY MICHAEL P
IPC分类号： H03M1/12
CPC分类号： H03F3/45475 , G11C19/285 , G11C27/02 , G11C27/024 , H03F3/45968 , H03F2200/78 , H03F2203/45614 , H03K5/249
摘要： A Direct Current (DC) charge comparator that provides low input offset by feeding complimentary plus and minus charge inputs to a single amplification path via an alternate input path switch. Multiple sample and hold circuits at the output of the amplification path permit comparison of the result when each of the charge inputs travels down each of the paths, to determine a correction.
摘要翻译：直流（DC）电荷比较器，通过将补充和负电荷输入通过备用输入路径开关馈送到单个放大路径来提供低输入偏移。在放大路径的输出处的多个采样和保持电路允许当每个电荷输入沿每个路径向下行进时结果的比较，以确定校正。

10. 发明申请

WO2007143074A3 BOOSTED CHARGE TRANSFER PIPELINE 审中-公开
标题翻译：增压充电管道
公开(公告)号：WO2007143074A3
公开(公告)日：2008-04-03
申请号：PCT/US2007012906
申请日：2007-05-31
申请人： KENET INC , ANTHONY MICHAEL P
发明人： ANTHONY MICHAEL P
IPC分类号： G11C19/18 , G11C7/10 , G11C19/28
CPC分类号： G11C19/186 , G11C19/285
摘要： A charge transfer circuit, such as a charge coupled device or other bucket brigade device, which incorporates an amplifier to assist with charge transfer.
摘要翻译：电荷转移电路，例如电荷耦合器件或其他桶式装置，其结合放大器以辅助电荷转移。

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