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1. 发明申请

WO2015183496A1 HYBRID R-2R STRUCTURE FOR LOW GLITCH NOISE SEGMENTED DAC 审中-公开
标题翻译：混合R-2R结构用于低玻璃噪声分离DAC
公开(公告)号：WO2015183496A1
公开(公告)日：2015-12-03
申请号：PCT/US2015/029535
申请日：2015-05-06
申请人： QUALCOMM INCORPORATED
发明人： LEE, Sang Min , SEO, Dongwon
IPC分类号： H03M1/06 , H03M1/08 , H03M1/68 , H03M1/78
CPC分类号： H03M1/0863 , H03M1/0612 , H03M1/0881 , H03M1/687 , H03M1/785
摘要： The apparatus may be an N-bit DAC including (2M-1) parallel stages associated with M most significant bits, and (N-M) stages associated with (N-M) least significant bits. The (2M-1) parallel stages may deliver a first current to current-summing nodes of the DAC. The (N-M) stages may include a resistive network and a second pair of switches, and may deliver a second current to the resistive network of the stage. Each resistive network may scale the respectively delivered currents according to a binary weight of a stage corresponding to the resistive network, and may deliver the scaled currents to the pair of current-summing nodes. At least one of the (N-M) stages may be separated from the remaining stages.
摘要翻译：该装置可以是包括与M个最高有效位相关联的（2M-1）个并行级和与（N-M）个最低有效位相关联的（N-M）级的N位DAC。（2M-1）并联级可以将第一电流传送到DAC的电流求和节点。（N-M）级可以包括电阻网络和第二对开关，并且可以将第二电流传递到级的电阻网络。每个电阻网络可以根据对应于电阻网络的级的二进制权重来缩放分别传递的电流，并且可以将缩放的电流传送到一对电流求和节点。（N-M）级中的至少一个可以与其余级分离。

2. 发明申请

WO2014150831A1 DUAL-STRING DIGITAL-TO-ANALOG CONVERTERS (DACs), AND RELATED CIRCUITS, SYSTEMS, AND METHODS 审中-公开
标题翻译：双字模数转换器（DAC）及相关电路，系统和方法
公开(公告)号：WO2014150831A1
公开(公告)日：2014-09-25
申请号：PCT/US2014/024352
申请日：2014-03-12
申请人： QUALCOMM INCORPORATED
发明人： PRICE, Burt, L. , SHAH, Dhaval, R. , KOLLA, Yeshwant, Nagaraj
IPC分类号： H03M1/06 , H03M1/68 , H03M1/76
CPC分类号： H03M1/808 , H03M1/002 , H03M1/06 , H03M1/682 , H03M1/76 , H03M1/765 , H03M1/78 , H03M1/785
摘要： Dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a primary voltage divider of the dual string-DAC is comprised of at least one adjusting circuit. The adjusting circuit is configured to maintain the ideal voltage of a selected resistor node pair across a secondary voltage divider circuit in response to a primary switch unit selecting a selected resistor node pair. In this manner, impedance isolation is not required between a primary voltage divider and the secondary voltage divider circuit of the dual-string DAC. As a result, as non-limiting examples, the area on an integrated circuit (IC) for a dual-string DAC may be decreased, power consumption of the DAC may be decreased, and/or the dual-string DAC may have increased performance by not requiring a settling time.
摘要翻译：公开了双串数/模转换器（DAC）及相关电路，系统和方法。在本文公开的实施例中，双串DAC的初级分压器由至少一个调节电路组成。调整电路被配置为响应于主开关单元选择所选择的电阻器节点对，在次级分压器电路上保持所选择的电阻器节点对的理想电压。以这种方式，双串DAC的初级分压器和次级分压器电路之间不需要阻抗隔离。结果，作为非限制性示例，可以减小用于双串DAC的集成电路（IC）上的面积，DAC的功耗可能降低，和/或双串DAC可以具有增加的性能不需要安置时间。

3. 发明申请

WO2013165976A3 SEGMENTED DIGITAL-TO-ANALOG CONVERTER HAVING WEIGHTED CURRENT SOURCES 审中-公开
标题翻译：分段数字 - 模拟转换器具有加权电流源
公开(公告)号：WO2013165976A3
公开(公告)日：2013-12-27
申请号：PCT/US2013038806
申请日：2013-04-30
申请人： ANALOG DEVICES TECHNOLOGY
发明人： MEDINA SANCHEZ-CASTRO ITALO CARLOS
IPC分类号： H03M1/66
CPC分类号： H03M1/785 , H03M1/687 , H03M1/745 , H03M1/765
摘要： A digital input to a digital-to-analog converter (DAC) is divided into a most significant portion and a lesser significant portion. At least one tap voltage generator generates a plurality of voltages, preferably using a resistor string. A decoder decodes at least one subword that forms the lesser significant portion to generate a corresponding at least one control signal. A switching unit accesses voltages generated by the at least one tap voltage generator in response to the at least one control signal. A scaled current generator generates a respective weighted current from each accessed voltage. An output stage combines all the weighted currents with a voltage that is an analog representation of the most significant portion of the digital input to generate an analog approximation of the entire digital input.
摘要翻译：数模转换器（DAC）的数字输入分为最高有效部分和较低有效部分。至少一个抽头电压发生器优选地使用电阻串来产生多个电压。解码器对构成较低有效部分的至少一个子字进行解码以生成对应的至少一个控制信号。切换单元响应于所述至少一个控制信号访问由所述至少一个抽头电压发生器产生的电压。缩放电流生成器从每个访问的电压生成相应的加权电流。输出级将所有加权电流与数字输入最重要部分的模拟表示的电压相结合，以生成整个数字输入的模拟近似值。

4. 发明申请

WO2011081966A2 REDUCED AREA DIGITAL-TO-ANALOG CONVERTER 审中-公开
标题翻译：减少区域数字到模拟转换器
公开(公告)号：WO2011081966A2
公开(公告)日：2011-07-07
申请号：PCT/US2010/060551
申请日：2010-12-15
申请人： TEXAS INSTRUMENTS INCORPORATED , LI, Qunying , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： LI, Qunying
IPC分类号： H03M1/66
CPC分类号： H03M1/785 , H03M1/1061 , H03M1/667 , H03M1/687 , H03M1/808
摘要： One embodiment of the invention includes a digital-to-analog converter (DAC) system (10). A resistive ladder (16) comprises a plurality of resistors (20) having an approximately equal resistance and is arranged in a respective plurality of resistive rungs (18) between first and second ends of the resistive ladder. The first end of the resistive ladder can be coupled to an output and at least a portion of the plurality of resistors between the first end and the second end of the resistive ladder can have a physical size that is descending size-scaled in a direction from the first end of the resistive ladder to the second end of the resistive ladder. A switching circuit (22) is configured to connect each of the plurality of resistive rungs (18) to one of a first voltage and a second voltage based on a binary value of a digital input signal to generate a corresponding analog output voltage at the output.
摘要翻译：本发明的一个实施例包括数模转换器（DAC）系统（10）。电阻梯（16）包括具有大致相等电阻的多个电阻（20），并且布置在电阻梯的第一和第二端之间的相应的多个电阻梯级（18）中。电阻梯的第一端可以耦合到输出，并且电阻梯的第一端和第二端之间的多个电阻的至少一部分可以具有沿着从电阻梯的第一端到电阻梯的第二端。开关电路（22）被配置为基于数字输入信号的二进制值将多个电阻级（18）中的每一个连接到第一电压和第二电压中的一个，以在输出端产生相应的模拟输出电压。

5. 发明申请

WO2008077387A3 DEVICE FOR THE LOW-DISTORTION TRANSFORMATION, PARTICULARLY AMPLIFICATION, OF SIGNALS 审中-公开
标题翻译：装置于形成失真武器，包括增益，信号
公开(公告)号：WO2008077387A3
公开(公告)日：2009-03-05
申请号：PCT/DE2007002301
申请日：2007-12-20
申请人： STRAUSSMANN JUERGEN
发明人： STRAUSSMANN JUERGEN
IPC分类号： H03M1/06 , H03M1/08
CPC分类号： H03M1/0614 , H03M1/0881 , H03M1/661 , H03M1/745 , H03M1/76 , H03M1/785
摘要： The invention describes a device for the low-distortion transformation, particularly amplification, of signals. In one embodiment, the device comprises a digital-to-analog converter having adjustable reference voltages, to which an analog-to-digital converter having adjustable reference voltages may be connected upstream. In a further embodiment, the device has a unit, which predistorts a digitized signal, or a digital signal, corresponding to the transmission characteristic curve of the amplifier. In a further embodiment, the device has a unit, which equalizes a distorted digitized signal corresponding to the transmission characteristic curve of the amplifier stored in the unit. In yet a further embodiment, the device has a digital-to-analog converter operating on the basis of the summation of weighted currents.
摘要翻译：它是用于形成低失真，尤其是增强的信号中描述的装置。在一个实施例中，该装置包括一个D /带可调基准电压A转换器，所述A / D转换器是必需的，上游调节的参考电压。在另一个实施方案中，该装置包括预失真的数字化信号或对应于所述放大器的传递特性的数字信号的单元。在进一步的实施方案中，装置具有均衡对应于存储在所述放大器的所述单位传送特性的数据的失真数字化的信号的单元。在又一实施例中，该装置具有进行动作，其基于加权流的总和一个D / A转换器。

6. 发明申请

WO2006112874A1 IMPROVED TRIM CIRCUITS AND METHODOLOGIES FOR DATA CONVERTERS 审中-公开
标题翻译：改进数据转换器的TRIM电路和方法
公开(公告)号：WO2006112874A1
公开(公告)日：2006-10-26
申请号：PCT/US2005/029653
申请日：2005-08-19
申请人： LINEAR TECHNOLOGY CORPORATION , COPLEY, Patrick, Philip
发明人： COPLEY, Patrick, Philip
IPC分类号： H03M1/10
CPC分类号： H03M1/1057 , H03M1/785
摘要： An improved digital-to-analog converter comprises a reference node, switches providing an input digital signal, and an output stage including at least one resistive element. A resistance ladder, coupled to the switches, includes branches corresponding respectively to bit positions, in which selective operation of the switches in response to the input digital signal produces a corresponding analog output signal from the output stage. The ladder includes a first trim structure coupled to the most significant bit position (MSB) and a second trim structure in the output stage resistive element or elements. The first trim structure is configured to adjust the gain of the converter without affecting the relative bit weights of the bit positions, and wherein the resistances of the first and second trim structures are substantially of a prescribed ratio prior to any trimming.
摘要翻译：改进的数模转换器包括参考节点，提供输入数字信号的开关以及包括至少一个电阻元件的输出级。耦合到开关的电阻梯级包括分别对应于位位置的分支，其中响应于输入数字信号的开关的选择性操作从输出级产生相应的模拟输出信号。梯子包括耦合到最高有效位位置（MSB）的第一微调结构和输出级电阻元件中的第二微调结构。第一调整结构被配置为调整转换器的增益而不影响位位置的相对位权重，并且其中在任何修整之前第一和第二修剪结构的电阻基本上是规定的比率。

7. 发明申请

WO00065719A1 METHOD AND APPARATUS FOR DIGITAL TO ANALOG CONVERTERS WITH IMPROVED SWITCHED R-2R LADDERS 审中-公开
标题翻译：具有改进的开关R-2R梯形图的数字转换器的方法和装置
公开(公告)号：WO00065719A1
公开(公告)日：2000-11-02
申请号：PCT/US1999/028880
申请日：1999-12-02
IPC分类号： H03M1/06 , H03M1/78
CPC分类号： H03M1/06 , H03M1/785
摘要： Operating range of R-2R ladders for digital to analog converters (DACs) is improved by increasing resistance in series with a termination switch in a termination leg to avoid transistor saturation for increasing DAC resolution, increasing reference voltage range, or other application. The switched R-2R ladder circuit is modified to compensate for increasing resistance to maintain proper resistor matching for generation of the appropriate range of analog output voltages for a digital input signal.
摘要翻译：通过增加与终端脚中的终端开关串联的电阻，可以改善数模转换器（DAC）的R-2R梯级的工作范围，以避免晶体管饱和，从而提高DAC分辨率，增加参考电压范围或其他应用。修改开关式R-2R梯形电路以补偿增加的电阻，以保持适当的电阻匹配，以产生数字输入信号的适当范围的模拟输出电压。

8. 发明申请

WO1994015403A1 R/2R DIGITAL TO ANALOG CONVERTER 审中-公开
标题翻译： R / 2R数字到模拟转换器
公开(公告)号：WO1994015403A1
公开(公告)日：1994-07-07
申请号：PCT/EP1993003111
申请日：1993-11-05
申请人： VLSI TECHNOLOGY INC. , VALDENAIRE, Patrick
发明人： VLSI TECHNOLOGY INC.
IPC分类号： H03M01/78
CPC分类号： H03M1/785
摘要： A digital-to-analog converter of the R/2R ladder type is composed of two individually asymmetric ladders (51a, 51b) symmetrically coupled to a differential amplifier (16). Switch means (S1, etc.) in the shunt arms of the ladders are controlled so that the same number of shunt arms is connected to each of a pair of input or output nodes irrespective of the value of the controlling digital signal. The most significant shunt arm in each ladder may be configured as an equivalent (41, 42) of that part of the respective ladder extending from the respective stage node (10) towards the least significant end of the ladder.
摘要翻译： R / 2R梯形类型的数/模转换器由对称地耦合到差分放大器（16）的两个单独的不对称梯（51a，51b）组成。控制梯形分流臂中的开关装置（S1等），使得与一对输入或输出节点中的每一个连接相同数目的分流臂，而与控制数字信号的值无关。每个梯子中最重要的分流臂可以被配置为从相应的舞台节点（10）朝向梯子的最低有效端延伸的相应梯子的该部分的等同物（41,42）。

9. 发明申请

WO9107825A3 TERMINATION CIRCUIT FOR AN R-2R LADDER THAT COMPENSATES FOR TEMPERATURE DRIFT 审中-公开
标题翻译：用于补偿温度漂移的R-2R梯形终端电路
公开(公告)号：WO9107825A3
公开(公告)日：1991-06-27
申请号：PCT/US9006790
申请日：1990-11-19
申请人： ANALOG DEVICES INC
发明人： BROKAW A PAUL
IPC分类号： H03M1/06 , H03M1/08 , H03M1/78
CPC分类号： H03M1/089 , H03M1/785
摘要： A termination circuit for an R-2R ladder network for producing weighted currents, the 2R terminating resistor of the ladder being connected to an excitation source voltage which is 2(kT/q)ln2 closer to the supply voltage than the emitter of the current source in the last (i.e., least significant) leg of the ladder. The excitation source is fabricated with just one type of bipolar transistor and does not require an amplifier or frequency compensation capacitor(s). The excitation source is a simple circuit requiring only five transistors, at least one of which has an emitter area which is a multiple of the emitter areas of the current source transistors. The base-emitter voltages of the transistors in the excitation source are connected in a voltage loop that goes from a voltage VLSB at the emitter of the current source transistor connected to the least significant ladder network shunt resistor to a voltage, Vt, which would be equal to VLSB, if all six transistors in the loop had the same emitter area, but which deviates therefrom by 2(kT/q)ln2 due to the differences in the emitter areas.
摘要翻译：用于产生加权电流的R-2R梯形网络的端接电路，梯形的2R终端电阻连接到比电流源的发射极更接近电源电压的2（kT / q）ln2的激励源电压在阶梯的最后（即最不重要的）阶段。激励源只用一种双极型晶体管制造，不需要放大器或频率补偿电容器。激励源是一个简单的电路，只需要五个晶体管，其中至少一个晶体管的发射极面积是电流源晶体管发射极面积的倍数。激励源中的晶体管的基极 - 发射极电压连接在电压回路中，该电压回路从连接到最低有效梯形网络分流电阻器的电流源晶体管的发射极处的电压VLSB变为电压Vt，等于VLSB，如果回路中的所有六个晶体管具有相同的发射极面积，但由于发射极面积的差异，其偏离2（kT / q）ln2。

10. 发明申请

WO2016040674A1 HYBRID DIGITAL-TO-ANALOG CONVERSION SYSTEM 审中-公开
标题翻译：混合数字到模拟转换系统
公开(公告)号：WO2016040674A1
公开(公告)日：2016-03-17
申请号：PCT/US2015/049480
申请日：2015-09-10
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： SHILL, Mark, Allan
IPC分类号： H03M1/68 , H03M1/06
CPC分类号： H03M1/785 , H03M1/68 , H03M1/765
摘要： In described examples, a digital-to-analog conversion (DAC) circuit (100) has a resistor ladder circuit (130) controlled by high order bits (D[n+l :N]) and a resistor string circuit (110) controlled by low order bits (D[l :n]). The resistor ladder circuit (130) includes a stem resistor (131) and a branch resistor (132). The stem resistor (131) has a stem resistance, and the branch resistor (132) has a branch resistance that is substantially equal to two times of the stem resistance. The resistor string circuit (110) includes a string current source (120), a string resistor (114), and a bridge resistor (117). The string current source (120) is configured to generate a string current that is based on a ratio of a reference voltage divided by a predetermined resistance. The string resistor (114) has a string resistance that corresponds to the predetermined resistance, and it is configured to selectively receive the string current based on a selection signal (143) decoded from the low order bits (D[l :n]).
摘要翻译：在所述示例中，数模转换（DAC）电路（100）具有由高阶位（D [n + 1：N]）控制的电阻梯形电路（130）和控制的电阻串电路通过低阶位（D [l：n]）。电阻梯形电路（130）包括一根杆状电阻（131）和一个分支电阻（132）。干式电阻器（131）具有干电阻，并且分支电阻器（132）具有基本上等于干线电阻的两倍的分支电阻。电阻串电路（110）包括串电流源（120），串电阻（114）和桥电阻（117）。串电流源（120）被配置为产生基于参考电压除以预定电阻的比率的串电流。串电阻（114）具有对应于预定电阻的串电阻，并且其被配置为基于从低位位（D [1：n]）解码的选择信号（143）有选择地接收串电流。

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