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1. 发明申请

WO2006009896A3 ANALOG TO DIGITAL CONVERTER CALIBRATION VIA SYNCHRONOUS DEMODULATION 审中-公开
标题翻译：通过同步解调模拟数字转换器校准
公开(公告)号：WO2006009896A3
公开(公告)日：2007-11-08
申请号：PCT/US2005021568
申请日：2005-06-17
申请人： KENET INC , KUSHNER LAWRENCE J , ANTHONY MICHAEL P
发明人： KUSHNER LAWRENCE J , ANTHONY MICHAEL P
IPC分类号： H03M1/10
CPC分类号： H03M1/1061 , H03M1/0682 , H03M1/44
摘要： A technique for dynamically calibrating a successive approximation charge to digital converter by toggling at least some portion of the converter between two predetermined states, with the design goal of balancing the voltage and/or charge that is output in the two states. The two states are chosen such that they are expected to generate the same output voltage when the converter is in "normal" operation mode, e.g., within a fraction of the Least Significant Bit (LSB) resolution of the converter. If there is an imbalance, switching between the two calibration states invariably generates a square wave signal that toggles between two distinct values. A synchronous demodulator having a bandwidth centered at the toggle frequency can then be used to accurately detect an amount of error, which is then feedback to generate correction signals. If there are undesirable static offsets introduced by the synchronous demodulator or by the signal and/or charge levels output by the two differential halves of the converter, a properly timed latch can be used to further stabilize the error signal.
摘要翻译：通过在两个预定状态之间切换转换器的至少一部分来动态校准逐次逼近电荷到数字转换器的技术，其设计目的是平衡在两种状态下输出的电压和/或电荷。选择这两个状态使得当转换器处于“正常”操作模式时，例如在转换器的最低有效位（LSB）分辨率的一小部分内，它们被期望产生相同的输出电压。如果存在不平衡，则在两个校准状态之间切换总是产生在两个不同值之间切换的方波信号。具有以切换频率为中心的带宽的同步解调器然后可以用于精确地检测误差量，然后反馈以产生校正信号。如果由同步解调器引入不期望的静态偏移或由转换器的两个差分半部输出的信号和/或电荷电平，则可以使用适当定时的锁存器来进一步稳定误差信号。

2. 发明申请

WO2006009966A2 A DEVICE FOR SUBTRACTING OR ADDING A CONSTANT AMOUNT OF CHARGE IN A CHARGE-COUPLED DEVICE AT HIGH OPERATING FREQUENCIES 审中-公开
标题翻译：用于在高运行频率下对充电耦合器件进行充电或增加充电量的设备
公开(公告)号：WO2006009966A2
公开(公告)日：2006-01-26
申请号：PCT/US2005/021688
申请日：2005-06-20
申请人： KENET, INC. , KUSHNER, Lawrence, J. , ANTHONY, Michael, P. , KOHLER, Edward
发明人： KUSHNER, Lawrence, J. , ANTHONY, Michael, P. , KOHLER, Edward
IPC分类号： G11C19/28
CPC分类号： G11C19/282 , G11C19/287 , H01L27/14806
摘要： A circuit for adding or subtracting an amount of charge from a charge sample, such as in a Charge Coupled Device (CCD), by portioning and pipelining the processing stages, to avoid introducing a memory effect. The operation, such as subtraction, is split into multiple stages, with each stage responsible for removing only a portion of the total amount of charge that is desired to be removed. The subtraction pipeline stages operate together to remove the total desired charge amount. In one embodiment each successive subtraction stage removes a corresponding lesser amount of charge. As a result, greater accuracy in the amount of charge removed is achieved as well operation at higher frequencies than previous charge subtraction approaches.
摘要翻译：用于通过对处理级进行分段和流水线从电荷样本（例如电荷耦合器件（CCD））中增加或减少电荷量的电路，以避免引入记忆效应。诸如减法的操作被分成多个阶段，每个阶段负责仅去除期望被移除的总电荷量的一部分。减法流水线级共同操作以去除总计的所需电荷量。在一个实施例中，每个连续的减法阶段去除相应较少量的电荷。结果，实现了去除电荷量的更高精度以及在比先前的电荷减法方法更高的频率下的操作。

3. 发明申请

WO2004004171A1 DYNAMIC DISPERSION COMPENSATION 1N HIGH-SPEED OPTICAL TRANSMISSION SYSTEMS 审中-公开
标题翻译：动态分散补偿1N高速光传输系统
公开(公告)号：WO2004004171A1
公开(公告)日：2004-01-08
申请号：PCT/US2003/020031
申请日：2003-06-25
申请人： AXE, INC. , JONES, David, J. , THOEN, Erik, R. , KESLER, Morris, P. , KUSHNER, Lawrence, J.
发明人： JONES, David, J. , THOEN, Erik, R. , KESLER, Morris, P. , KUSHNER, Lawrence, J.
IPC分类号： H04B10/18
CPC分类号： H04B10/25133 , H03L7/087 , H03L7/093 , H04L7/033
摘要： In a system and method for dynamic compensation, one or more spectral components within the electrical spectrum of the received data signals is used for adjusting the dispersion of the received signals to provide a dispersion compensated signal. In one example, the amplitude of the tone of the transmission bit rate and the bit error rate of the received signals are determined and employed as combined error signal used for the compensation process.
摘要翻译：在用于动态补偿的系统和方法中，接收数据信号的电谱中的一个或多个频谱分量用于调整接收信号的色散以提供色散补偿信号。在一个示例中，确定传输比特率的音调的幅度和接收信号的误码率，并将其用作用于补偿处理的组合误差信号。

4. 发明申请

WO2006104578A3 MANUFACTURING CCDS IN A CONVENTIONAL CMOS PROCESS 审中-公开
公开(公告)号：WO2006104578A3
公开(公告)日：2006-10-05
申请号：PCT/US2006/004799
申请日：2006-02-09
申请人： KENET, INC. , SOLLNER, Gerhard , KUSHNER, Lawrence, J. , ANTHONY, Michael, P. , KOHLER, Edward , GRANT, Wesley
发明人： SOLLNER, Gerhard , KUSHNER, Lawrence, J. , ANTHONY, Michael, P. , KOHLER, Edward , GRANT, Wesley
IPC分类号： H01L21/00 , H01L21/339
摘要： A technique for forming Charge-Coupled Devices (CCDs) in a conventional Complementary Metal Oxide Semiconductor (CMOS) process. A number of single- layer polysilicon gates are formed on an as-grown, native doped silicon substrate, with gaps between them. Masking is used to selectively dope the gates while preventing doping of the silicon in the gaps. Masking may likewise be used to selectively silicide the gates while preventing suicide formation in the gaps. Conventional source-drain processing produces input/output diffusions for the CCD.

5. 发明申请

WO2006009966A3 DEVICE FOR SUBTRACTING/ADDING A CONSTANT AMOUNT OF CHARGE IN A CHARGE-COUPLED DEVICE 审中-公开
标题翻译：用于在充电耦合器件中放置/添加恒定电量的装置
公开(公告)号：WO2006009966A3
公开(公告)日：2006-05-04
申请号：PCT/US2005021688
申请日：2005-06-20
申请人： KENET INC , KUSHNER LAWRENCE J , ANTHONY MICHAEL P , KOHLER EDWARD
发明人： KUSHNER LAWRENCE J , ANTHONY MICHAEL P , KOHLER EDWARD
IPC分类号： G11C19/28 , H01L27/148
CPC分类号： G11C19/282 , G11C19/287 , H01L27/14806
摘要： A circuit for adding or subtracting an amount of charge from a charge sample, such as in a Charge Coupled Device (CCD), by portioning and pipelining the processing stages, to avoid introducing a memory effect. The operation, such as subtraction, is split into multiple stages, with each stage responsible for removing only a portion of the total amount of charge that is desired to be removed. The subtraction pipeline stages operate together to remove the total desired charge amount. In one embodiment each successive subtraction stage removes a corresponding lesser amount of charge. As a result, greater accuracy in the amount of charge removed is achieved as well operation at higher frequencies than previous charge subtraction approaches.
摘要翻译：一种用于通过分配和流水线处理级来从电荷样本（例如电荷耦合器件（CCD））中增加或减少电荷量的电路，以避免引入记忆效应。诸如减法的操作被分成多个阶段，每个阶段负责仅去除期望被移除的总计费用的一部分。减法流水线段一起工作，以消除总的所需电荷量。在一个实施例中，每个连续的减法阶段去除相应较少量的电荷。结果，除了先前的电荷减法方法之外，在更高的频率下也实现更高的去除电荷量的精度。

6. 发明申请

WO2008094626A8 COMMON-MODE INSENSITIVE SAMPLER 审中-公开
公开(公告)号：WO2008094626A8
公开(公告)日：2008-11-06
申请号：PCT/US2008001263
申请日：2008-01-29
申请人： KENET INC , KUSHNER LAWRENCE J , ANTHONY MICHAEL P , FISHER JOHN S
发明人： KUSHNER LAWRENCE J , ANTHONY MICHAEL P , FISHER JOHN S
IPC分类号： H03M1/34
CPC分类号： H03M1/0636 , H03M1/1245
摘要： An approach to rejecting input common-mode voltage variations in a sampler/converter that avoids the use of a differential amplifier in the signal path, and without introducing added distortion or noise. In one embodiment, the input common-mode variations are sensed on a pair of matched resistors that straddle the common mode analog inputs, on a node 'Vcmi'. An alternative, switched-capaci tor- based sensing scheme is also possible. Using this measured Vcmi, adjustments are then made to the rest of the sampler/converter to take out any variations observed at Vcmi.

7. 发明申请

WO2008094626A2 COMMON-MODE INSENSITIVE SAMPLER 审中-公开
标题翻译：通用型隐性采样器
公开(公告)号：WO2008094626A2
公开(公告)日：2008-08-07
申请号：PCT/US2008/001263
申请日：2008-01-29
申请人： KENET, INC. , KUSHNER, Lawrence, J. , ANTHONY, Michael, P. , FISHER, John, S.
发明人： KUSHNER, Lawrence, J. , ANTHONY, Michael, P. , FISHER, John, S.
IPC分类号： H03M1/34
CPC分类号： H03M1/0636 , H03M1/1245
摘要： An approach to rejecting input common-mode voltage variations in a sampler/converter that avoids the use of a differential amplifier in the signal path, and without introducing added distortion or noise. In one embodiment, the input common-mode variations are sensed on a pair of matched resistors that straddle the common mode analog inputs, on a node 'Vcmi'. An alternative, switched-capaci tor- based sensing scheme is also possible. Using this measured Vcmi, adjustments are then made to the rest of the sampler/converter to take out any variations observed at Vcmi.
摘要翻译：拒绝采样器/转换器中的输入共模电压变化的方法，其避免在信号路径中使用差分放大器，并且不引入附加的失真或噪声。在一个实施例中，在节点“Vcmi”上跨越共模模拟输入的一对匹配电阻器上感测输入共模变化。一种替代的基于开关电容的感测方案也是可能的。使用该测量的Vcmi，然后对采样器/转换器的其余部分进行调整，以取出在Vcmi处观察到的任何变化。

8. 发明申请

WO2006014558A3 VOLTAGE RANDOM ACCESS MEMORY (VRAM) 审中-公开
公开(公告)号：WO2006014558A3
公开(公告)日：2006-02-09
申请号：PCT/US2005/024137
申请日：2005-07-06
申请人： KENET, INC. , ANTHONY, Michael, P. , KUSHNER, Lawrence, J.
发明人： ANTHONY, Michael, P. , KUSHNER, Lawrence, J.
IPC分类号： H03M1/78 , H03M7/00
摘要： An integrated circuit memory cell and voltage ladder design that adapts techniques typically applied to Static Random Access Memory (SRAM) circuits to implement a compact array of analog Voltage Random Access Memory (VRAM) locations. The memory cells in the VRAM each store a digital value that controls a corresponding switch. The switch couple a particular voltage from a set of voltages generated by the ladder, to be output when that location is enabled. Multiple analog output voltages are provided by simply providing additional rows of cells.

9. 发明申请

WO2006009896A2 ANALOG TO DIGITAL CONVERTER CALIBRATION VIA SYNCHRONOUS DEMODULATION 审中-公开
标题翻译：通过同步解调模拟数字转换器校准
公开(公告)号：WO2006009896A2
公开(公告)日：2006-01-26
申请号：PCT/US2005/021568
申请日：2005-06-17
申请人： KENET, INC. , KUSHNER, Lawrence, J. , ANTHONY, Michael, P.
发明人： KUSHNER, Lawrence, J. , ANTHONY, Michael, P.
IPC分类号： H03M1/10
CPC分类号： H03M1/1061 , H03M1/0682 , H03M1/44
摘要： A technique for dynamically calibrating a successive approximation charge to digital converter by toggling at least some portion of the converter between two predetermined states, with the design goal of balancing the voltage and/or charge that is output in the two states. The two states are chosen such that they are expected to generate the same output voltage when the converter is in "normal" operation mode, e.g., within a fraction of the Least Significant Bit (LSB) resolution of the converter. If there is an imbalance, switching between the two calibration states invariably generates a square wave signal that toggles between two distinct values. A synchronous demodulator having a bandwidth centered at the toggle frequency can then be used to accurately detect an amount of error, which is then feedback to generate correction signals. If there are undesirable static offsets introduced by the synchronous demodulator or by the signal and/or charge levels output by the two differential halves of the converter, a properly timed latch can be used to further stabilize the error signal.
摘要翻译：通过在两个预定状态之间切换转换器的至少一部分来动态校准逐次逼近电荷到数字转换器的技术，其设计目标是平衡在两种状态下输出的电压和/或电荷。选择两个状态使得当转换器处于“正常”操作模式时，例如在转换器的最低有效位（LSB）分辨率的一小部分内，它们被期望产生相同的输出电压。如果存在不平衡，则在两个校准状态之间切换总是产生在两个不同值之间切换的方波信号。然后可以使用具有以触发频率为中心的带宽的同步解调器来精确地检测误差量，然后将其反馈以产生校正信号。如果由同步解调器引入不期望的静态偏移或由转换器的两个差分半部输出的信号和/或电荷电平，则可以使用适当定时的锁存器来进一步稳定误差信号。

10. 发明申请

WO2003019788A1 SYSTEM AND METHOD FOR WIDE DYNAMIC RANGE CLOCK RECOVERY. 审中-公开
标题翻译：用于宽动态范围恢复的系统和方法。
公开(公告)号：WO2003019788A1
公开(公告)日：2003-03-06
申请号：PCT/US2002/027017
申请日：2002-08-23
申请人： AXE, INC. , KUSHNER, Lawrence, J. , RAO, Hemonth
发明人： KUSHNER, Lawrence, J. , RAO, Hemonth
IPC分类号： H03M7/00
CPC分类号： H03L7/093 , H03L7/087 , H04L7/033
摘要： A system and method for clock recovery from an input data stream recovers the clock signal in a manner that preserves the signal strength of the input signal. The measure of signal strength, referred to herein as the "signal strength indicator" is in turn used to normalize the output of a phase detector in a phase-locked loop (PLL), and the normalized signal is used as an input to the PLL oscillator to recover the clock signal from the input data signal. In this manner, the phase-locked loop is used to perform narrow band filtering, while baseband amplifiers are used to compensate for reference signal power variations. In one aspect, the present invention is directed to a clock recovery system for recovering a clock signal from an input data signal. The system (figure 2) comprises a primary phase detector (122B) for receiving an input data signal (130), and for combining the input data signal (130) with a feedback signal (136) to generate the signal strength indicator (153). A gain equalizer (254) normalizes the phase difference signal by the signal strength indicator, and an oscillator provides the clock signal based on the normalized phase difference signal and further provides the clock signal as the feedback signal which is returned to the auxiliary and primary detectors.
摘要翻译：用于从输入数据流进行时钟恢复的系统和方法以保持输入信号的信号强度的方式恢复时钟信号。此处称为“信号强度指示符”的信号强度测量又用于在锁相环（PLL）中归一化相位检测器的输出，归一化信号用作PLL的输入振荡器从输入数据信号恢复时钟信号。以这种方式，锁相环用于执行窄带滤波，而基带放大器用于补偿参考信号功率变化。一方面，本发明涉及一种用于从输入数据信号中恢复时钟信号的时钟恢复系统。系统（图2）包括用于接收输入数据信号（130）的主相位检测器（122B），并且用于将输入数据信号（130）与反馈信号（136）组合以产生信号强度指示器（153）。增益均衡器（254）通过信号强度指示器对相位差信号进行归一化，并且振荡器基于归一化相位差信号提供时钟信号，并且还提供时钟信号作为反馈信号，该反馈信号返回到辅助和主检测器。

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