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1. 发明申请

WO2023272373A1 OVERCURRENT DETECTION USING A PROGRAMMABLE LOGIC DEVICE 审中-公开
公开(公告)号：WO2023272373A1
公开(公告)日：2023-01-05
申请号：PCT/CA2022/000028
申请日：2022-06-27
申请人： MAGNA INTERNATIONAL INC.
发明人： NEUDORFHOFER, Michael , OBERLEITNER, Oliver
IPC分类号： H03M1/34 , H03K19/20 , H03K19/177
摘要： An analog-to-digital converter (ADC) circuit for measuring an analog input signal comprises a comparator including a non-inverting input having a reference value and an inverting input coupled to the analog input signal. The comparator is configured to assert a comparator output based on a comparison between values on the inverting and non-inverting inputs. A sampling element receives a clock signal is configured to hold a first output terminal at a digital logic level of the comparator output in response to receiving each pulse of the clock signal, to provide a high-frequency pulse-width modulated (PWM) signal representing a value of the analog input signal. A programmable logic device (PLD) includes a digital comparator receiving a digital value based on the high-frequency PWM signal, and generating an error signal based on comparing the digital value to one or more error levels.

2. 发明申请

WO2021258090A1 CIRCUITRY FOR AUTONOMOUSLY MEASURING ANALOG SIGNALS AND RELATED SYSTEMS, METHODS, AND DEVICES 审中-公开
公开(公告)号：WO2021258090A1
公开(公告)日：2021-12-23
申请号：PCT/US2021/070308
申请日：2021-03-25
申请人： MICROCHIP TECHNOLOGY INCORPORATED
发明人： SUNDERDIEK, Gregor Hubert
IPC分类号： H03M1/00 , G08B17/107 , H03M1/12 , G08B1/08 , G08B17/12 , H03M1/002 , H03M1/34
摘要： Analog signal measurement and related circuitry, systems, and methods are disclosed. Circuitry includes timing circuitry configured to assert a first enable signal at a first time and a second enable signal at a second time. The circuitry also includes an operational amplifier circuit configured to enable responsive to the assertion of the first enable signal. The operational amplifier circuit is configured to receive an analog input signal and, if enabled, generate an amplified analog input signal responsive to the analog input signal. The circuitry further includes signal analyzing circuitry configured to enable responsive to the assertion of the first enable signal, compare the amplified analog input signal to one or more threshold values responsive to the assertion of the second enable signal, and generate an alert signal responsive to a determination that the amplified analog input signal falls outside of the one or more threshold values.

3. 发明申请

WO2021222197A1 RANGING SYSTEMS AND METHODS FOR DECREASING TRANSITIVE EFFECTS IN MULTI-RANGE MATERIALS MEASUREMENTS 审中-公开
公开(公告)号：WO2021222197A1
公开(公告)日：2021-11-04
申请号：PCT/US2021/029328
申请日：2021-04-27
申请人： LAKE SHORE CRYOTRONICS, INC.
发明人： FORTNEY, Houston
IPC分类号： H03M1/12 , H03M1/06 , H03M1/34
摘要： A measurement system includes a gain chain configured to amplify an analog input signal; a range selector configured to select a gain between the analog input signal and a plurality of analog-to-digital converter (ADC) outputs from a plurality of ADCs, wherein each ADC output has a path, and a gain of each output path is made up of a plurality of gain stages in the gain chain; and a mixer configured to combine the plurality of ADC outputs into a single mixed output.

4. 发明申请

WO2021067932A1 NON-LINEARITY CORRECTION 审中-公开
公开(公告)号：WO2021067932A1
公开(公告)日：2021-04-08
申请号：PCT/US2020/054258
申请日：2020-10-05
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： GUPTA, Pankaj , TANGUDU, Jawaharlal , PAULOSE, Ajai
IPC分类号： H03M1/08 , H03M1/34
摘要： A method (600) for non-linearity correction includes receiving (608, 622) a first output signal from a data signal path containing a first analog-to-digital converter and receiving a second output signal from a second analog-to-digital converter. The method also includes generating (624, 626, 628) first non-linearity coefficients using the first output signal and generating (610, 612, 614, 616) second non-linearity coefficients using the first and second output signals. The method further includes applying (634), by a non-linearity corrector in the data signal path, the first and second non-linearity coefficients to compensate for non-linearity components in a digitized signal output from the first analog-to-digital converter to generate a corrected digitized signal.

5. 发明申请

WO2020198097A1 ANALOG TO DIGITAL CONVERSION CIRCUIT WITH VERY NARROW BANDPASS DIGITAL FILTERING 审中-公开
公开(公告)号：WO2020198097A1
公开(公告)日：2020-10-01
申请号：PCT/US2020/024123
申请日：2020-03-23
申请人： SIGMASENSE, LLC.
发明人： MCGIBNEY, Grant Howard , GRAY, Patrick Troy , MORRISON, Gerald Dale , VAN OSTRAND, Daniel Keith
IPC分类号： H03M1/12 , H03M1/18 , H03M1/34
摘要： An analog to digital conversion circuit includes an analog to digital converter (ADC) circuit operable to convert an analog signal having an oscillation frequency into a first digital signal having a first data rate frequency, where the analog signal includes a set of pure tone components. The ADC circuit further includes a digital decimation filtering circuit operable to convert the first digital signal into a second digital signal having a second data rate frequency. The ADC circuit further includes a digital bandpass filter circuit operable to convert the second digital signal into an outbound digital signal having a third data rate frequency. The digital bandpass filter circuit is set to produce a bandpass region having a bandwidth tuned for filtering a desired pure tone. The ADC circuit further includes a coefficient processor operable to calculate the plurality of coefficients and a processing module operable to select the desired pure tone.

6. 发明申请

WO0041310A3 SYSTEM FOR QUANTIZING AN ANALOG SIGNAL UTILIZING A RESONANT TUNNELING DIODE BRIDGE 审中-公开
标题翻译：用于定量使用谐振隧道二极管的模拟信号的系统
公开(公告)号：WO0041310A3
公开(公告)日：2000-09-28
申请号：PCT/US0000173
申请日：2000-01-05
申请人： RAYTHEON CO
发明人： BROEKAERT TOM P E
IPC分类号： H03M1/12 , H03K3/315 , H03M1/06 , H03M1/34
CPC分类号： B82Y10/00 , H03M1/0682 , H03M1/34
摘要： A system for quantizing an analog signal comprises an input terminal for receiving an input signal, an inverted input terminal for receiving an inverted input signal, a clock terminal for receiving a clock signal, and an inverted clock terminal for receiving an inverted clock signal. A first negative-resistance device has a first terminal coupled to the clock terminal and a second terminal coupled to the clock terminal coupled to the input terminal. A second negative-resistance device has a third terminal coupled to the clock terminal and a fourth terminal coupled to the inverted input terminal. A third negative-resistance device has a fifth terminal coupled to the input terminal and a sixth terminal coupled inverted clock terminal. A fourth negative-resistance device has a seventh terminal coupled to the inverted input terminal and an eighth terminal coupled to the inverted clock terminal. An output terminal for producing an output signal is connected to the input terminal. An inverted output terminal for producing an inverted output signal is connected to the inverted input terminal.
摘要翻译：用于量化模拟信号的系统包括用于接收输入信号的输入端子，用于接收反相输入信号的反相输入端子，用于接收时钟信号的时钟端子和用于接收反相时钟信号的反相时钟端子。第一负电阻器件具有耦合到时钟端子的第一端子和耦合到耦合到输入端子的时钟端子的第二端子。第二负电阻器件具有耦合到时钟端子的第三端子和耦合到反相输入端子的第四端子。第三负电阻器件具有耦合到输入端子的第五端子和第六端子耦合反相时钟端子。第四负电阻器件具有耦合到反相输入端的第七端子和耦合到反相时钟端子的第八端子。用于产生输出信号的输出端连接到输入端。用于产生反相输出信号的反相输出端连接到反相输入端。

7. 发明申请

WO00041310A2 SYSTEM FOR QUANTIZING AN ANALOG SIGNAL UTILIZING A RESONANT TUNNELING DIODE BRIDGE 审中-公开
标题翻译：量化包含谐振隧道二极管桥的模拟信号的系统
公开(公告)号：WO00041310A2
公开(公告)日：2000-07-13
申请号：PCT/US2000/000173
申请日：2000-01-05
IPC分类号： H03M1/12 , H03K3/315 , H03M1/06 , H03M1/34
CPC分类号： B82Y10/00 , H03M1/0682 , H03M1/34
摘要： A system for quantizing an analog signal comprises an input terminal for receiving an input signal, an inverted input terminal for receiving an inverted input signal, a clock terminal for receiving a clock signal, and an inverted clock terminal for receiving an inverted clock signal. A first negative-resistance device has a first terminal coupled to the clock terminal and a second terminal coupled to the clock terminal coupled to the input terminal. A second negative-resistance device has a third terminal coupled to the clock terminal and a fourth terminal coupled to the inverted input terminal. A third negative-resistance device has a fifth terminal coupled to the input terminal and a sixth terminal coupled inverted clock terminal. A fourth negative-resistance device has a seventh terminal coupled to the inverted input terminal and an eighth terminal coupled to the inverted clock terminal. An output terminal for producing an output signal is connected to the input terminal. An inverted output terminal for producing an inverted output signal is connected to the inverted input terminal.
摘要翻译：用于量化模拟信号的系统包括用于接收输入信号的输入端子，用于接收反相输入信号的反相输入端子，用于接收输入信号的时钟端子。时钟和用于接收反相时钟信号的反相时钟端。第一负阻器件具有耦合到时钟端子的第一端子和耦合到耦合到输入端子的时钟端子的第二端子。第二负阻器件包括耦合到时钟端子的第三端子和耦合到反相输入端子的第四端子。第三负阻器件具有耦合到输入端子的第五端子和耦合到反转时钟端子的第六端子。第四负阻器件具有耦合到反相输入端子的第七端子和耦合到反相时钟端子的第八端子。产生输出信号的输出端连接到输入端。产生反相输出信号的反相输出端连接到反相输入端。

8. 发明申请

WO9709788A3 A/D CONVERSION WITH FOLDING AND INTERPOLATION 审中-公开
标题翻译： A / D转换与折叠和插值
公开(公告)号：WO9709788A3
公开(公告)日：1997-04-03
申请号：PCT/IB9600869
申请日：1996-08-29
申请人： PHILIPS ELECTRONICS NV , PHILIPS NORDEN AB
发明人： VORENKAMP PIETER , VENES ARNOLDUS GERARDUS WILHEL , VAN DE PLASSCHE RUDY JOHAN
IPC分类号： H03M1/34 , H03M1/20 , H03M1/36
CPC分类号： H03M1/204 , H03M1/141
摘要： An A/D converter has an input part IS which provides transitions T1..Tx associated with different levels of an analog input signal Vin. An intermediate part IMS carries out folding and interpolation operations F1, I1 and F2, I2..IN on the transitions T1..Tx to obtain a set of bit-determining signals XO.. XQ. At least one of the operations, folding F1, F2,.. or interpolation I1, IN, is carried out more than once in alternation with the other operation, interpolation I1, IN or folding F1, F2,.. respectively. An output part OS provides a digital output signal Do on the basis of the bit-determining signals XO..XQ. Such an A/D converter can be implemented in a cost-efficient manner and may be combined with digital signal-processing circuitry.

9. 发明申请

WO2022199427A1 一种应用于模数转换电路的数据处理算法审中-公开
公开(公告)号：WO2022199427A1
公开(公告)日：2022-09-29
申请号：PCT/CN2022/080921
申请日：2022-03-15
申请人：张家炎
发明人：张家炎 ZHANG, Jiayan
IPC分类号： H03M1/34
摘要：一种应用于模数转换电路的数据处理算法，设定Q组数组、每组数组包括N个模数转换值以及对应的计算底数X的幂k；输出多组数组G1、G2、G3、…GQ中各组数组的N个模数转换值；计算G1至GQ各数组的中位数测度值、极小值测度值、极大值测度值、众数测度值、调和平均数测度值、几何平均数测度值和多维测度值。通过对多组模数转换值进行中位数、极小值、极大值、众数、调和平均数、算数平均数进行测度，再将上述测度进行多维测度运算，能够显著提高模数转换电路的ADC芯片的模数转换精度。

10. 发明申请

WO2022057513A1 具有预充电和提前复位输出级的比较器电路审中-公开
公开(公告)号：WO2022057513A1
公开(公告)日：2022-03-24
申请号：PCT/CN2021/111549
申请日：2021-08-09
申请人：杭州集益威半导体有限公司
发明人：蔡敏卿 , 姚豫封 , 葛云龙 , 王浩南 , 李承哲 , 钟英权
IPC分类号： H03M1/00 , H03M1/08 , H03M1/34
摘要：本申请公开了一种具有预充电和提前复位输出级的比较器电路，包括：第一预充电晶体管和第二预充电晶体管，第一预充电晶体管的栅极连接预充电信号，第二预充电晶体管的栅极连接主时钟信号，预充电信号早于主时钟信号使能。在预充电阶段，电流很小，比较器会缓慢放大输入小信号从而减小噪声。经过一定时间延迟后，加大电流，使比较器在预充电基础上快速完成预放大阶段进入再生阶段。由于有大电流，可以以较快的速度完成再生阶段。由于预充电时间已经有了一定的信号放大，之后阶段的噪声等效到输入就减小了。本发明可以同时满足高速，低功耗，低噪声。本发明前馈提前复位输出级，在不增加复位时间和不太多增加内部电容时使滞回降到了指标以内。

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