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1. 发明申请

WO2012115743A1 LOW-TEMPERATURE SELECTIVE EPITAXIAL GROWTH OF SILICON FOR DEVICE INTEGRATION 审中-公开
标题翻译：低温选择性外延生长用于器件集成的硅
公开(公告)号：WO2012115743A1
公开(公告)日：2012-08-30
申请号：PCT/US2012/022716
申请日：2012-01-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , HEKMATSHOAR-TABARI, Bahman , KHAKIFIROOZ, Ali , REZNICEK, Alexander , SADANA, Devendra, K. , SHAHIDI, Ghavam, G. , SHAHRJERDI, Davood
发明人： HEKMATSHOAR-TABARI, Bahman , KHAKIFIROOZ, Ali , REZNICEK, Alexander , SADANA, Devendra, K. , SHAHIDI, Ghavam, G. , SHAHRJERDI, Davood
IPC分类号： H01L21/00
CPC分类号： C30B25/04 , C30B25/105 , C30B25/14 , C30B25/183 , C30B25/186 , C30B29/06 , C30B33/12 , H01L21/02381 , H01L21/02395 , H01L21/02532 , H01L21/02576 , H01L21/02584 , H01L21/0262 , H01L21/02639 , H01L21/3065
摘要： An epitaxy method includes providing (402) an exposed crystalline region of a substrate material. Silicon is epitaxially deposited (404) on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted (408) with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000.
摘要翻译：外延法包括提供（402）暴露的基底材料的结晶区域。硅在低温工艺中在衬底材料上外延沉积（404），其中沉积温度低于500摄氏度。源气体用稀释气体稀释（408），稀释气体与原料气体的气体比小于1000。

2. 发明申请

WO2010016956A1 CRYSTALLINE SILICON SUBSTRATES WITH IMPROVED MINORITY CARRIER LIFETIME 审中-公开
标题翻译：具有改进的少数载体寿命的晶体硅衬底
公开(公告)号：WO2010016956A1
公开(公告)日：2010-02-11
申请号：PCT/US2009/041506
申请日：2009-04-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , DE SOUZA, Joel, P. , HOVEL, Harold, John , INNS, Daniel, A. , SADANA, Devendra, K. , SHAHIDI, Ghavam, G.
发明人： DE SOUZA, Joel, P. , HOVEL, Harold, John , INNS, Daniel, A. , SADANA, Devendra, K. , SHAHIDI, Ghavam, G.
IPC分类号： H01L21/322
CPC分类号： H01L21/3225 , H01L21/02032
摘要： A method for improving the minority lifetime of silicon containing wafer having metallic contaminants therein is described incorporating annealing at 1200°C or greater and providing a gaseous ambient of oxygen, an inert gas and a chlorine containing gas such as HCl.
摘要翻译：描述了一种用于改善其中具有金属污染物的含硅晶片的少数寿命的方法，其包括在1200℃或更高温度下退火并提供氧气，惰性气体和含氯气体如HCl的气态环境。

3. 发明申请

WO2006003061A1 STRAINED SILICON-ON-INSULATOR BY ANODIZATION OF A BURIED p+ SILICON GERMANIUM LAYER 审中-公开
标题翻译：通过阳极氧化P +硅锗层的分级制备的绝缘硅绝缘体
公开(公告)号：WO2006003061A1
公开(公告)日：2006-01-12
申请号：PCT/EP2005/052424
申请日：2005-05-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , Compagnie IBM France , ADAM, Thomas, N , BEDELL, Stephen, W. , DE SOUZA, Joel, P. , FOGEL, Keith, E. , REZNICEK, Alexander , SADANA, Devendra, K. , SHAHIDI, Ghavam
发明人： ADAM, Thomas, N , BEDELL, Stephen, W. , DE SOUZA, Joel, P. , FOGEL, Keith, E. , REZNICEK, Alexander , SADANA, Devendra, K. , SHAHIDI, Ghavam
IPC分类号： H01L21/762
CPC分类号： H01L21/76259 , Y10S438/967
摘要： A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.
摘要翻译：提供了制造应变半导体绝缘体（SSOI）衬底的成本有效和可制造的方法，其避免晶片接合。该方法包括在衬底上生长各种外延半导体层，其中半导体层中的至少一个是在应变半导体层下面的掺杂和弛豫半导体层; 通过电解阳极氧化处理将掺杂和松弛的半导体层转化成多孔半导体，并氧化以将多孔半导体层转化为掩埋氧化物层。该方法提供了在衬底上包括松弛半导体层的SSOI衬底; 在松弛的半导体层上形成高质量的掩埋氧化物层; 以及在高质量掩埋氧化物层上的应变半导体层。根据本发明，松弛半导体层和应变半导体层具有相同的晶体取向。

4. 发明申请

WO2012002994A1 SELECTIVE EPITAXY OF SI-CONTAINING MATERIALS AND SUBSTITUTIONALLY DOPED CRYSTALLINE SI-CONTAINING MATERIALS 审中-公开
标题翻译：含SI材料的选择性外延和替代掺杂的含晶体材料
公开(公告)号：WO2012002994A1
公开(公告)日：2012-01-05
申请号：PCT/US2011/001116
申请日：2011-06-23
申请人： MATHESON TRI-GAS, INC. , INTERNATIONAL BUSINESS MACHINES CORPORATION , FRANCIS, Terry, Arthur , HASAKA, Satoshi , BRABANT, Paul, David , TORRES, Robert, Jr. , HE, Hong , REZNICEK, Alexander , ADAM, Thomas, N. , SADANA, Devendra, K.
发明人： FRANCIS, Terry, Arthur , HASAKA, Satoshi , BRABANT, Paul, David , TORRES, Robert, Jr. , HE, Hong , REZNICEK, Alexander , ADAM, Thomas, N. , SADANA, Devendra, K.
IPC分类号： C30B25/02
CPC分类号： H01L21/02532 , C23C16/30 , C23C16/325 , C30B25/02 , C30B29/06 , H01L21/0237 , H01L21/02529 , H01L21/02573 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02636
摘要： The present invention discloses that under modified chemical vapor deposition (mCVD) conditions an epitaxial silicon film may be formed by exposing a substrate contained within a chamber to a relatively high carrier gas flow rate in combination with a relatively low silicon precursor flow rate at a temperature of less than about 550°C and a pressure in the range of about 10 mTorr - 200 Torr. Furthermore, the crystalline Si may be in situ doped to contain relatively high levels of substitutional carbon by carrying out the deposition at a relatively high flow rate using tetrasilane as a silicon source and a carbon-containing gas such as dodecalmethylcyclohexasilane or tetramethyldisilane under modified CVD conditions.
摘要翻译：本发明公开了在改进的化学气相沉积（mCVD）条件下，外延硅膜可以通过将包含在腔室内的衬底暴露于相对高的载气流量与在较低的硅前体流速小于约550℃，压力范围为约10mTorr-200Torr。此外，通过在改进的CVD条件下使用四硅烷作为硅源和含碳气体如十二烷基甲基环己硅烷或四甲基二硅烷以相对高的流速进行沉积，可以将晶体Si原位掺杂以含有相对高水平的取代碳。

5. 发明申请

WO2007130333A3 ION IMPLANTATION COMBINED WITH IN SITU OR EX SITU HEAT TREATMENT FOR IMPROVED FIELD EFFECT TRANSISTORS 审中-公开
公开(公告)号：WO2007130333A3
公开(公告)日：2007-11-15
申请号：PCT/US2007/010411
申请日：2007-04-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , BEDELL, Stephen, W. , DESOUZA, Joel, P. , REN, Zhibin , REZNICEK, Alexander , SADANA, Devendra, K. , SAENGER, Katherine, L. , SHAHIDI, Ghavam
发明人： BEDELL, Stephen, W. , DESOUZA, Joel, P. , REN, Zhibin , REZNICEK, Alexander , SADANA, Devendra, K. , SAENGER, Katherine, L. , SHAHIDI, Ghavam
IPC分类号： H01L21/8234 , H01L21/336
摘要： This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (SfD) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a "divided-dose-anneal-in-between" (DDAB) scheme that avoids the need for tooling capable of performing hot implants.

6. 发明申请

WO2012173816A1 UNIFORMLY DISTRIBUTED SELF-ASSEMBLED CONE-SHAPED PILLARS FOR HIGH EFFICIENCY SOLAR CELLS 审中-公开
标题翻译：用于高效太阳能电池的均匀分布自组装式锥形支架
公开(公告)号：WO2012173816A1
公开(公告)日：2012-12-20
申请号：PCT/US2012/040878
申请日：2012-06-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , DIMITRAKOPOULOS, Christos , HONG, Augustin, J. , KIM, Jeehwan , SADANA, Devendra, K. , SHIU, Kuen-ting
发明人： DIMITRAKOPOULOS, Christos , HONG, Augustin, J. , KIM, Jeehwan , SADANA, Devendra, K. , SHIU, Kuen-ting
IPC分类号： H01L31/00
CPC分类号： G06F3/061 , G06F3/064 , G06F3/0647 , G06F3/0653 , G06F3/0689 , G06F11/0727 , G06F11/1076 , G06F12/02 , H01L31/02366 , H04L67/1002 , H04W8/04 , H04W8/065 , Y02E10/50
摘要： A method for fabricating a photovoltaic device includes applying (206) a diblock copolymer layer on a substrate and removing a first polymer material from the diblock copolymer layer to form a plurality of distributed pores. A pattern forming layer is deposited (212) on a remaining surface of the diblock copolymer layer and in the pores in contact with the substrate. The diblock copolymer layer is lifted off (214) and portions of the pattern forming layer are left in contact with the substrate. The substrate is etched (216) using the pattern forming layer to protect portions of the substrate to form pillars in the substrate such that the pillars provide a radiation absorbing structure in the photovoltaic device.
摘要翻译：制造光伏器件的方法包括将二嵌段共聚物层施加（206）到基底上，并从二嵌段共聚物层除去第一聚合物材料以形成多个分布孔。在二嵌段共聚物层的剩余表面和与基材接触的孔中沉积图案形成层（212）。将二嵌段共聚物层剥离（214），并且图案形成层的部分与基材保持接触。使用图案形成层来蚀刻（216）衬底，以保护衬底的部分以在衬底中形成柱状，使得柱在光伏器件中提供辐射吸收结构。

7. 发明申请

WO2009108479A1 POROUS SILICON QUANTUM DOT PHOTODETECTOR 审中-公开
标题翻译：多孔硅量子点光源
公开(公告)号：WO2009108479A1
公开(公告)日：2009-09-03
申请号：PCT/US2009/033517
申请日：2009-02-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , HOVEL, Harold, J. , DE SOUZA, Joel, P. , SADANA, Devendra, K.
发明人： HOVEL, Harold, J. , DE SOUZA, Joel, P. , SADANA, Devendra, K.
IPC分类号： H01L31/00
CPC分类号： H01L31/035281 , B82Y20/00 , H01L31/022425 , H01L31/0296 , H01L31/0304 , H01L31/18 , Y02E10/544 , Y02P70/521
摘要： Embodiments of the present invention provide a solar energy converter, which includes a silicon layer having at least two regions of a first and a second conductivity type that form a P-N junction, at least a portion of the silicon layer being porous, and pores in the portion of porous silicon containing a semiconductor material, the semiconductor material being different from silicon; and a first and a second electrode being placed at a bottom and a top surface of the silicon layer respectively. Methods of manufacturing the same are also provided.
摘要翻译：本发明的实施例提供了一种太阳能转换器，其包括具有形成PN结的至少两个第一和第二导电类型的区域的硅层，至少一部分硅层是多孔的，并且孔中的孔含有半导体材料的多孔硅的部分，所述半导体材料与硅不同; 以及分别设置在硅层的底部和顶面的第一和第二电极。还提供了制造方法。

8. 发明申请

WO2006017640A1 METHOD OF FORMING STRAINED SILICON MATERIALS WITH IMPROVED THERMAL CONDUCTIVITY 审中-公开
标题翻译：形成具有改善的导热性的应变硅材料的方法
公开(公告)号：WO2006017640A1
公开(公告)日：2006-02-16
申请号：PCT/US2005/027691
申请日：2005-08-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , BEDELL, Stephen, W. , CHEN, Huajie , FOGEL, Keith , MITCHELL, Ryan, M. , SADANA, Devendra, K.
发明人： BEDELL, Stephen, W. , CHEN, Huajie , FOGEL, Keith , MITCHELL, Ryan, M. , SADANA, Devendra, K.
IPC分类号： H01L21/36
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02507 , H01L21/02532
摘要： A method is disclosed for forming a strained Si layer on SiGe, where the SiGe layer has improved thermal conductivity. A first layer (41) of Si or Ge is deposited on a substrate (10) in a first depositing step; a second layer (42) of the other element is deposited on the first layer in a second depositing step; and the first and second depositing steps are repeated so as to form a combined SiGe layer (50) having a plurality of Si layers and a plurality of Ge layers (41-44). The respective thicknesses of the Si layers and Ge layers are in accordance with a desired composition ratio of the combined SiGe layer. The combined SiGe layer (50) is characterized as a digital alloy of Si and Ge having a thermal conductivity greater than that of a random alloy of Si and Ge. This method may further include the step of depositing a Si layer (61) on the combined SiGe layer (50); the combined SiGe layer is characterized as a relaxed SiGe layer, and the Si layer (61) is a strained Si layer. For still greater thermal conductivity in the SiGe layer, the first layer and second layer may be deposited so that each layer consists essentially of a single isotope.
摘要翻译：公开了一种在SiGe上形成应变Si层的方法，其中SiGe层具有改善的导热性。在第一沉积步骤中，在衬底（10）上沉积Si或Ge的第一层（41）另一元件的第二层（42）在第二沉积步骤中沉积在第一层上; 并且重复第一和第二沉积步骤以形成具有多个Si层和多个Ge层（41-44）的组合SiGe层（50）。 Si层和Ge层的各自的厚度根据组合的SiGe层的期望组成比。组合的SiGe层（50）的特征在于具有大于Si和Ge的随机合金的热导率的Si和Ge的数字合金。该方法还可以包括在组合SiGe层（50）上沉积Si层（61）的步骤。组合的SiGe层被表征为弛豫的SiGe层，并且Si层（61）是应变Si层。对于SiGe层中的更高的热导率，可以沉积第一层和第二层，使得每层基本上由单一同位素组成。

9. 发明申请

WO2013033139A1 FORMATION OF METAL NANOSPHERES AND MICROSPHERES 审中-公开
标题翻译：形成金属纳米微粒和微球
公开(公告)号：WO2013033139A1
公开(公告)日：2013-03-07
申请号：PCT/US2012/052759
申请日：2012-08-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , HONG, Augustin, J. , JUNG, Woo-shik , KIM, Jeehwan , NAH, Jae-woong , SADANA, Devendra, K.
发明人： HONG, Augustin, J. , JUNG, Woo-shik , KIM, Jeehwan , NAH, Jae-woong , SADANA, Devendra, K.
IPC分类号： H01L51/40
CPC分类号： H01L31/035227 , C03C15/00 , C03C17/06 , C03C2218/34 , H01L31/022433 , H01L31/02363 , H01L31/035281 , H01L31/0376 , H01L31/0392 , H01L31/03921 , H01L31/03923 , H01L31/03925 , H01L31/056 , H01L31/075 , Y02E10/52 , Y02E10/541 , Y02E10/548 , Y10S438/945 , Y10S977/773 , Y10S977/779 , Y10T428/12014 , Y10T428/12069 , Y10T428/12076 , Y10T428/24479 , Y10T428/24488 , Y10T428/2982
摘要： Hemispheres (18) and spheres (28) are formed and employed for a plurality of applications. Hemispheres (18) are employed to form a substrate having an upper surface and a lower surface (12). The upper surface includes peaks of pillars (10) which have a base attached to the lower surface. The peaks have a density defined at the upper surface by an array of hemispherical metal structures (18) that act as a mask during an etch to remove substrate material down to the lower surface during formation of the pillars. The pillars are dense and uniform and include a microscale average diameter. The spheres are formed as independent metal spheres or nanoparticles for other applications.
摘要翻译：形成半球（18）和球（28）并用于多个应用。半球（18）用于形成具有上表面和下表面（12）的基底。上表面包括具有附接到下表面的基部的柱（10）的峰。这些峰具有在上表面处限定的半球形金属结构（18）阵列的密度，该半球形金属结构（18）在蚀刻期间用作掩模，以在形成支柱期间将基底材料移除到下表面。支柱是致密和均匀的，并且包括微米级的平均直径。球形成为独立的金属球体或纳米颗粒用于其他应用。

10. 发明申请

WO2012118577A1 TANDEM SOLAR CELL WITH IMPROVED ABSORPTION MATERIAL 审中-公开
标题翻译：具有改进吸收材料的TANDEM太阳能电池
公开(公告)号：WO2012118577A1
公开(公告)日：2012-09-07
申请号：PCT/US2012/022708
申请日：2012-01-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , GUNAWAN, Oki , KIM, Jeehwan , MITZI, David, B. , SADANA, Devendra, K. , TODOROV, Teodor, K.
发明人： GUNAWAN, Oki , KIM, Jeehwan , MITZI, David, B. , SADANA, Devendra, K. , TODOROV, Teodor, K.
IPC分类号： H01L31/0256
CPC分类号： H01L31/0326 , C23C14/34 , C25D7/12 , H01L31/076 , H01L31/078 , H01L31/18 , H01L31/20 , Y02E10/548
摘要： A photosensitive device and method includes a top cell (102) having an N-type layer, a P-type layer and a top intrinsic layer therebetween. A bottom cell (104) includes an N-type layer, a P-type layer and a bottom intrinsic layer therebetween. The bottom intrinsic layer includes a Cu-Zn-Sn containing chalcogenide (116).
摘要翻译：感光装置和方法包括具有N型层的顶层单元（102），P型层和其间的顶层本征层。底部单元（104）包括N型层，P型层和底层本征层。底部本征层包括含有Cu-Zn-Sn的硫族化物（116）。

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