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1. 发明申请

WO2007130333A3 ION IMPLANTATION COMBINED WITH IN SITU OR EX SITU HEAT TREATMENT FOR IMPROVED FIELD EFFECT TRANSISTORS 审中-公开
公开(公告)号：WO2007130333A3
公开(公告)日：2007-11-15
申请号：PCT/US2007/010411
申请日：2007-04-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , BEDELL, Stephen, W. , DESOUZA, Joel, P. , REN, Zhibin , REZNICEK, Alexander , SADANA, Devendra, K. , SAENGER, Katherine, L. , SHAHIDI, Ghavam
发明人： BEDELL, Stephen, W. , DESOUZA, Joel, P. , REN, Zhibin , REZNICEK, Alexander , SADANA, Devendra, K. , SAENGER, Katherine, L. , SHAHIDI, Ghavam
IPC分类号： H01L21/8234 , H01L21/336
摘要： This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (SfD) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined with ex situ heat treatments in a "divided-dose-anneal-in-between" (DDAB) scheme that avoids the need for tooling capable of performing hot implants.

2. 发明申请

WO2007130333A2 ION IMPLANTATION COMBINED WITH IN SITU OR EX SITU HEAT TREATMENT FOR IMPROVED FIELD EFFECT TRANSISTORS 审中-公开
标题翻译：用于改进现场效应晶体管的原位或原位热处理组合的离子植入
公开(公告)号：WO2007130333A2
公开(公告)日：2007-11-15
申请号：PCT/US2007010411
申请日：2007-04-30
申请人： IBM , BEDELL STEPHEN W , DESOUZA JOEL P , REN ZHIBIN , REZNICEK ALEXANDER , SADANA DEVENDRA K , SAENGER KATHERINE L , SHAHIDI GHAVAM
发明人： BEDELL STEPHEN W , DESOUZA JOEL P , REN ZHIBIN , REZNICEK ALEXANDER , SADANA DEVENDRA K , SAENGER KATHERINE L , SHAHIDI GHAVAM
IPC分类号： H01L21/8234
CPC分类号： H01L29/66628 , H01L21/26513 , H01L21/324 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/7848 , H01L29/78618 , H01L29/78684 , Y10S438/909 , Y10S438/943
摘要： This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (SfD) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined withex situ heat treatments in a "divided-dose-anneal-in-between" (DDAB) scheme that avoids the need for tooling capable of performing hot implants.
摘要翻译：本发明教导了将离子注入步骤与原位或非原位热处理组合以避免和/或最小化植入物诱导的非晶化（在绝缘体上的超薄硅层中的FET中的源/漏（SfD）区域的潜在问题）和植入物诱导的应变S / D区域的塑性弛豫（对于通道应变由嵌入的S / D区域与下面的基底层不匹配而提供的应变通道FET的潜在问题）。在第一实施例中，通过在升高的温度下进行离子注入将离子注入与原位热处理组合。在第二实施例中，离子注入在“分剂量退火中间”（DDAB）方案中组合了原位热处理，避免了对能够进行热植入的加工的需要。

3. 发明申请

WO2011115773A3 THIN-BOX METAL BACKGATE EXTREMELY THIN SOI DEVICE 审中-公开
标题翻译：薄金属背板极薄的SOI器件
公开(公告)号：WO2011115773A3
公开(公告)日：2011-12-29
申请号：PCT/US2011027461
申请日：2011-03-08
申请人： IBM , CHAN KEVIN K , REN ZHIBIN , WANG XINHUI
发明人： CHAN KEVIN K , REN ZHIBIN , WANG XINHUI
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L21/7624 , H01L29/66628 , H01L29/66772 , H01L29/78603 , H01L29/78645 , H01L29/78648 , H01L29/78696
摘要： Silicon-on-insulator (SOI) structures with silicon layers less than 20 nm thick are used to form extremely thin silicon-on-insulator (ETSOI) semiconductor devices. ETSOI devices are manufactured using a thin tungsten backgate 101 encapsulated by thin nitride layers 100, 102 to prevent metal oxidation, the tungsten backgate 103 being characterized by its low resistivity. The structure further includes at least one FET having a gate stack 131, 132, 133 formed by a high-K metal gate 132 and a tungsten region 133 superimposed thereon, the footprint of the gate stack utilizing the thin SOI layer 100 as a channel. The SOI structure thus formed controls Vt variations from the thin SOI thickness and dopants therein. The ETSOI high-K metal backgate fully depleted device in conjunction with the thin BOX provides an excellent short channel control and significantly lowers the drain induced bias and sub-threshold swings. The present structure supports the evidence of the stability of the wafer having a tungsten film during thermal processing, and especially during STI and contact formation.
摘要翻译：使用具有小于20nm厚的硅层的绝缘体上硅（SOI）结构来形成极薄的绝缘体上硅（ETSOI）半导体器件。 ETSOI器件使用由薄氮化物层100,102包封的薄钨背板101制造以防止金属氧化，钨背板103的特征在于其低电阻率。该结构还包括至少一个FET，其具有由高K金属栅极132和叠加在其上的钨区域133形成的栅极堆叠131,132,133，栅极堆叠的占用面积利用薄SOI层100作为沟道。如此形成的SOI结构控制了来自薄SOI厚度和其中掺杂剂的Vt变化。 ETSOI高K金属背栅完全耗尽器件与薄型BOX一起提供出色的短通道控制，并显着降低漏极引起的偏置和亚阈值波动。本结构支持在热处理期间具有钨膜的晶片稳定性的证据，并且特别是在STI和接触形成期间。

4. 发明申请

WO2011056336A2 ASYMMETRIC EPITAXY AND APPLICATION THEREOF 审中-公开
标题翻译：非对称外延及其应用
公开(公告)号：WO2011056336A2
公开(公告)日：2011-05-12
申请号：PCT/US2010/051383
申请日：2010-10-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , YIN, Haizhou , WANG, Xinhui , CHAN, Kevin, K. , REN, Zhibin
发明人： YIN, Haizhou , WANG, Xinhui , CHAN, Kevin, K. , REN, Zhibin
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/26586 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation. A source region formed to the second side of the gate structure by the epitaxial growth has a height higher than a drain region formed to the first side of the gate structure by the epitaxial growth. A semiconductor structure formed thereby is also provided.
摘要翻译：本发明提供一种形成不对称场效应晶体管的方法。所述方法包括在半导体衬底的顶部上形成栅极结构，所述栅极结构包括栅极叠层和与所述栅极叠层的侧壁相邻的间隔物，并且具有与所述第一侧相对的第一侧和第二侧; 从所述衬底中的所述栅极结构的第一侧执行成角度的离子注入，从而形成与所述第一侧相邻的离子注入区，其中所述栅极结构防止所述成角度的离子注入到达邻近所述衬底的所述第二侧的所述衬底门结构; 以及在栅极结构的第一和第二侧在衬底上执行外延生长。结果，离子注入区域上的外延生长比不经历离子注入的区域慢得多。通过外延生长形成到栅极结构的第二侧的源极区的高度高于通过外延生长形成到栅极结构的第一侧的漏极区的高度。还提供由此形成的半导体结构。

5. 发明申请

WO2011115773A2 THIN-BOX METAL BACKGATE EXTREMELY THIN SOI DEVICE 审中-公开
标题翻译：薄盒金属背板极薄的SOI器件
公开(公告)号：WO2011115773A2
公开(公告)日：2011-09-22
申请号：PCT/US2011/027461
申请日：2011-03-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHAN, Kevin, K , REN, Zhibin , WANG, Xinhui
发明人： CHAN, Kevin, K , REN, Zhibin , WANG, Xinhui
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L21/7624 , H01L29/66628 , H01L29/66772 , H01L29/78603 , H01L29/78645 , H01L29/78648 , H01L29/78696
摘要： Silicon-on-insulator (SOI) structures with silicon layers less than 20 nm thick are used to form extremely thin silicon-on-insulator (ETSOI) semiconductor devices. ETSOI devices are manufactured using a thin tungsten backgate 101 encapsulated by thin nitride layers 100, 102 to prevent metal oxidation, the tungsten backgate 103 being characterized by its low resistivity. The structure further includes at least one FET having a gate stack 131, 132, 133 formed by a high-K metal gate 132 and a tungsten region 133 superimposed thereon, the footprint of the gate stack utilizing the thin SOI layer 100 as a channel. The SOI structure thus formed controls Vt variations from the thin SOI thickness and dopants therein. The ETSOI high-K metal backgate fully depleted device in conjunction with the thin BOX provides an excellent short channel control and significantly lowers the drain induced bias and sub-threshold swings. The present structure supports the evidence of the stability of the wafer having a tungsten film during thermal processing, and especially during STI and contact formation.
摘要翻译：使用具有小于20nm厚的硅层的绝缘体上硅（SOI）结构来形成极薄的绝缘体上硅（ETSOI）半导体器件。使用由薄氮化物层100,102封装的薄钨背栅101制造ETSOI器件，以防止金属氧化，钨背栅103的特征在于其低电阻率。该结构还包括至少一个FET，其具有由高K金属栅极132和叠加在其上的钨区域133形成的栅极叠层131,132,133，利用薄SOI层100作为沟道的栅极堆叠的覆盖区。这样形成的SOI结构控制了与其中的薄SOI厚度和掺杂剂的Vt变化。 ETSOI高K金属背栅完全耗尽器件与薄BOX结合提供了出色的短通道控制，并显着降低了漏极引起的偏置和次阈值摆幅。本结构支持在热处理期间具有钨膜的晶片的稳定性的证据，特别是在STI和接触形成期间。

6. 发明申请

WO2011056336A3 ASYMMETRIC EPITAXY AND APPLICATION THEREOF 审中-公开
标题翻译：不对称外延及其应用
公开(公告)号：WO2011056336A3
公开(公告)日：2011-07-28
申请号：PCT/US2010051383
申请日：2010-10-05
申请人： IBM , YIN HAIZHOU , WANG XINHUI , CHAN KEVIN K , REN ZHIBIN
发明人： YIN HAIZHOU , WANG XINHUI , CHAN KEVIN K , REN ZHIBIN
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/26586 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation. A source region formed to the second side of the gate structure by the epitaxial growth has a height higher than a drain region formed to the first side of the gate structure by the epitaxial growth. A semiconductor structure formed thereby is also provided.
摘要翻译：本发明提供了形成非对称场效应晶体管的方法。所述方法包括在半导体衬底的顶部上形成栅极结构，所述栅极结构包括栅极叠层和邻近所述栅极堆叠的侧壁的间隔物，并且具有与所述第一侧相对的第一侧和第二侧; 从衬底中的栅极结构的第一侧进行成角度的离子注入，从而形成与第一侧相邻的离子注入区域，其中栅极结构防止成角度的离子注入到达邻近第二侧的衬底门结构; 以及在栅极结构的第一和第二侧在衬底上进行外延生长。结果，在离子注入区域上的外延生长比经历无离子注入的区域慢得多。通过外延生长形成到栅极结构的第二侧的源极区域的高度高于通过外延生长形成于栅极结构的第一侧的漏极区域的高度。还提供了由此形成的半导体结构。

7. 发明申请

WO2009053327A1 METHOD FOR FABRICATING SUPER-STEEP RETROGRADE WELL MOSFET ON SOI OR BULK SILICON SUBSTRATE, AND DEVICE FABRICATED IN ACCORDANCE WITH THE METHOD 审中-公开
标题翻译：在SOI或大块硅衬底上制造超级退火井MOSFET的方法，以及根据该方法制造的器件
公开(公告)号：WO2009053327A1
公开(公告)日：2009-04-30
申请号：PCT/EP2008/064113
申请日：2008-10-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , CAI, Jin , MAJUMDAR, Amlan , NING, Tak, Hung , REN, Zhibin
发明人： CAI, Jin , MAJUMDAR, Amlan , NING, Tak, Hung , REN, Zhibin
IPC分类号： H01L29/10 , H01L29/78 , H01L21/336
CPC分类号： H01L29/1083 , H01L21/28052 , H01L21/28088 , H01L21/28247 , H01L29/165 , H01L29/4933 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well (SSRW) implant doping profile; annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon and, prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate. The substrate may be a bulk Si substrate or a Si-on-insulator substrate. The method accommodates the use of an oxynitride gate stack structure or a high dielectric constant oxide/metal (high-K/metal) gate stack structure. The various thermal processes used during fabrication are selected/controlled so as to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon.
摘要翻译：提供了一种制造半导体器件的方法，其中该方法包括提供由晶体硅构成的衬底; 在晶体硅中注入接地平面以与衬底的表面相邻，所述接地平面被植入以呈现期望的超陡逆向阱（SSRW）注入掺杂分布; 使用基本上无扩散的热退火来退火植入物损伤，以在晶体硅中保持期望的超陡逆向阱注入掺杂分布，并且在执行浅沟槽隔离工艺之前，在衬底的表面上沉积硅帽层。衬底可以是体积Si衬底或绝缘体上硅衬底。该方法适应于使用氧氮化物栅叠层结构或高介电常数氧化物/金属（高K /金属）栅叠层结构。选择/控制在制造期间使用的各种热处理，以便在晶体硅中保持期望的超陡逆向阱注入掺杂分布。

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