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1. 发明申请

WO2010008748A1 SPACER FILL STRUCTURE, METHOD AND DESIGN STRUCTURE FOR REDUCING DEVICE VARIATION 审中-公开
标题翻译：用于减小装置变化的间隔件填充结构，方法和设计结构
公开(公告)号：WO2010008748A1
公开(公告)日：2010-01-21
申请号：PCT/US2009/047719
申请日：2009-06-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ANDERSON, Brent, A. , BRYANT, Andres , RANKIN, Jed, H. , NOWAK, Edward, J.
发明人： ANDERSON, Brent, A. , BRYANT, Andres , RANKIN, Jed, H. , NOWAK, Edward, J.
IPC分类号： H01L21/334
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： A design structure (100, FIG. 1a) is provided for spacer fill structures (100 and 300) and, more particularly, spacer fill structures (100 and 300), a method of manufacturing and a design structure for reducing device variation is provided. The structure includes a plurality of dummy fill shapes (100) in different areas of a device which are configured such that gate perimeter to gate area ratio will result in a total perimeter density being uniform across a chip.
摘要翻译：提供用于间隔件填充结构（100和300）的设计结构（100，图1a），并且更具体地提供间隔件填充结构（100和300），制造方法和设计提供了用于减小设备变化的结构。该结构包括在器件的不同区域中的多个虚拟填充形状（100），其被配置为使得栅极周边与栅极面积之比将导致整个芯片上的总周边密度是均匀的。

2. 发明申请

WO2006044349A2 PLANAR SUBSTRATE DEVICES INTEGRATED WITH FINFETS AND METHOD OF MANUFACTURE 审中-公开
标题翻译：与FinFET集成的平面基板器件和制造方法
公开(公告)号：WO2006044349A2
公开(公告)日：2006-04-27
申请号：PCT/US2005/036471
申请日：2005-10-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ANDERSON, Brent, A. , NOWAK, Edward, J. , RANKIN, Jed, H.
发明人： ANDERSON, Brent, A. , NOWAK, Edward, J. , RANKIN, Jed, H.
IPC分类号： H01L21/8234
CPC分类号： H01L29/785 , H01L21/823821 , H01L21/823828 , H01L21/823878 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： A planar substrate device (100) integrated with fin field effect transistors (FinFETs) and a method of manufâcture comprises a silicon-on-insulator (SOI) wafer (101) comprising a substrate (103); a buried insulator layer (105) over the substrate (103); and a semiconductor layer (115) over the buried insulator layer (105). The structure (100) further comprises a FinFET (130) over the buried insulator layer (105) and a field effect transistor (FET) (131) integrated in the substrate (103), wherein the FET (127) gate is planar to the FinFET gate (125). The structure (100) further comprises retrograde well regions (104, 106, 108, 110) configured in the substrate (103). In one embodiment, the structure (100) further comprises a shallow trench isolation region (111) configured in the substrate (103).
摘要翻译：与鳍状场效应晶体管（FinFET）集成的平面基板装置（100）和制造方法包括：包含基板（103）的绝缘体上硅（SOI）晶片（101）; 在所述衬底（103）上方的掩埋绝缘体层（105）; 以及在所述掩埋绝缘体层（105）上方的半导体层（115）。所述结构（100）还包括在所述掩埋绝缘体层（105）上的FinFET（130）和集成在所述衬底（103）中的场效应晶体管（FET）（131），其中所述FET（127）栅极与 FinFET门（125）。结构（100）还包括配置在基底（103）中的逆行井区（104,106,108,110）。在一个实施例中，结构（100）还包括构造在衬底（103）中的浅沟槽隔离区（111）。

3. 发明申请

WO2011059639A2 DAMASCENE GATE HAVING PROTECTED SHORTING REGIONS 审中-公开
标题翻译：具有保护区的大马士革堡
公开(公告)号：WO2011059639A2
公开(公告)日：2011-05-19
申请号：PCT/US2010/053091
申请日：2010-10-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ANDERSON, Brent, A. , NOWAK, Edward, J. , RANKIN, Jed, H.
发明人： ANDERSON, Brent, A. , NOWAK, Edward, J. , RANKIN, Jed, H.
CPC分类号： H01L21/28247 , H01L21/76834 , H01L21/76897
摘要： The present invention relates generally to semiconductor devices and, more specifically, to damascene gates (100; Fig 1C) having protected shorting regions (60) and related methods for their manufacture. A first aspect of the invention provides a method of forming a damascene gate (100) with protected shorting regions (60), the method comprising: forming a damascene gate having: a gate dielectric atop a substrate (12); a gate conductor (40) atop the gate dielectric; a conductive liner laterally adjacent the gate conductor (30); a spacer between the conductive liner and the substrate (20); and a first dielectric atop the gate conductor (60); removing a portion of the conductive liner (30); and depositing a second dielectric (60) atop a remaining portion of the conductive liner (30), such that the second dielectric is laterally adjacent both the first dielectric and the gate.
摘要翻译：本发明一般涉及半导体器件，更具体地，涉及具有受保护的短路区域（60）的镶嵌栅极（100;图1C）及其制造的相关方法。本发明的第一方面提供了一种形成具有受保护的短路区域（60）的镶嵌栅极（100）的方法，所述方法包括：形成镶嵌栅极，其具有在基板（12）的顶部的栅极电介质; 位于栅极电介质顶部的栅极导体（40）; 横向邻近所述栅极导体（30）的导电衬垫; 导电衬垫和衬底（20）之间的间隔物; 和位于所述栅极导体（60）顶部的第一电介质; 去除所述导电衬套（30）的一部分; 以及在所述导电衬套（30）的剩余部分的顶部沉积第二电介质（60），使得所述第二电介质横向相邻于所述第一电介质和所述栅极。

4. 发明申请

WO2005045900A2 METHOD OF FABRICATING A FINFET 审中-公开
标题翻译：制造FINFET的方法
公开(公告)号：WO2005045900A2
公开(公告)日：2005-05-19
申请号：PCT/US2004/037029
申请日：2004-11-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ANDERSON, Brent, A. , NOWAK, Edward, J. , RANKIN, Jed, H.
发明人： ANDERSON, Brent, A. , NOWAK, Edward, J. , RANKIN, Jed, H.
IPC分类号： H01L
CPC分类号： H01L29/785 , H01L29/66795
摘要： A FinFET structure and method of forming a FinFET device. The method includes: (a) providing a semiconductor substrate (100), (b) forming a dielectric layer (110) on a top surface (105) of the substrate (100); (c) forming a silicon fin (135) on a top surface (115) of the dielectric layer (110); (d) forming a protective layer (160) on at least one sidewall (150A) of the fin (135); and (e) removing the protective layer (160) from the at least one sidewall (150A) in a channel region (175) of the fin (135). In a second embodiment, the protective layer (160) is converted to a protective spacer (210A).
摘要翻译： FinFET结构和形成FinFET器件的方法。该方法包括：（a）提供半导体衬底（100），（b）在衬底（100）的顶表面（105）上形成电介质层（110）; （c）在介电层（110）的顶表面（115）上形成硅翅片（135）; （d）在翅片（135）的至少一个侧壁（150A）上形成保护层（160）; 和（e）在所述翅片（135）的通道区域（175）中从所述至少一个侧壁（150A）移除所述保护层（160）。在第二实施例中，保护层（160）被转换成保护间隔物（210A）。

5. 发明申请

WO2005064682A1 SEMICONDUCTOR MEMORY DEVICE WITH INCREASED NODE CAPACITANCE 审中-公开
标题翻译：具有增加的节点电容的半导体存储器件
公开(公告)号：WO2005064682A1
公开(公告)日：2005-07-14
申请号：PCT/US2003/039026
申请日：2003-12-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ANDERSON, Brent, A. , BRYANT, Andres , NOWAK, Edward, J.
发明人： ANDERSON, Brent, A. , BRYANT, Andres , NOWAK, Edward, J.
IPC分类号： H01L27/148
CPC分类号： H01L27/1211 , H01L27/11 , H01L29/66795 , H01L29/785
摘要： An integrated circuit semiconductor memory device (100) has a first dielectric layer (116) characterized as the BOX layer absent from a portion (130) of the substrate (112) under the gate of a storage transistor to increase the gate-to-substrate capacitance and thereby reduce the soft error rate. A second dielectric layer (132) having a property different from the first dielectric layer at least partly covers that portion (130) of the substrate. The device may be a FinFET device including a fin (122) and a gate dielectric layer (124, 126) between the gate and the fin, with the second dielectric layer having less leakage than the gate dielectric layer.
摘要翻译：集成电路半导体存储器件（100）具有第一介电层（116），其特征在于，在存储晶体管的栅极下方的衬底（112）的部分（130）中不存在BOX层，以增加栅极到衬底电容，从而降低软错误率。具有不同于第一电介质层的性质的第二电介质层（132）至少部分地覆盖衬底的该部分（130）。器件可以是FinFET器件，其包括在栅极和鳍之间的鳍（122）和栅极电介质层（124,126），其中第二介电层具有比栅极电介质层更少的泄漏。

6. 发明申请

WO2009012295A2 FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE 审中-公开
标题翻译：具有合并源/排水硅酸盐的FIN型场效应晶体管结构及形成结构的方法
公开(公告)号：WO2009012295A2
公开(公告)日：2009-01-22
申请号：PCT/US2008/070143
申请日：2008-07-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ANDERSON, Brent, A. , BRYANT, Andres , ELLIS-MONAGHAN, John, J. , NOWAK, Edward, J.
发明人： ANDERSON, Brent, A. , BRYANT, Andres , ELLIS-MONAGHAN, John, J. , NOWAK, Edward, J.
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： Disclosed herein are embodiments of a multiple fin fin-type field effect transistor (350) (i.e., a multiple fin dual-gate or tri-gate field effect transistor) (300, 300a, 300b) in which the multiple fins arc partially or completely merged by a highly conductive material (360a, 360b) (e.g., a metal suicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions (375a-b). Merging the semiconductor fins (350) in this manner also allows each of the source/drain regions (375a-b) to be contacted by a single contact via as well as more flexible placement of that contact via.
摘要翻译：这里公开了多鳍片式场效应晶体管（350）（即，多鳍式双栅极或三栅极场效应晶体管）（300,300a，300b）的实施例，其中多个鳍部分或完全地部分由高导电性材料（360a，360b）（例如，金属硅化物）合并。以这种方式合并散热片允许串联电阻最小化，栅极和源极/漏极区域（375a-b）之间的寄生电容几乎不增加（如果有的话）。以这种方式合并半导体散热片（350）还允许源极/漏极区域（375a-b）中的每一个被单个接触通孔接触以及该接触通孔的更灵活的放置。

7. 发明申请

WO2009012276A2 ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD 审中-公开
标题翻译：不对称场效应晶体管结构与方法
公开(公告)号：WO2009012276A2
公开(公告)日：2009-01-22
申请号：PCT/US2008/070102
申请日：2008-07-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ANDERSON, Brent, A. , BRYANT, Andres , CLARK, William, F. , NOWAK, Edward, J.
发明人： ANDERSON, Brent, A. , BRYANT, Andres , CLARK, William, F. , NOWAK, Edward, J.
IPC分类号： H01L21/335
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7834 , H01L29/7835
摘要： Disclosed are embodiments of an asymmetric field effect transistor structure (200a-c) and a method of forming the structure in which both series resistance in the source region (204, 304) (Rs) and gate (210, 310) to drain ((205, 305) capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay) Specifically, different heights (214, 215) of the source (204) and drain regions (205) and/or different distances (351, 352) between the source (304) and drain regions (305) and the gate (210, 310) are tailored to minimize series resistance in the source region (204, 305) (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate (210, 310) to drain (205, 305) capacitance (i.e., in order to simultaneously ensure that gate ( 210, 310) to drain (205, 305) capacitance is less than a predetermined capacitance value).
摘要翻译：公开了非对称场效应晶体管结构（200a-c）的实施例以及形成其中源极区（204,304）（Rs）和栅极（210,310）中的串联电阻都流到（（为了提供最佳性能（即，以最小的电路延迟来提供改进的驱动电流），电容（C，C）被减小。具体地，源（204）和漏极区（205）的不同高度（214,215）在源极（304）和漏极区域（305）和栅极（210,310）之间的不同距离（351,352）被定制以最小化源极区域（204,305）中的串联电阻（即，按顺序以确保串联电阻小于预定电阻值），并且为了同时使栅极（210,310）最小化以漏极（205,305）的电容（即，为了同时确保栅极（210,310）至漏极（205,305）电容小于预定的电容值）。

8. 发明申请

WO2010138278A2 INTEGRATED CIRCUIT DEVICE WITH DEEP TRENCH ISOLATION REGIONS FOR ALL INTER-WELL AND INTRA-WELL ISOLATION AND WITH A SHARED CONTACT TO A JUNCTION BETWEEN ADJACENT DEVICE DIFFUSION REGIONS AND AN UNDERLYING FLOATING WELL SECTION 审中-公开
标题翻译：具有深度分离隔离区域的集成电路设备，用于所有内部和内部隔离以及与共享设备扩展区域和下面的浮动区段之间的连接的共享接触
公开(公告)号：WO2010138278A2
公开(公告)日：2010-12-02
申请号：PCT/US2010/033469
申请日：2010-05-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ANDERSON, Brent, A. , BRYANT, Andres , NOWAK, Edward, J.
发明人： ANDERSON, Brent, A. , BRYANT, Andres , NOWAK, Edward, J.
IPC分类号： H01L21/8244 , H01L27/11
CPC分类号： H01L27/0207 , H01L21/823481 , H01L21/823493 , H01L27/092 , H01L27/11 , H01L27/1104
摘要： Disclosed are embodiments of an improved integrated circuit device structure (200) (e.g., a static random access memory array structure or other integrated circuit device structure incorporating both P-type and N-type devices) (121a and 121b) and a method of forming the structure that uses DTI regions (160) for all inter- well and intra- well isolation and, thereby provides a low-cost isolation scheme that avoids FET width variations due to STI-DTI misalignment. Furthermore, because the DTI regions (160) used for intra- well isolation effectively create some floating well sections, (203) which must each be connected to a supply voltage (e.g., Vdd) (280) to prevent threshold voltage (Vt) variations, the disclosed integrated circuit device also includes a shared contact (280) to a junction between the diffusion regions (221 and 222) of adjacent devices (121a and 121b) and an underlying floating well section (205). This shared contact (280) eliminates the cost and area penalties that would be incurred if a discrete supply voltage contact was required for each floating well section (205).
摘要翻译：公开了改进的集成电路器件结构（200）（例如，并入P型和N型器件的静态随机存取存储器阵列结构或其他集成电路器件结构）（121a和121b）的实施例和形成方法使用DTI区域（160）进行所有井间和井内隔离的结构，从而提供了一种低成本的隔离方案，避免了由于STI-DTI失准导致的FET宽度变化。此外，由于用于井内隔离的DTI区域（160）有效地产生一些浮动井区段（203），其必须各自连接到电源电压（例如Vdd）（280），以防止阈值电压（Vt）变化所公开的集成电路器件还包括到相邻器件（121a和121b）的扩散区域（221和222）与下面的浮动阱区段（205）之间的连接处的共用触点（280）。这种共享联系人（280）消除了如果每个浮动井段（205）需要离散的电源电压接触，将会产生的成本和面积的惩罚。

9. 发明申请

WO2008064227A2 DUAL STRESS DEVICE AND METHOD 审中-公开
标题翻译：双应力装置和方法
公开(公告)号：WO2008064227A2
公开(公告)日：2008-05-29
申请号：PCT/US2007/085246
申请日：2007-11-20
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ANDERSON, Brent, A. , BRYANT, Andres , NOWAK, Edward, J.
发明人： ANDERSON, Brent, A. , BRYANT, Andres , NOWAK, Edward, J.
IPC分类号： H01L29/786 , H01L29/78 , H01L21/84 , H01L21/336
CPC分类号： H01L29/785 , H01L21/31155 , H01L21/76283 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1203 , H01L29/1037 , H01L29/66621 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/7849
摘要： A semiconductor device (80,85) including semiconductor material (35,40) having a bend and a trench feature formed at the bend, and a gate structure (45,50) at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.
摘要翻译：包括半导体材料（35,40）的半导体器件（80,85），其具有在弯曲处形成的弯曲部和沟槽特征，以及至少部分地设置在沟槽特征中的栅极结构（45,50）。一种制造半导体结构的方法，包括在层上形成具有沟槽特征的半导体材料，在沟槽特征中至少部分地形成栅极结构，以及弯曲半导体材料，使得在反转沟道中的半导体材料中产生应力栅结构的区域。

10. 发明申请

WO2012061167A1 ASYMMETRIC HETERO-STRUCTURE FET AND METHOD OF MANUFACTURE 审中-公开
标题翻译：不对称异质结构FET及其制造方法
公开(公告)号：WO2012061167A1
公开(公告)日：2012-05-10
申请号：PCT/US2011/057779
申请日：2011-10-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , ANDERSON, Brent, A. , JOHNSON, Jeffrey, B. , NOWAK, Edward, J. , ROBINSON, Robert, R.
发明人： ANDERSON, Brent, A. , JOHNSON, Jeffrey, B. , NOWAK, Edward, J. , ROBINSON, Robert, R.
IPC分类号： H01L29/10 , H01L21/336 , H01L29/165 , H01L29/49 , H01L29/51
CPC分类号： H01L29/1054 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/66659
摘要： An asymmetric hetero-structure FET and method of manufacture is provided. The structure includes a semiconductor substrate (10) and an epitaxially grown semiconductor layer (15) on the semiconductor substrate (10). The epitaxially grown semiconductor layer (15) includes an alloy having a band structure and thickness that confines inversion carriers in a channel region, and a thicker portion extending deeper into the semiconductor structure at a doped edge to avoid confinement of the inversion carriers at the doped edge.
摘要翻译：提供了非对称异质结构FET及其制造方法。该结构包括在半导体衬底（10）上的半导体衬底（10）和外延生长的半导体层（15）。外延生长的半导体层（15）包括具有限制沟道区域中的反转载流子的带结构和厚度的合金，以及在掺杂边缘处更深地延伸到半导体结构中的较厚部分，以避免掺杂的反转载流子的约束边缘。

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