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1. 发明申请

WO2013101028A1 AVD HARDMASK FOR DAMASCENE PATTERNING 审中-公开
公开(公告)号：WO2013101028A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067764
申请日：2011-12-29
申请人： INTEL CORPORATION , BRAIN, Ruth A. , FISCHER, Kevin J. , CHILDS, Michael A.
发明人： BRAIN, Ruth A. , FISCHER, Kevin J. , CHILDS, Michael A.
IPC分类号： H01L21/3205 , H01L21/28
CPC分类号： H01L23/5329 , H01L21/311 , H01L21/31144 , H01L21/76802 , H01L21/76807 , H01L23/49827 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.
摘要翻译：一种包括在集成电路结构的接触点上形成介电层的方法; 在所述电介质层的表面上形成包括电介质材料的硬掩模; 以及使用所述硬掩模作为图案在所述电介质层中形成至少一个通孔到所述接触点。一种包括电路基板的装置，包括至少一个包括接触点的活性层; 所述至少一个有源层上的介电层; 包括其中具有用于互连材料的至少一个开口的电介质材料的硬掩模; 以及在硬掩模的至少一个开口中并通过介电层到接触点的互连材料。

2. 发明申请

WO2014100278A1 LANDING STRUCTURE FOR THROUGH-SILICON VIA 审中-公开
标题翻译：通过硅的接地结构
公开(公告)号：WO2014100278A1
公开(公告)日：2014-06-26
申请号：PCT/US2013/076289
申请日：2013-12-18
申请人： INTEL CORPORATION , PELTO, Christopher M. , BRAIN, Ruth A. , LEE, Kevin J. , LEATHERMAN, Gerald S.
发明人： PELTO, Christopher M. , BRAIN, Ruth A. , LEE, Kevin J. , LEATHERMAN, Gerald S.
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , H01L21/76879 , H01L21/76898 , H01L23/522 , H01L23/5226 , H01L2224/16225 , H01L2924/15311
摘要： Embodiments of the present disclosure describe techniques and configurations associated with forming a landing structure for a through-silicon via (TSV) using interconnect structures of interconnect layers. In eon embodiment, an apparatus includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a device layer disposed on the first surface of the semiconductor substrate, the device layer including one or more transistor devices, interconnect layers disposed on the device layer, the interconnect layers including a plurality of interconnect structures and one or more through-silicon vias disposed between the first surface and the second surface, wherein the plurality of interconnect structures include interconnect structures that are electrically coupled with the one or more TSVs and configured to provide one or more corresponding landing structures of the one or more TSVs. Other embodiments may be described and/or claimed
摘要翻译：本公开的实施例描述与使用互连层的互连结构形成用于穿硅通孔（TSV）的着陆结构相关联的技术和配置。在实施例中，一种装置包括具有第一表面和与第一表面相对的第二表面的半导体衬底，设置在半导体衬底的第一表面上的器件层，器件层包括一个或多个晶体管器件，布置的互连层在所述器件层上，所述互连层包括多个互连结构以及设置在所述第一表面和所述第二表面之间的一个或多个穿硅通孔，其中所述多个互连结构包括互连结构，所述互连结构与所述一个或多个 TSV并且被配置为提供一个或多个TSV的一个或多个相应的着陆结构。可以描述和/或要求保护其他实施例

3. 发明申请

WO2019066978A1 CONDUCTIVE VIA AND METAL LINE END FABRICATION AND STRUCTURES RESULTING THEREFROM 审中-公开
公开(公告)号：WO2019066978A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/054641
申请日：2017-09-30
申请人： INTEL CORPORATION , WALLACE, Charles H. , PATEL, Reken , PARK, Hyunsoo , HARAN, Mohit K. , BASU, Debashish , WARD, Curtis W. , BRAIN, Ruth A.
发明人： WALLACE, Charles H. , PATEL, Reken , PARK, Hyunsoo , HARAN, Mohit K. , BASU, Debashish , WARD, Curtis W. , BRAIN, Ruth A.
IPC分类号： H01L21/768
摘要： Conductive via and metal line end fabrication is described. In an example, an interconnect structure includes a first inter-layer dielectric (ILD) on a hardmask layer, where the ILD includes a first ILD opening and a second ILD opening. The interconnect structure further includes an etch stop layer (ESL) on the ILD layer, where the ESL includes a first ESL opening aligned with the first ILD opening to form a first via opening, and where the ESL layer includes a second ESL opening aligned with the second ILD opening. The interconnect structure further includes a first via in the first via opening, a second ILD layer on the first ESL, and a metal line in the second ILD layer, where the metal line is in contact with the first via, and where the metal line includes a first metal opening, and where the metal line includes a second metal opening aligned with the second ILD opening and the ESL opening to form a second via opening. The interconnect structure further includes a metal line end in the first metal opening and further includes a second via in the metal line, where the second via is in the second via opening.

4. 发明申请

WO2013070221A1 RECESSED BOTTOM-ELECTRODE CAPACITORS AND METHODS OF ASSEMBLING SAME 审中-公开
标题翻译：接触底电极电容器及其组装方法
公开(公告)号：WO2013070221A1
公开(公告)日：2013-05-16
申请号：PCT/US2011/060113
申请日：2011-11-10
申请人： INTEL CORPORATION , BRAIN, Ruth A. , STEIGERWALD, Joseph M.
发明人： BRAIN, Ruth A. , STEIGERWALD, Joseph M.
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/28
CPC分类号： H01L28/40 , G06F1/16 , H01L27/108 , H01L27/10852 , H01L27/10894 , H01L28/91
摘要： A capacitor-over-bitline structure includes a bottom electrode that has an open vessel form factor. The bottom-electrode form factor includes a floor, rectilinear sidewalls, and a rim that defines the topmost feature. A capacitor dielectric film contacts and covers the floor, the sidewalls, and the rim. A top electrode has a convex form factor that complements the concave bottom-electrode form factor. A process of forming the capacitor-over-bitline structure by spinning on a reflowable sacrificial material such as an oxide that covers both logic and memory portions of a semiconductive device, followed by a polish-back process and a recessing etch of the bottom electrode.
摘要翻译：电容器 - 位线结构包括具有开放容器外形的底部电极。底部电极形状因子包括底板，直线侧壁和限定最顶端特征的边缘。电容器电介质膜接触并覆盖地板，侧壁和边缘。顶部电极具有补充凹底电极形状因子的凸形形状因子。通过在可覆盖的牺牲材料（例如覆盖半导体器件的逻辑和存储器部分的氧化物）上旋转形成电容器 - 位线结构的过程，接着是底部电极的抛光处理和凹陷蚀刻。

5. 发明申请

WO2019132944A1 POWER SHARED CELL ARCHITECTURE 审中-公开
公开(公告)号：WO2019132944A1
公开(公告)日：2019-07-04
申请号：PCT/US2017/068820
申请日：2017-12-28
申请人： INTEL CORPORATION , KUMAR, Ranjith , BOHR, Mark T. , BRAIN, Ruth A. , NABORS, Marni , WU, Tai-Hsuan , CHAKRAVARTY, Sourav
发明人： KUMAR, Ranjith , BOHR, Mark T. , BRAIN, Ruth A. , NABORS, Marni , WU, Tai-Hsuan , CHAKRAVARTY, Sourav
IPC分类号： H01L27/06 , H01L27/02
摘要： An integrated circuit structure includes a metal level comprising a plurality of interconnect lines along a first direction. A cell is on the metal level, wherein one or more of the plurality of interconnect lines that extend through the cell comprise a power shared track that is segmented inside the cell into one or more power segments and one or more signal segments so that both power and signals share a same track.

6. 发明申请

WO2016105402A1 VIA BLOCKING LAYER 审中-公开
标题翻译：通过阻塞层
公开(公告)号：WO2016105402A1
公开(公告)日：2016-06-30
申请号：PCT/US2014/072252
申请日：2014-12-23
申请人： INTEL CORPORATION
发明人： HOURANI, Rami , KRYSAK, Marie , GSTREIN, Florian , BRAIN, Ruth A. , BOHR, Mark T.
IPC分类号： H01L21/3205 , H01L21/28
CPC分类号： H01L21/76807 , H01L21/76831 , H01L23/3171 , H01L23/5226 , H01L23/528 , H01L2221/1031 , H01L2221/1063
摘要： Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.
摘要翻译：公开了用于在给定互连层内绝缘或电隔离选择通孔的技术，因此导电布线可跳过那些选择的隔离通孔以到达同一层中的其它通孔或互连。可以根据需要在给定互连中的任何数量的位置选择性地实现这种通孔阻挡层。还提供了用于形成通孔阻挡层的技术，包括使用牺牲钝化层促进形成通孔阻挡层的绝缘体材料的选择性沉积的第一种方法，第二种使用湿可隐藏聚合物配方的旋涂的方法促进形成通孔阻挡层的绝缘体材料的选择性沉积，以及使用纳米颗粒配方的旋涂以促进形成通孔阻挡层的绝缘体材料的选择性沉积的第三种方法。避免了通常与保形沉积工艺相关的有害蚀刻工艺。

7. 发明申请

WO2018063330A1 PLUG & TRENCH ARCHITECTURES FOR INTEGRATED CIRCUITS & METHODS OF MANUFACTURE 审中-公开
标题翻译：用于集成电路的插头和插槽结构及制造方法
公开(公告)号：WO2018063330A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054799
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： WALLACE, Charles H. , PAIK, Marvin Y. , PARK, Hyunsoo , HARAN, Mohit K. , KAPLAN, Alexander F. , BRAIN, Ruth A.
IPC分类号： H01L21/768
CPC分类号： H01L21/76816 , H01L21/31144 , H01L21/76808 , H01L21/76897 , H01L23/5226 , H01L23/528
摘要： Methods and architectures for IC interconnect trenches, and trench plugs that define separations between two adjacent trench ends. Plugs and trenches may be defined through a multiple patterning process. An upper grating pattern may be summed with a plug keep pattern into a pattern accumulation layer. The pattern accumulation layer may be employed to define plug masks. A lower grating pattern may then be summed with the plug masks to define a pattern in trench ILD material, which can then be backfilled with interconnect metallization. As such, a complex damascene interconnect structure can be fabricated at the scaled-down geometries achievable with pitch-splitting techniques. In some embodiments, the trenches are located at spaces between first spacer masks defined in a patterning process associated with the first grating pattern while the plug masks are located based on a tone-inversion of second spacer masks associated with the second grating pattern.
摘要翻译： IC互连沟槽的方法和体系结构以及限定两个相邻沟槽端部之间分隔的沟槽插塞。插头和沟槽可以通过多重构图过程来定义。上光栅图案可以与插塞保持图案相加成图案堆积层。图案积累层可以用来定义插塞掩模。然后可以将下光栅图案与插塞掩模相加以在沟槽ILD材料中限定图案，然后可以用互连金属化来回填。这样，复杂的镶嵌互连结构可以用分节技术实现的按比例缩小的几何形状来制造。在一些实施例中，沟槽在与第一光栅图案相关的图案化工艺限定的第一间隔物掩模之间的空间位于当插头掩模基于与所述第二栅格图案相关联的第二间隔物掩模的音调反转位于

8. 发明申请

WO2016105350A1 METHOD AND STRUCTURE TO CONTACT TIGHT PITCH CONDUCTIVE LAYERS WITH GUIDED VIAS USING ALTERNATING HARDMASKS AND ENCAPSULATING ETCHSTOP LINER SCHEME 审中-公开
标题翻译：使用替代硬件和封装ETCHSTOP LINER程序与引导VIAS接触的垂直导引层的方法和结构
公开(公告)号：WO2016105350A1
公开(公告)日：2016-06-30
申请号：PCT/US2014/071999
申请日：2014-12-22
申请人： INTEL CORPORATION
发明人： CHAWLA, Jasmeet S. , BRAIN, Ruth A. , SCHENKER, Richard E. , SINGH, Kanwal Jit , MYERS, Alan M.
IPC分类号： H01L21/768 , H01L21/31
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/485 , H01L21/486 , H01L21/76804 , H01L21/76808 , H01L21/76816 , H01L21/76832 , H01L21/76834 , H01L21/76883 , H01L21/76897 , H01L23/5226 , H01L23/5329 , H01L23/53295 , H01L2224/16225
摘要： Interconnect structures having alternating dielectric caps and an etchstop liner for semiconductor devices and methods for manufacturing such devices are described. According to an embodiment, an interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. The interconnect structure may also include one or more first interconnect lines in the ILD. A first dielectric cap may be positioned above a top surface of each of the first interconnect lines. Additional embodiments include one or more second interconnect lines in the ILD that are arranged in an alternating pattern with the first interconnect lines. A second dielectric cap may be formed above a top surface of each of the second interconnect lines. Embodiments may also include an etchstop liner that is formed over top surfaces of the first dielectric caps.
摘要翻译：描述了具有交替电介质盖的互连结构和用于半导体器件的蚀刻衬垫以及用于制造这种器件的方法。根据实施例，互连结构可以包括在ILD的顶表面上方的第一硬掩模层的层间电介质（ILD）。互连结构还可以包括ILD中的一个或多个第一互连线。第一电介质盖可以位于每个第一互连线的顶表面上方。另外的实施例包括ILD中以与第一互连线交替模式布置的一个或多个第二互连线。第二电介质盖可以形成在每个第二互连线的顶表面之上。实施例还可以包括形成在第一电介质盖的顶表面上的蚀刻阻挡衬里。

9. 发明申请

WO2018118090A1 CONDUCTIVE CAP-BASED APPROACHES FOR CONDUCTIVE VIA FABRICATION AND STRUCTURES RESULTING THEREFROM 审中-公开
公开(公告)号：WO2018118090A1
公开(公告)日：2018-06-28
申请号：PCT/US2016/068583
申请日：2016-12-23
申请人： INTEL CORPORATION
发明人： GSTREIN, Florian , HAN, Eungnak , HOURANI, Rami , BRAIN, Ruth A. , NYHUS, Paul A. , CHANDHOK, Manish , WALLACE, Charles H. , TSANG, Chi-Hwa
IPC分类号： H01L21/768
摘要： Conductive cap-based approaches for conductive via fabrication is described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer above a substrate. Each of the conductive lines is recessed relative to an uppermost surface of the ILD layer. A plurality of conductive caps is on corresponding ones of the plurality of conductive lines, in recess regions above each of the plurality of conductive lines. A hardmask layer is on the plurality of conductive caps and on the uppermost surface of the ILD layer. The hardmask layer includes a first hardmask component on and aligned with the plurality of conductive caps, and a second hardmask component on an aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a conductive cap of one of the plurality of conductive lines.

10. 发明申请

WO2017222515A1 VIA BLOCKING LAYER 审中-公开
标题翻译：威盛阻塞层
公开(公告)号：WO2017222515A1
公开(公告)日：2017-12-28
申请号：PCT/US2016/038686
申请日：2016-06-22
申请人： INTEL CORPORATION
发明人： HOURANI, Rami , KRYSAK, Marie , GSTREIN, Florian , BRAIN, Ruth A. , BOHR, Mark T. , CHANDHOK, Manish
IPC分类号： H01L21/768 , H01L21/02
摘要： An embodiment includes an apparatus comprising: a metal layer comprising a plurality of interconnect lines on a plurality of vias; an additional metal layer comprising first, second, and third interconnect lines on first, second, and third vias; the first and third vias coupling the first and third interconnect lines to two of the plurality of interconnect lines; a lateral interconnect, included entirely within the additional metal layer, directly connected to each of the first, second, and third interconnect lines; and an insulator layer included entirely between two sidewalls of the second via. Other embodiments are described herein.
摘要翻译：一个实施例包括一种装置，该装置包括：在多个通孔上包括多个互连线的金属层; 附加金属层，其包括第一，第二和第三通孔上的第一，第二和第三互连线; 第一和第三通孔将第一和第三互连线连接到多条互连线中的两条; 完全包括在所述附加金属层内的横向互连直接连接到所述第一，第二和第三互连线中的每一个; 以及完全包括在第二通孔的两个侧壁之间的绝缘层。这里描述了其他实施例。

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