专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2019066978A1 CONDUCTIVE VIA AND METAL LINE END FABRICATION AND STRUCTURES RESULTING THEREFROM 审中-公开
公开(公告)号：WO2019066978A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/054641
申请日：2017-09-30
申请人： INTEL CORPORATION , WALLACE, Charles H. , PATEL, Reken , PARK, Hyunsoo , HARAN, Mohit K. , BASU, Debashish , WARD, Curtis W. , BRAIN, Ruth A.
发明人： WALLACE, Charles H. , PATEL, Reken , PARK, Hyunsoo , HARAN, Mohit K. , BASU, Debashish , WARD, Curtis W. , BRAIN, Ruth A.
IPC分类号： H01L21/768
摘要： Conductive via and metal line end fabrication is described. In an example, an interconnect structure includes a first inter-layer dielectric (ILD) on a hardmask layer, where the ILD includes a first ILD opening and a second ILD opening. The interconnect structure further includes an etch stop layer (ESL) on the ILD layer, where the ESL includes a first ESL opening aligned with the first ILD opening to form a first via opening, and where the ESL layer includes a second ESL opening aligned with the second ILD opening. The interconnect structure further includes a first via in the first via opening, a second ILD layer on the first ESL, and a metal line in the second ILD layer, where the metal line is in contact with the first via, and where the metal line includes a first metal opening, and where the metal line includes a second metal opening aligned with the second ILD opening and the ESL opening to form a second via opening. The interconnect structure further includes a metal line end in the first metal opening and further includes a second via in the metal line, where the second via is in the second via opening.

2. 发明申请

WO2018063330A1 PLUG & TRENCH ARCHITECTURES FOR INTEGRATED CIRCUITS & METHODS OF MANUFACTURE 审中-公开
标题翻译：用于集成电路的插头和插槽结构及制造方法
公开(公告)号：WO2018063330A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054799
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： WALLACE, Charles H. , PAIK, Marvin Y. , PARK, Hyunsoo , HARAN, Mohit K. , KAPLAN, Alexander F. , BRAIN, Ruth A.
IPC分类号： H01L21/768
CPC分类号： H01L21/76816 , H01L21/31144 , H01L21/76808 , H01L21/76897 , H01L23/5226 , H01L23/528
摘要： Methods and architectures for IC interconnect trenches, and trench plugs that define separations between two adjacent trench ends. Plugs and trenches may be defined through a multiple patterning process. An upper grating pattern may be summed with a plug keep pattern into a pattern accumulation layer. The pattern accumulation layer may be employed to define plug masks. A lower grating pattern may then be summed with the plug masks to define a pattern in trench ILD material, which can then be backfilled with interconnect metallization. As such, a complex damascene interconnect structure can be fabricated at the scaled-down geometries achievable with pitch-splitting techniques. In some embodiments, the trenches are located at spaces between first spacer masks defined in a patterning process associated with the first grating pattern while the plug masks are located based on a tone-inversion of second spacer masks associated with the second grating pattern.
摘要翻译： IC互连沟槽的方法和体系结构以及限定两个相邻沟槽端部之间分隔的沟槽插塞。插头和沟槽可以通过多重构图过程来定义。上光栅图案可以与插塞保持图案相加成图案堆积层。图案积累层可以用来定义插塞掩模。然后可以将下光栅图案与插塞掩模相加以在沟槽ILD材料中限定图案，然后可以用互连金属化来回填。这样，复杂的镶嵌互连结构可以用分节技术实现的按比例缩小的几何形状来制造。在一些实施例中，沟槽在与第一光栅图案相关的图案化工艺限定的第一间隔物掩模之间的空间位于当插头掩模基于与所述第二栅格图案相关联的第二间隔物掩模的音调反转位于

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式