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1. 发明申请

WO0223355A8 BUFFER TO MULTIPLE MEMORY INTERFACE 审中-公开
标题翻译：缓冲到多个存储器接口
公开(公告)号：WO0223355A8
公开(公告)日：2003-02-13
申请号：PCT/US0129378
申请日：2001-09-18
申请人： INTEL CORP , BONELLA RANDY M , HALBERT JOHN , WILLIAMS MICHAEL , LAM CHUNG , DODD JAMES
发明人： BONELLA RANDY M , HALBERT JOHN , WILLIAMS MICHAEL , LAM CHUNG , DODD JAMES
IPC分类号： G06F13/16 , G11C5/00 , G06F13/42
CPC分类号： G06F13/16 , Y02D10/14
摘要： Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least on e buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The at least one buffer allows the memory interface to be split into first and second subinterfaces. The first sub-interface is between the chipset and the buffer. The second sub-interface is between the buffer and the memory modules. The method also includes interleaving output of the memory ranks in the memory modules, and configuring the at least one buffer to properly latch data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.
摘要翻译：公开了在芯片组和存储器数据之间提供电隔离。本公开包括在芯片组和存储器模块之间的存储器接口中提供至少一个缓冲器。每个存储器模块包括多个存储器等级。至少一个缓冲器允许将存储器接口分割成第一和第二子接口。第一个子接口位于芯片组和缓冲区之间。第二个子接口位于缓冲区和内存模块之间。该方法还包括交织存储器模块中的存储器级别的输出，以及配置至少一个缓冲器以适当地锁存正在芯片组和存储器模块之间传输的数据。第一子接口和第二子接口彼此独立地操作，但是彼此同步。

2. 发明申请

WO0223355A3 BUFFER TO MULTIPLE MEMORY INTERFACE 审中-公开
标题翻译：缓冲到多个存储器接口
公开(公告)号：WO0223355A3
公开(公告)日：2002-08-22
申请号：PCT/US0129378
申请日：2001-09-18
申请人： INTEL CORP , BONELLA RANDY M , HALBERT JOHN , WILLIAMS MICHAEL , LAM CHUNG , DODD JAMES
发明人： BONELLA RANDY M , HALBERT JOHN , WILLIAMS MICHAEL , LAM CHUNG , DODD JAMES
IPC分类号： G06F13/16 , G11C5/00 , G06F13/42
CPC分类号： G06F13/16 , Y02D10/14
摘要： Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least on e buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The at least one buffer allows the memory interface to be split into first and second subinterfaces. The first sub-interface is between the chipset and the buffer. The second sub-interface is between the buffer and the memory modules. The method also includes interleaving output of the memory ranks in the memory modules, and configuring the at least one buffer to properly latch data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.
摘要翻译：公开了在芯片组和存储器数据之间提供电隔离。本公开包括在芯片组和存储器模块之间的存储器接口中提供至少一个缓冲器。每个存储器模块包括多个存储器等级。至少一个缓冲器允许将存储器接口分割成第一和第二子接口。第一个子接口位于芯片组和缓冲区之间。第二个子接口位于缓冲区和内存模块之间。该方法还包括交织存储器模块中的存储器级别的输出，以及配置至少一个缓冲器以适当地锁存正在芯片组和存储器模块之间传输的数据。第一子接口和第二子接口彼此独立地操作，但是彼此同步。

3. 发明申请

WO0223352A3 SYSTEM AND METHOD FOR PROVIDING RELIABLE TRANSMISSION IN A BUFFERED MEMORY SYSTEM 审中-公开
标题翻译：用于在缓冲存储器系统中提供可靠传输的系统和方法
公开(公告)号：WO0223352A3
公开(公告)日：2002-08-15
申请号：PCT/US0128930
申请日：2001-09-14
申请人： INTEL CORP , HALBERT JOHN , WILLIAMS MICHAEL , BONELLA RANDY , DODD JAMES
发明人： HALBERT JOHN , WILLIAMS MICHAEL , BONELLA RANDY , DODD JAMES
IPC分类号： G06F13/42 , G11C5/00 , G11C7/22
CPC分类号： G06F13/4239
摘要： The present invention provides a system and method for providing reliable transmission in a buffered memory system. The system includes memory devices memory controller, data buffers, an address/command buffer, and a clock circuit. The memory controller sends data, address information, status information and command information, to the memory devices and receives data from the memory devices. The buffers interconnect the memory devices and the memory controller. The clock circuit is embedded in the addr/cmd buffer. The clock circuit takes and input clock and outputs an output clock to the data buffers and/or the memory devices to control clock-shew to the data buffers and/or the memory devices.
摘要翻译：本发明提供了一种用于在缓冲存储器系统中提供可靠传输的系统和方法。该系统包括存储器件存储器控制器，数据缓冲器，地址/命令缓冲器和时钟电路。存储器控制器向存储器件发送数据，地址信息，状态信息和命令信息，并从存储器件接收数据。缓冲器互连存储器件和存储器控制器。时钟电路嵌入在addr / cmd缓冲区中。时钟电路接收并输入时钟，并将输出时钟输出到数据缓冲器和/或存储器件，以控制数据缓冲器和/或存储器件的时钟频率。

4. 发明申请

WO2005050599A3 BUFFERED MEMORY MODULE WITH IMPLICIT TO EXPLICIT MEMORY COMMAND EXPANSION 审中-公开
标题翻译：缓冲存储器模块，不明显的存储器命令扩展
公开(公告)号：WO2005050599A3
公开(公告)日：2006-04-20
申请号：PCT/US2004036964
申请日：2004-11-05
申请人： INTEL CORP , HALBERT JOHN , FREEMAN CHRIS , WILLIAMS MICHAEL , BAINS KILJIT , ELLIS ROBERT , VOGT PETE
发明人： HALBERT JOHN , FREEMAN CHRIS , WILLIAMS MICHAEL , BAINS KILJIT , ELLIS ROBERT , VOGT PETE
IPC分类号： G06F13/16
CPC分类号： G06F13/16
摘要： Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a buffer that receives memory commands and data, and then presents those commands and data to physical memory devices through a separate interface. The buffer has the capability to accept an implicit memory command, i.e., a command that does not contain a fully-formed memory device command, but instead instructs the memory module buffer to form one or more fully-formed memory device commands to perform memory operations. Substantial memory channel bandwidth can be saved, for instance, with a command that instructs a memory module to clear a region of memory or copy a region to a second area in memory. Other embodiments are described and claimed.
摘要翻译：在实施例中包括用于缓冲存储器模块的方法和装置。在示例性系统中，存储器模块具有接收存储器命令和数据的缓冲器，然后通过单独的接口将这些命令和数据呈现给物理存储器设备。缓冲器具有接受隐含存储器命令的功能，即，不包含完全形成的存储器件命令的命令，而是指示存储器模块缓冲器形成一个或多个完全形成的存储器件命令以执行存储器操作。例如，可以通过指令存储器模块清除存储器区域或将区域复制到存储器中的第二区域的命令来保存实质存储器通道带宽。描述和要求保护其他实施例。

5. 发明申请

WO2005066965A3 INTEGRAL MEMORY BUFFER AND SERIAL PRESENCE DETECT CAPABILITY FOR FULLY-BUFFERED MEMORY MODULES 审中-公开
标题翻译：完全缓冲存储器模块的完整存储缓冲器和串行存在检测能力
公开(公告)号：WO2005066965A3
公开(公告)日：2005-11-17
申请号：PCT/US2004041901
申请日：2004-12-13
申请人： INTEL CORP , HALBERT JOHN , FREEMAN CHRIS , WILLIAMS MICHAEL , BAINS KULJIT , ELLIS ROBERT
发明人： HALBERT JOHN , FREEMAN CHRIS , WILLIAMS MICHAEL , BAINS KULJIT , ELLIS ROBERT
IPC分类号： G11C5/00 , G11C7/10 , G11C7/20
CPC分类号： G11C7/1051 , G06F13/1673 , G06F13/1684 , G11C7/1078 , G11C7/20
摘要： Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, a serial presence detect function is included within a memory module buffer instead of being provided by a separate EEPROM device mounted on the memory module. Various embodiments thus can provide cost savings, chip placement and signal routing simplification, and can in some circumstances save pins on the module. Other embodiments are described and claimed.
摘要翻译：用于缓冲存储器模块的方法和装置包括在这些实施例中。在示例性系统中，串行存在检测功能被包括在存储器模块缓冲器内，而不是由安装在存储器模块上的单独的EEPROM设备提供。因此各种实施例可以提供成本节省，芯片布置和信号路由简化，并且在一些情况下可以将模块上的引脚节省。描述并要求保护其他实施例。

6. 发明申请

WO0173540A3 METHOD AND APPARATUS FOR TIMING-DEPENDENT TRANSFERS USING FIFOs 审中-公开
标题翻译：使用FIFO进行定时相关传输的方法和装置
公开(公告)号：WO0173540A3
公开(公告)日：2002-03-07
申请号：PCT/US0107219
申请日：2001-03-06
申请人： INTEL CORP , VOLK ANDREW M , WILLIAMS MICHAEL , MCDONNELL DAVID J
发明人： VOLK ANDREW M , WILLIAMS MICHAEL , MCDONNELL DAVID J
IPC分类号： G11C7/10
CPC分类号： G11C7/10
摘要： A method and apparatus for communicating commands and/or data between two different time domains. In one embodiment, multiple memory commands are placed into one or more FIFOs in a manner that specifies the delays that must take place between execution of the different commands. Along with the commands, delay information is placed into the FIFOs, specifying the number of clock cycles, or other form of time delay, that must elapse between execution of a command and execution of a subsequent command. This delay information is used to delay the execution of the subsequent command for the specified time period, while minimizing or eliminating any excess delays. Cue information can also be placed into the FIFOs with the commands to specify which commands must wait for other commands before beginning execution. The delay and cue information is determined and created in the time domain that initiates the transfers. The delays and cueing are executed in the other time domain. Although the different commands may be delivered through different FIFOs and can therefore have unpredictable arrival times with respect to each other, the delay and cueing information maintains the proper executing order and timing between the commands. Interactive control logic at the output of each FIFO uses the timing data to maintain execution in the proper order and with the proper inter-command delays.
摘要翻译：一种用于在两个不同时域之间传送命令和/或数据的方法和装置。在一个实施例中，多个存储器命令以指定在不同命令的执行之间必须发生的延迟的方式被放置到一个或多个FIFO中。与命令一起，将延迟信息放入FIFO中，指定执行命令和执行后续命令之间必须经过的时钟周期数量或其他形式的时间延迟。该延迟信息用于在指定的时间段内延迟后续命令的执行，同时最小化或消除任何多余的延迟。提示信息也可以放在FIFO中，其命令用于指定哪些命令在开始执行之前必须等待其他命令。在启动传输的时域中确定和创建延迟和提示信息。延迟和提示在其他时间域执行。虽然不同的命令可以通过不同的FIFO传递，并且因此可以相对于彼此具有不可预测的到达时间，但是延迟和提示信息保持命令之间的正确的执行顺序和定时。每个FIFO的输出端的交互控制逻辑使用定时数据来维持正确顺序的执行和适当的指令间延迟。

7. 发明申请

WO2005120465A3 MULTI-LAYER TABLET COMPRISING NON-STEROIDAL ANTI-INFLAMMATORY DRUGS DECONGESTANTS AND NON-SEDATING ANTIHISTAMINES 审中-公开
标题翻译：包含非消毒性抗炎药物分解物和非消化抗生素的多层板
公开(公告)号：WO2005120465A3
公开(公告)日：2007-06-28
申请号：PCT/US2005019200
申请日：2005-06-01
申请人： WYETH CORP , BERLIN ROGER , RAMSEY PETER , USAYAPANT ARUNYA , FUBARA JOSEPHINE , POXON SCOTT , BUBNIS WILLIAM , GIAMALVA DAVID , STRODE JOHN , BACHERT JOHN , WILLIAMS MICHAEL
发明人： BERLIN ROGER , RAMSEY PETER , USAYAPANT ARUNYA , FUBARA JOSEPHINE , POXON SCOTT , BUBNIS WILLIAM , GIAMALVA DAVID , STRODE JOHN , BACHERT JOHN , WILLIAMS MICHAEL
IPC分类号： A61K9/20 , A61K9/22 , A61K9/24 , A61K9/28 , A61K31/137 , A61K31/192 , A61K31/495 , A61K31/55
CPC分类号： A61K31/55 , A61K9/209 , A61K31/192 , A61K31/495
摘要： The present invention is directed to a pharmaceutical composition and method for treatment of rhinitis and cold like symptoms, the composition includes a non-steroidal anti-inflammatory drug (NSAID), a decongestant and an antihistamine preferably in a multi-layer tablet comprising an immediate release layer and an extended release layer to optimize the delivery profile and match the duration of biological action of the multiple active agents.
摘要翻译：本发明涉及用于治疗鼻炎和感冒症状的药物组合物和方法，该组合物包括非甾体抗炎药（NSAID），减充血剂和抗组胺剂，优选在多层片剂中，其包含立即释放层和延长释放层以优化递送分布并匹配多种活性剂的生物作用的持续时间。

8. 发明申请

WO03026267A2 TELECOMMUNICATIONS 审中-公开
标题翻译：电信
公开(公告)号：WO03026267A2
公开(公告)日：2003-03-27
申请号：PCT/GB0204262
申请日：2002-09-19
申请人： ORANGE PERSONAL COMM SERV LTD , WILLIAMS MICHAEL , SHAW CHRISTOPHER
发明人： WILLIAMS MICHAEL , SHAW CHRISTOPHER
IPC分类号： G06Q30/00 , G06Q20/00 , H04M15/00
CPC分类号： H04M15/44 , H04M15/00 , H04M15/43 , H04M15/80 , H04M2215/0104 , H04M2215/0152
摘要： A computer-implemented method of determining rating data for use in rating a service requested to be provided to a subscriber of a telecommunications system, the method comprising the steps of: storing individual subscriber records relating respectively to individual subscribers of a telecommunications systems. storing, in a subscriber record relating to a subscriber, information for use in determining rating data for use in rating a service requested to be provided to the subscriber, the information identifying one or more parameters of a service; receiving a request to provide a service to the subscriber, and determining rating data for use in rating the requested service in dependence on the information if one or more parameters of the service requested match the service parameters identified in the information.
摘要翻译：一种计算机实现的方法，用于确定用于对要求提供给电信系统的用户的服务进行评级的等级数据，所述方法包括以下步骤：存储分别涉及电信系统的各个用户的各个用户记录。在与订户相关的用户记录中存储用于确定用于对请求提供给订户的服务进行评级的等级数据的信息，所述信息标识服务的一个或多个参数; 接收向所述用户提供服务的请求，以及如果所请求的服务的一个或多个参数与所述信息中标识的服务参数匹配，则根据所述信息确定用于评估所请求服务的等级数据。

9. 发明申请

WO2012037527A3 APPARATUS AND METHOD FOR THE AUTOMATED MEASUREMENT OF SURAL NERVE CONDUCTION VELOCITY AND AMPLITUDE 审中-公开
标题翻译：自动测量神经传导速度和振幅的装置和方法
公开(公告)号：WO2012037527A3
公开(公告)日：2012-05-10
申请号：PCT/US2011052042
申请日：2011-09-16
申请人： NEUROMETRIX INC , BOETTCHER BONNIEJEAN , CRYAN MARC , GOZANI SHAI N , HERB GLENN , KONG XUAN , WILLIAMS MICHAEL , FENDROCK CHARLES
发明人： BOETTCHER BONNIEJEAN , CRYAN MARC , GOZANI SHAI N , HERB GLENN , KONG XUAN , WILLIAMS MICHAEL , FENDROCK CHARLES
IPC分类号： A61B5/053
CPC分类号： A61B5/04001 , A61B5/01 , A61B5/05 , A61B5/4041 , A61B2560/0266 , A61B2560/028 , A61B2560/0425 , A61B2560/0468 , A61B2562/0209 , A61B2562/046
摘要： Apparatus for measuring sural nerve conduction velocity and amplitude, the apparatus comprising: a housing; stimulation means mounted to the housing for electrically stimulating a human sural nerve; a biosensor releasably mounted to the housing, the biosensor comprising a plurality of electrodes for detecting a sural nerve response; acquisition means mounted to the housing and electrically connected to the biosensor for electrically acquiring the sural nerve response; processing means mounted to the housing and electrically connected to the acquisition means for digitizing, processing and storing the sural nerve response; calculation means mounted to the housing and electrically connected to the processing means for calculating the conduction velocity and amplitude of the sural nerve response; and display means mounted to the housing for displaying the sural nerve conduction velocity and amplitude; wherein the stimulation means and the biosensor are to be placed on a patient's anatomy by manipulating the housing.
摘要翻译：用于测量腓肠神经传导速度和振幅的装置，该装置包括：壳体; 刺激装置安装到壳体上以电刺激人的腓肠神经; 生物传感器，其可释放地安装到所述壳体，所述生物传感器包括用于检测腓肠神经反应的多个电极; 获取装置，其安装到所述壳体并电连接到所述生物传感器，用于电采集所述腓肠神经反应; 处理装置，其安装到壳体并电连接到采集装置，用于数字化，处理和存储腓肠神经反应; 计算装置，安装到壳体并电连接到处理装置，用于计算腓肠神经反应的传导速度和振幅; 以及显示装置，安装到所述壳体以显示所述腓肠神经传导速度和振幅; 其中所述刺激装置和所述生物传感器通过操纵所述外壳而被放置在患者的解剖结构上。

10. 发明申请

WO2011057210A2 METHODS AND SYSTEMS FOR REMOVAL OF IMPLANTABLE INTRAVASCULAR DEVICES 审中-公开
标题翻译：用于移除可植入的血管内装置的方法和系统
公开(公告)号：WO2011057210A2
公开(公告)日：2011-05-12
申请号：PCT/US2010055863
申请日：2010-11-08
申请人： INNERPULSE , FIFER DANIEL , GLENN RICHARD , SMITH JEFFREY , ORTH GEOFF , WILLIAMS MICHAEL , SANDERS WILLIAM M D , BARDSLEY EARL , GRACZYK WENDY
发明人： FIFER DANIEL , GLENN RICHARD , SMITH JEFFREY , ORTH GEOFF , WILLIAMS MICHAEL , SANDERS WILLIAM M D , BARDSLEY EARL , GRACZYK WENDY
IPC分类号： A61B17/3205 , A61B17/22 , A61B17/32 , A61N1/36 , A61N1/372
CPC分类号： A61B17/320016 , A61B17/29 , A61B2017/00358 , A61B2017/32006 , A61N1/37205 , A61N2001/0578
摘要： Improved methods, systems and apparatuses for extracting devices implanted within the vasculature of a patient are provided, including a method of extracting an intravascular device anchored in a vasculature of a patient, the device including a device body and a lead coupled to the device body, the lead having a distal end including an electrode, the distal end being fixed in a heart of the patient, the method comprising forming an incision in the vasculature, disconnecting the lead from the device body, removing the distal end of the lead from the heart, withdrawing the lead from the patient, disconnecting the device body from an anchor, and withdrawing the device body from the patient via the incision.
摘要翻译：提供了用于提取植入患者的脉管系统内的装置的改进的方法，系统和设备，包括提取锚定在患者的脉管系统中的血管内装置的方法，所述装置包括装置主体和联接到装置主体的引线，所述引线具有包括电极的远端，所述远端固定在患者的心脏中，所述方法包括在所述脉管系统中形成切口，将所述引线从所述装置主体断开，从所述心脏移除所述引线的所述远端，从患者身上抽出导线，将装置主体与锚定件分离，并且经由切口从患者身上抽出装置主体。

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