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1. 发明申请

WO0223352A3 SYSTEM AND METHOD FOR PROVIDING RELIABLE TRANSMISSION IN A BUFFERED MEMORY SYSTEM 审中-公开
标题翻译：用于在缓冲存储器系统中提供可靠传输的系统和方法
公开(公告)号：WO0223352A3
公开(公告)日：2002-08-15
申请号：PCT/US0128930
申请日：2001-09-14
申请人： INTEL CORP , HALBERT JOHN , WILLIAMS MICHAEL , BONELLA RANDY , DODD JAMES
发明人： HALBERT JOHN , WILLIAMS MICHAEL , BONELLA RANDY , DODD JAMES
IPC分类号： G06F13/42 , G11C5/00 , G11C7/22
CPC分类号： G06F13/4239
摘要： The present invention provides a system and method for providing reliable transmission in a buffered memory system. The system includes memory devices memory controller, data buffers, an address/command buffer, and a clock circuit. The memory controller sends data, address information, status information and command information, to the memory devices and receives data from the memory devices. The buffers interconnect the memory devices and the memory controller. The clock circuit is embedded in the addr/cmd buffer. The clock circuit takes and input clock and outputs an output clock to the data buffers and/or the memory devices to control clock-shew to the data buffers and/or the memory devices.
摘要翻译：本发明提供了一种用于在缓冲存储器系统中提供可靠传输的系统和方法。该系统包括存储器件存储器控制器，数据缓冲器，地址/命令缓冲器和时钟电路。存储器控制器向存储器件发送数据，地址信息，状态信息和命令信息，并从存储器件接收数据。缓冲器互连存储器件和存储器控制器。时钟电路嵌入在addr / cmd缓冲区中。时钟电路接收并输入时钟，并将输出时钟输出到数据缓冲器和/或存储器件，以控制数据缓冲器和/或存储器件的时钟频率。

2. 发明申请

WO0223355A8 BUFFER TO MULTIPLE MEMORY INTERFACE 审中-公开
标题翻译：缓冲到多个存储器接口
公开(公告)号：WO0223355A8
公开(公告)日：2003-02-13
申请号：PCT/US0129378
申请日：2001-09-18
申请人： INTEL CORP , BONELLA RANDY M , HALBERT JOHN , WILLIAMS MICHAEL , LAM CHUNG , DODD JAMES
发明人： BONELLA RANDY M , HALBERT JOHN , WILLIAMS MICHAEL , LAM CHUNG , DODD JAMES
IPC分类号： G06F13/16 , G11C5/00 , G06F13/42
CPC分类号： G06F13/16 , Y02D10/14
摘要： Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least on e buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The at least one buffer allows the memory interface to be split into first and second subinterfaces. The first sub-interface is between the chipset and the buffer. The second sub-interface is between the buffer and the memory modules. The method also includes interleaving output of the memory ranks in the memory modules, and configuring the at least one buffer to properly latch data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.
摘要翻译：公开了在芯片组和存储器数据之间提供电隔离。本公开包括在芯片组和存储器模块之间的存储器接口中提供至少一个缓冲器。每个存储器模块包括多个存储器等级。至少一个缓冲器允许将存储器接口分割成第一和第二子接口。第一个子接口位于芯片组和缓冲区之间。第二个子接口位于缓冲区和内存模块之间。该方法还包括交织存储器模块中的存储器级别的输出，以及配置至少一个缓冲器以适当地锁存正在芯片组和存储器模块之间传输的数据。第一子接口和第二子接口彼此独立地操作，但是彼此同步。

3. 发明申请

WO0223355A3 BUFFER TO MULTIPLE MEMORY INTERFACE 审中-公开
标题翻译：缓冲到多个存储器接口
公开(公告)号：WO0223355A3
公开(公告)日：2002-08-22
申请号：PCT/US0129378
申请日：2001-09-18
申请人： INTEL CORP , BONELLA RANDY M , HALBERT JOHN , WILLIAMS MICHAEL , LAM CHUNG , DODD JAMES
发明人： BONELLA RANDY M , HALBERT JOHN , WILLIAMS MICHAEL , LAM CHUNG , DODD JAMES
IPC分类号： G06F13/16 , G11C5/00 , G06F13/42
CPC分类号： G06F13/16 , Y02D10/14
摘要： Providing electrical isolation between the chipset and the memory data is disclosed. The disclosure includes providing at least on e buffer in a memory interface between a chipset and memory modules. Each memory module includes a plurality of memory ranks. The at least one buffer allows the memory interface to be split into first and second subinterfaces. The first sub-interface is between the chipset and the buffer. The second sub-interface is between the buffer and the memory modules. The method also includes interleaving output of the memory ranks in the memory modules, and configuring the at least one buffer to properly latch data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.
摘要翻译：公开了在芯片组和存储器数据之间提供电隔离。本公开包括在芯片组和存储器模块之间的存储器接口中提供至少一个缓冲器。每个存储器模块包括多个存储器等级。至少一个缓冲器允许将存储器接口分割成第一和第二子接口。第一个子接口位于芯片组和缓冲区之间。第二个子接口位于缓冲区和内存模块之间。该方法还包括交织存储器模块中的存储器级别的输出，以及配置至少一个缓冲器以适当地锁存正在芯片组和存储器模块之间传输的数据。第一子接口和第二子接口彼此独立地操作，但是彼此同步。

4. 发明申请

WO0223353A3 APPARATUS FOR IMPLEMENTING A BUFFERED DAISY-CHAIN RING CONNECTION BETWEEN A MEMORY CONTROLLER AND MEMORY MODULES 审中-公开
标题翻译：用于在存储器控制器和存储器模块之间实现缓冲的数据链连接的装置
公开(公告)号：WO0223353A3
公开(公告)日：2003-07-31
申请号：PCT/US0129236
申请日：2001-09-18
申请人： INTEL CORP , HALBERT JOHN , BONELLA RANDY , LAM CHUNG , DODD JAMES
发明人： HALBERT JOHN , BONELLA RANDY , LAM CHUNG , DODD JAMES
IPC分类号： G06F13/16 , G06F13/42 , G11C5/00
CPC分类号： G06F13/1684 , G06F13/4256 , Y02D10/14 , Y02D10/151
摘要： A plurality of memory modules interface through a daisy-chain providing a point-to-point connection for each memory module. The first and last memory module in the daisy chain each connect to a separate memory controller port forming a ring circuit. A distinct set of signals connect the memory modules in each direction. A junction circuit in each memory module provides line isolation, a coupling to the adjoining memory modules in the daisy chain, or in the case of the first and last memory module in the daisy chain, a memory module and a memory controller, and a data synchronization circuit. Each junction circuit provides as well as voltage conversion so that the memory devices on a memory module operate at a different voltage than the memory controller, and multiplexing/de-mulitplexing so that a lesser number of lines interfaces with each junction circuit.
摘要翻译：多个存储器模块通过菊花链接口，为每个存储器模块提供点对点连接。菊花链中的第一个和最后一个存储器模块都连接到形成环形电路的单独的存储器控制器端口。一组独特的信号在每个方向连接存储器模块。每个存储器模块中的结电路提供线路隔离，耦合到菊花链中的相邻存储器模块，或者在菊花链中的第一和最后存储器模块的情况下，存储器模块和存储器控制器以及数据同步电路每个结电路提供以及电压转换，使得存储器模块上的存储器件在与存储器控制器不同的电压下工作，并且复用/解复用，使得较少数量的线路与每个结电路接口。

5. 发明申请

WO0223550A3 APPARATUS FOR IMPLEMENTING A BUFFERED DAISY-CHAIN CONNECTION BETWEEN A MEMORY CONTROLLER AND MEMORY MODULES 审中-公开
标题翻译：用于实现存储器控制器和存储器模块之间缓冲的数据链连接的装置
公开(公告)号：WO0223550A3
公开(公告)日：2003-07-10
申请号：PCT/US0129383
申请日：2001-09-18
申请人： INTEL CORP , HALBERT JOHN , BONELLA RANDY , LAM CHUNG , DODD JAMES
发明人： HALBERT JOHN , BONELLA RANDY , LAM CHUNG , DODD JAMES
IPC分类号： G06F13/16 , G06F12/00 , G06F13/40 , G06F13/42 , G11C5/02 , G11C5/14 , G11C8/12 , G11C5/00
CPC分类号： G11C8/12 , G06F13/409 , G06F13/4256 , G11C5/02 , G11C5/14 , Y02D10/14 , Y02D10/151
摘要： A plurality of memory modules interface through a daisy-chain providing a point-to-point connection for each memory module. The first and the last memory module in the daisy chain each connect to a separate memory controller port forming a ring circuit. A distinct set of signals connect the memory modules in each direction. A junction circuit in each memory module provides line isolation, a coupling to the adjoining memory modules in the daisy chain or in the case of the first and last memor module in the daisy chain, a memory module and a memory controller, and a data synchronization circuit. Each junction circuit provides as well as voltage conversion so that the memory devices on a memory module operate at a different voltage than the memory controller, and multiplexing/de-multiplexing so that a lesser number of lines interface with each junction circuit.
摘要翻译：多个存储器模块通过菊花链接口，为每个存储器模块提供点对点连接。菊花链中的第一个和最后一个存储器模块都连接到形成环形电路的单独的存储器控制器端口。一组独特的信号在每个方向连接存储器模块。每个存储器模块中的结电路提供线路隔离，耦合到菊链中的相邻存储器模块，或者在菊花链中的第一和最后一个存储器模块的情况下，存储器模块和存储器控制器以及数据同步电路。每个结电路提供以及电压转换，使得存储器模块上的存储器件以与存储器控制器不同的电压工作，以及多路复用/解复用，使得较少数量的线路与每个结电路接口。

6. 发明申请

WO2004010435A3 A SYSTEM, APPARATUS, AND METHOD FOR A FLEXIBLE DRAM ARCHITECTURE 审中-公开
标题翻译：一种用于灵活DRAM架构的系统，装置和方法
公开(公告)号：WO2004010435A3
公开(公告)日：2004-04-01
申请号：PCT/US0321133
申请日：2003-07-03
申请人： INTEL CORP
发明人： DODD JAMES , JOHNSON BRIAN
IPC分类号： G11C7/10 , G11C11/408 , G06F12/06
CPC分类号： G11C7/1045 , G11C11/408
摘要： An addressing scheme to allow for a flexible DRAM configuration.
摘要翻译：一种用于允许灵活DRAM配置的寻址方案。

7. 发明申请

WO2004107184A3 A METHOD AND APPARATUS TO IMPROVE MULTI-CPU SYSTEM PERFORMANCE FOR ACCESSES TO MEMORY 审中-公开
标题翻译：一种提高存储器访问的多CPU系统性能的方法和装置
公开(公告)号：WO2004107184A3
公开(公告)日：2005-01-27
申请号：PCT/US2004014807
申请日：2004-05-12
申请人： INTEL CORP
发明人： DODD JAMES , MILSTREY ROBERT
IPC分类号： G06F13/16
CPC分类号： G06F13/1631
摘要： A flowchart and circuit for tracking memory page accesses in a multi-processor computing system to optimize memory bandwidth utilization.
摘要翻译：一种用于跟踪多处理器计算系统中的存储器页面访问以优化存储器带宽利用率的流程图和电路。

8. 发明申请

WO03083665A2 OBTAINING DATA MASK MAPPING INFORMATION 审中-公开
标题翻译：获取数据掩码映射信息
公开(公告)号：WO03083665A2
公开(公告)日：2003-10-09
申请号：PCT/US0307915
申请日：2003-03-13
申请人： INTEL CORP
发明人： RIESENMAN ROBERT , DODD JAMES , WILLIAMS MICHAEL
IPC分类号： G06F12/04 , G06F12/06 , G06F13/16 , G06F12/00
CPC分类号： G06F13/1626 , G06F12/04
摘要： A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a location in memory. In still another embodiment, the data mask map is determined through an algorithm.
摘要翻译：数据掩模图可以以各种方式编程到存储设备中。在一个实施例中，将数据掩码硬连接到选择设备中以重新排序数据掩码位或数据块。在另一个实施例中，从存储器中的位置检索数据掩码图。在另一个实施例中，通过算法确定数据掩码图。

9. 发明申请

WO2004021194A2 PRECHARGE SUGGESTION 审中-公开
标题翻译：预先建议
公开(公告)号：WO2004021194A2
公开(公告)日：2004-03-11
申请号：PCT/US0326243
申请日：2003-08-22
申请人： INTEL CORP
发明人： DODD JAMES
IPC分类号： G06F12/02 , G06F12/06 , G06F12/08
CPC分类号： G06F12/0215
摘要： Machine-readable media, methods, and apparatus are described which process memory transactions. In some embodiments, a processor requests an external memory controller to close a storage location of a memory associated with a first memory transaction based upon a relationship between the first memory transaction and a second memory transaction.
摘要翻译：描述了处理存储器事务的机器可读介质，方法和装置。在一些实施例中，处理器基于第一存储器事务和第二存储器事务之间的关系，请求外部存储器控制器关闭与第一存储器事务相关联的存储器的存储位置。

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