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1. 发明申请

WO2012054041A1 METAL-INSULATOR TRANSITION SWITCHING DEVICES 审中-公开
标题翻译：金属绝缘子过渡开关器件
公开(公告)号：WO2012054041A1
公开(公告)日：2012-04-26
申请号：PCT/US2010/053549
申请日：2010-10-21
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , PICKETT, Matthew D. , KUEKES, Philip J. , WILLIAMS, R. Stanley , PERNER, Frederick , WU, Wei , BRATKOVSKI, Alexandre M.
发明人： PICKETT, Matthew D. , KUEKES, Philip J. , WILLIAMS, R. Stanley , PERNER, Frederick , WU, Wei , BRATKOVSKI, Alexandre M.
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L47/02 , H01L47/005 , H01L49/003
摘要： A metal-insulator transition switching device (100) includes a first electrode (120) and a second electrode (125). A channel region (115) which includes a bulk metal-insulator transition material separates the first electrode (120) and the second electrode (125). A method for forming a metal-insulator transition switching device (200) includes depositing a layer of bulk metal-insulator transition material (245) in between a first electrode (220) and a second electrode (225) to form a channel region (115) and forming a gate electrode (210) operatively connected to the channel region (115).
摘要翻译：金属 - 绝缘体转变开关装置（100）包括第一电极（120）和第二电极（125）。包括体金属 - 绝缘体转移材料的沟道区域（115）将第一电极（120）和第二电极（125）分开。一种用于形成金属 - 绝缘体转变开关器件（200）的方法包括在第一电极（220）和第二电极（225）之间沉积体金属 - 绝缘体转变材料层（245）以形成沟道区域（115））并且形成可操作地连接到沟道区（115）的栅电极（210）。

2. 发明申请

WO2012067660A1 METHOD AND CIRCUIT FOR SWITCHING A MEMRISTIVE DEVICE 审中-公开
标题翻译：用于切换物理装置的方法和电路
公开(公告)号：WO2012067660A1
公开(公告)日：2012-05-24
申请号：PCT/US2011/023250
申请日：2011-01-31
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , PERNER, Frederick , YI, Wei , PICKETT, Matthew, D.
发明人： PERNER, Frederick , YI, Wei , PICKETT, Matthew, D.
IPC分类号： H03K17/30 , H01L29/41 , G11C11/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0007 , G11C13/0064 , G11C2013/0066 , G11C2013/0073 , G11C2013/0078 , G11C2211/5624 , G11C2211/5645 , G11C2213/15
摘要： A method of switching a memristive device applies a current ramp of a selected polarity to the memristive device. The resistance of the device during the current ramp is monitored. When the resistance of the memristive device reaches the target value, the current ramp is removed.
摘要翻译：一种切换忆阻器件的方法将所选极性的电流斜坡应用于忆阻器件。监测电流斜坡期间器件的电阻。当忆阻器的电阻达到目标值时，电流斜坡被去除。

3. 发明申请

WO2011136795A1 CONNECTION AND ADDRESSING OF MULTI-PLANE CROSSPOINT DEVICES 审中-公开
标题翻译：多平面装置的连接和寻址
公开(公告)号：WO2011136795A1
公开(公告)日：2011-11-03
申请号：PCT/US2010/033141
申请日：2010-04-30
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , PERNER, Frederick
发明人： PERNER, Frederick
IPC分类号： H01L21/8239
CPC分类号： H01L27/101 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： A multi-plane circuit structure has at least a first circuit plane and a second circuit plane, and each circuit plane has a plurality of row wire segments, a plurality of column wire segments, and a plurality of crosspoint devices formed at intersections of the row wire segments and the column wire segments. The row and column wire segments have a segment length for forming a preselected number of crosspoint devices thereon. Each row wire segment in the second circuit plane is connected to a row wire segment in the first circuit plane with no offset in a row direction and in a column direction, and each column wire segment in the second circuit plane is connected to a column wire segment in the first circuit plane with an offset length in both the row direction and the column direction. The offset length corresponds to half of the preselected number of crosspoint devices.
摘要翻译：多平面电路结构至少具有第一电路平面和第二电路平面，并且每个电路平面具有多个行线段，多个列线段以及形成在该行的交叉处的多个交叉点设备线段和列线段。行和列线段具有用于在其上形成预选数量的交叉点设备的段长度。第二电路平面中的每行线段在第一电路平面中与行方向和列方向上没有偏移连接到行线段，并且第二电路平面中的每列线段连接到列线在行方向和列方向上具有偏移长度的第一电路平面中的段。偏移长度对应于预选数量的交叉点设备的一半。

4. 发明申请

WO2012134450A1 DUAL-PLANE MEMORY ARRAY 审中-公开
标题翻译：双平面内存阵列
公开(公告)号：WO2012134450A1
公开(公告)日：2012-10-04
申请号：PCT/US2011/030337
申请日：2011-03-29
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , PERNER, Frederick
发明人： PERNER, Frederick
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L45/12 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： A memory array has a plurality of conductor structures. Each conductor structure has a top wire segment extending in a first direction, a middle wire segment extending in a second direction at an angle from the first direction, a bottom wire segment extending in a direction opposite to the first direction, and a via connecting the top, middle, and bottom wire segments. A plurality of memory cells in an upper plane of the memory array are formed at intersections of the middle wire segment of each conductor structure with the top wire segments of neighboring conductor structures, and a plurality of memory cells in a lower plane are formed at intersections of the middle wire segment of each conductor structure with the bottom wire segments of neighboring conductor structures.
摘要翻译：存储器阵列具有多个导体结构。每个导体结构具有沿第一方向延伸的顶部线段，沿着与第一方向成一定角度的第二方向延伸的中间线段，沿与第一方向相反的方向延伸的底部线段，以及连接顶部，中间和底部线段。存储器阵列的上平面中的多个存储单元形成在每个导体结构的中间线段与相邻导体结构的顶部线段的交点处，并且下部平面中的多个存储单元形成在相交处每个导体结构的中间线段与相邻导体结构的底部线段。

5. 发明申请

WO2014018063A1 DYNAMIC SENSE CIRCUITRY 审中-公开
标题翻译：动态感测电路
公开(公告)号：WO2014018063A1
公开(公告)日：2014-01-30
申请号：PCT/US2012/048679
申请日：2012-07-27
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , PERNER, Frederick
发明人： PERNER, Frederick
IPC分类号： G11C7/06
CPC分类号： G11C13/004 , G11C7/062 , G11C7/067 , G11C7/106 , G11C27/02 , G11C2013/0042 , G11C2013/0054 , G11C2213/77 , H01L45/12
摘要： A dynamic sense circuit to determine memristor states within a memristor crossbar array that includes a differential comparator made up of a resistance capacitance (RC) network to capture a reference voltage and a differential pre-amp to operate in an open loop mode to dynamically compare the reference voltage to a sense voltage. An alternating current (AC) coupled amplifier receives the output of the comparator and outputs an amplified signal. A set-reset (SR) latch samples and holds the amplified signal as a digital value.
摘要翻译：一种动态感测电路，用于确定忆阻器交叉开关阵列内的忆阻器状态，其包括由电阻电容（RC）网络构成的差分比较器，以捕获参考电压和差分前置放大器以在开环模式下工作以动态地比较参考电压到感测电压。交流（AC）耦合放大器接收比较器的输出并输出放大的信号。置位（SR）锁存器将放大的信号采样并保存为数字值。

6. 发明申请

WO2012067667A1 CIRCUIT AND METHOD FOR READING A RESISTIVE SWITCHING DEVICE IN AN ARRAY 审中-公开
标题翻译：用于读取阵列中的电阻式切换装置的电路和方法
公开(公告)号：WO2012067667A1
公开(公告)日：2012-05-24
申请号：PCT/US2011/026496
申请日：2011-02-28
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , PERNER, Frederick
发明人： PERNER, Frederick
IPC分类号： G11C7/10 , G11C5/14
CPC分类号： G11C13/004 , G11C13/0007 , G11C27/02 , G11C27/024 , G11C2013/0054 , G11C2013/0057
摘要： A read circuit for sensing a resistive state of a resistive switching device in a crosspoint array has an equipotential preamplifier connected to a selected column line of the resistive switching device in the array to deliver a read current while maintaining the selected column line at a reference voltage near a biasing voltage applied to unselected row lines of the array. The read circuit includes a reference voltage generation component for generating the reference voltage for the equipotential preamplifier. The reference voltage generation component samples the biasing voltage via the selected column line and adds a small increment to a sampled biasing voltage to form the reference voltage.
摘要翻译：用于感测交叉点阵列中的电阻式开关装置的电阻状态的读取电路具有连接到阵列中的电阻式开关装置的选定列线的等电位前置放大器，以传送读取电流，同时将选定的列线保持在参考电压靠近施加到阵列的未选择行线的偏置电压。读取电路包括用于产生等电位前置放大器的参考电压的参考电压产生部件。参考电压产生组件通过所选列线对偏置电压进行采样，并将一个小增量加到采样的偏置电压上，以形成参考电压。

7. 发明申请

WO2013032424A1 CIRCUIT AND METHOD FOR READING A RESISTIVE SWITCHING DEVICE IN AN ARRAY 审中-公开
标题翻译：用于读取阵列中的电阻式切换装置的电路和方法
公开(公告)号：WO2013032424A1
公开(公告)日：2013-03-07
申请号：PCT/US2011/049337
申请日：2011-08-26
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , PERNER, Frederick
发明人： PERNER, Frederick
IPC分类号： G11C13/00 , G11C16/26 , G11C7/10 , G11C7/06
CPC分类号： G11C13/004 , G11C11/15 , G11C11/16 , G11C13/0007 , G11C2013/0054
摘要： A read circuit for sensing a resistance state of a resistive switching device in a crosspoint array utilizes a transimpedance equipotential preamplifier connected to a selected column line of the resistive switching device in the array. The equipotential preamplifier delivers a sense current while maintaining the selected column line at a reference voltage near a biasing voltage applied to unselected row lines of the array. A reference resistor is selectively connected to the equipotential preamplifier for setting a reference current, wherein the equipotential preamplifier is set to produce a preamplifier output voltage having a magnitude depending on whether the sense current is smaller or greater than the reference current. A voltage comparator is 10 connected to the equipotential preamplifier to compare the preamplifier output voltage with a setup reference voltage and generate a comparator output voltage indicative of the resistance state of the resistive switching device.
摘要翻译：用于感测交叉点阵列中的电阻式开关装置的电阻状态的读取电路利用连接到阵列中的电阻式开关装置的所选列线的跨阻抗等电位前置放大器。等电位前置放大器提供感测电流，同时将选定的列线保持在靠近施加到阵列的未选行行的偏置电压的参考电压。参考电阻器选择性地连接到等电位前置放大器以设置参考电流，其中等电位前置放大器被设置为产生具有取决于感测电流是小于还是大于参考电流的幅度的前置放大器输出电压。电压比较器10连接到等电位前置放大器，以将前置放大器输出电压与设置参考电压进行比较，并生成表示电阻开关器件的电阻状态的比较器输出电压。

8. 发明申请

WO2013015768A1 CIRCUIT AND METHOD FOR READING A RESISTIVE SWITCHING DEVICE IN AN ARRAY 审中-公开
标题翻译：用于读取阵列中的电阻式切换装置的电路和方法
公开(公告)号：WO2013015768A1
公开(公告)日：2013-01-31
申请号：PCT/US2011/044967
申请日：2011-07-22
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , PERNER, Frederick
发明人： PERNER, Frederick
IPC分类号： G11C7/10 , G11C7/06 , G11C13/00
CPC分类号： G11C13/0002 , G11C7/02 , G11C7/062 , G11C11/1673 , G11C13/0007 , G11C13/004 , G11C2013/0045 , G11C2013/0054 , G11C2213/77
摘要： A read circuit for sensing a resistance state of a resistive switching device in a crosspoint array utilizes an equipotential preamplifier connected to a selected column line of the resistive switching device in the array. The equipotential preamplifier delivers a sense current while maintaining the selected column line at a reference voltage near a biasing voltage 5 applied to unselected row lines of the array. The read circuit has a reference current source for generating a sense reference current, and a current comparator connected to evaluate the sense current delivered by the equipotential preamplifier against the sense reference current and generating an output signal indicative of the resistance state of the resistive switching device.
摘要翻译：用于感测交叉点阵列中的电阻式开关装置的电阻状态的读取电路利用连接到阵列中的电阻式开关装置的所选列线的等电位前置放大器。等电位前置放大器提供感测电流，同时将选定的列线保持在施加到阵列的未选行行的偏置电压5附近的参考电压。读取电路具有用于产生感测参考电流的参考电流源，以及连接的电流比较器，用于评估由等电位前置放大器相对于感测参考电流传递的感测电流，并产生指示电阻开关器件的电阻状态的输出信号。

9. 发明申请

WO2011112198A1 INTERCONNECTION ARCHITECTURE FOR MEMORY STRUCTURES 审中-公开
标题翻译：内存结构互连架构
公开(公告)号：WO2011112198A1
公开(公告)日：2011-09-15
申请号：PCT/US2010/027188
申请日：2010-03-12
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , PERNER, Frederick
发明人： PERNER, Frederick
IPC分类号： H01L21/8239 , H01L29/417
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/24
摘要： An interconnect architecture for connecting read/write circuitry (804) to a memory structure (200), the interconnect architecture includes a switching layer (222) comprising a number of access switches (310) arranged in at least one set of two offset switch blocks (312, 314), the access switches (310) being connected to a first set of parallel wire tracks (502) and a second set of parallel wire tracks (602) intersecting the first set of parallel wire tracks (502); and a routing layer (214) connecting the access switches (310) to a number of access vias (208, 210) of the memory structure (200); in which four wire tracks (502, 602) are used to select a programmable device (206) of the memory structure (200).
摘要翻译：一种用于将读/写电路（804）连接到存储器结构（200）的互连架构，所述互连架构包括切换层（222），其包括布置在至少一组两个偏移开关块中的多个访问开关（310）（312,314），所述接入开关（310）连接到与所述第一组平行线轨道（502）相交的第一组平行线轨道（502）和第二组平行线轨道（602）; 以及将所述接入交换机（310）连接到所述存储器结构（200）的多个接入通路（208,210）的路由层（214）; 其中四条电线轨道（502,602）用于选择存储器结构（200）的可编程设备（206）。

10. 发明申请

WO2015065443A1 THREE DIMENSIONAL RESISTIVE MEMORY ARCHITECTURES 审中-公开
标题翻译：三维电阻记忆体结构
公开(公告)号：WO2015065443A1
公开(公告)日：2015-05-07
申请号：PCT/US2013/067823
申请日：2013-10-31
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： PERNER, Frederick , RHO, Kwangmyoung , KIM, Jeong Hwan , HWANG, Sangmin , PARK, Jinwon , YI, Jae Yun , LEE, Jae Yeon , CHUNG, Sung Won
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： G11C13/0028 , G11C8/10 , G11C13/0002 , G11C13/0023 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C2213/71 , G11C2213/77 , H01L27/2436 , H01L27/2481 , H01L45/04
摘要： In one example, a three dimensional resistive memory architecture includes adjacent memory tiles with each tile including a multilevel resistive crossbar array and at least one decoder. The multilevel crossbar array includes layers of row crossbars, layers of column crossbars, and layers of resistive memory elements interposed between cross points of the row crossbars and the column crossbars, in which at least one layer of crossbars extends from a first tile through an adjacent tile and is used to address resistive memory elements in the adjacent tile, The at least one decoder underlies the multilevel resistive crossbar array and includes an address matrix comprising digital lines and analog lines, in which the digital lines select which crossbars are connected to the analog lines.
摘要翻译：在一个示例中，三维电阻存储器架构包括相邻的存储器片，每个片包括多电平电阻交叉列阵列和至少一个解码器。所述多级交叉开关阵列包括插入所述行十字条和所述列交叉条的交叉点之间的行交叉条，列交叉条层和电阻性存储器元件层，其中至少一层交叉条从第一瓦片延伸穿过相邻的并且用于寻址相邻瓦片中的电阻性存储器元件。至少一个解码器位于多电平电阻交叉开关阵列之下，并且包括包括数字线路和模拟线路的地址矩阵，其中数字线选择哪个交叉连接到模拟线。

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