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1. 发明申请

WO2017135967A1 DUAL IN-LINE MEMORY MODULE 审中-公开
标题翻译：双列直插存储模块
公开(公告)号：WO2017135967A1
公开(公告)日：2017-08-10
申请号：PCT/US2016/016782
申请日：2016-02-05
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： LESARTRE, Gregg B. , CULLER, Jason H. , FOLTIN, Martin , JAFFE, William S.
IPC分类号： G11C5/04 , G11C7/10
CPC分类号： G11C5/025 , G11C5/04 , G11C2207/105
摘要： According to an example, a dual in-line memory module (DIMM) may include a high density package substrate including a plurality of connectors for communicatively interconnecting the DIMM to a system, and a device including at least one of a first die including a plurality of wirebonds and associated wirebond pads to directly interface with the high density package substrate, and a second die including a plurality of connection pads to directly interface with the high density package substrate.
摘要翻译：根据一个示例，双列直插式存储器模块（DIMM）可以包括高密度封装基板，该高密度封装基板包括用于将DIMM通信地互连到系统的多个连接器，以及包括至少一个第一裸片和第二裸片中的一个，第一裸片包括多个引线键合和相关联的引线键合垫以直接与高密度封装基板接合，第二引线包括多个连接垫以直接与高密度封装基板接合。

2. 发明申请

WO2017074358A1 REFERENCE COLUMN SENSING FOR RESISTIVE MEMORY 审中-公开
标题翻译：电阻式存储器的参考列感应
公开(公告)号：WO2017074358A1
公开(公告)日：2017-05-04
申请号：PCT/US2015/057833
申请日：2015-10-28
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： IGNOWSKI, Jim , FOLTIN, Martin , JEON, Yoocham
IPC分类号： G11C13/00 , G11C7/06
CPC分类号： G11C7/062 , G11C7/02 , G11C13/0002 , G11C13/004 , G11C2013/0045 , G11C2013/0054 , G11C2207/063
摘要： A circuit includes a resistive memory cell in a memory array to store a memory state for the resistive memory cell. A reference cell in the memory array stores a reference memory state for the resistive memory cell. A function generator concurrently applies a read voltage to the resistive memory cell and the reference cell via a memory row address. A sensing circuit enables the function generator and monitors a target current received from the resistive memory cell when selected via a memory column address and monitors a reference current received when selected via a reference column address in response to the read voltage applied to the memory row address. A current comparator circuit in the sensing circuit compares a difference between the target current and the reference current to determine the memory state of the resistive memory cell.
摘要翻译：电路包括存储器阵列中的电阻式存储器单元以存储电阻式存储器单元的存储器状态。存储器阵列中的参考单元存储电阻式存储器单元的参考存储器状态。函数发生器通过存储器行地址同时将读取电压施加到电阻式存储器单元和参考单元。当经由存储器列地址选择时，感测电路启用函数发生器并监测从阻性存储器单元接收的目标电流，并响应于施加到存储器行地址的读取电压而监测当经由参考列地址选择时接收的参考电流。感测电路中的电流比较器电路比较目标电流和参考电流之间的差异以确定电阻式存储单元的存储状态。

3. 发明申请

WO2019212466A1 RESISTIVE AND DIGITAL PROCESSING CORES 审中-公开
公开(公告)号：WO2019212466A1
公开(公告)日：2019-11-07
申请号：PCT/US2018/030125
申请日：2018-04-30
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： STRACHAN, John Paul , MILOJICIC, Dejan S. , FOLTIN, Martin , CHALAMALASETTI, Sai Rahul , SHARMA, Amit S.
IPC分类号： G06F15/78 , G06F15/163
摘要： In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.

4. 发明申请

WO2017086925A1 ITERATIVE WRITE SEQUENCE INTERRUPT 审中-公开
标题翻译：迭代写序列中断
公开(公告)号：WO2017086925A1
公开(公告)日：2017-05-26
申请号：PCT/US2015/061009
申请日：2015-11-17
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： LESARTRE, Gregg B. , FOLTIN, Martin
IPC分类号： G06F13/16 , G06F13/24 , G06F12/00
CPC分类号： G06F13/1668 , G06F13/16 , G06F13/24
摘要： Example implementations relate to memory read requests. For example, an implementation may include tracking progress of an iterative write sequence to write data to a memory element of a memory module. A received read request is detected to be addressed to a memory bank that includes the memory element undergoing the iterative write sequence. Based on the tracked progress, a time is determined to interrupt the iterative write sequence with insertion of the read request. The time aligns between operations of the iterative write sequence and data is returned within a predetermined read latency.
摘要翻译：
示例实现涉及内存读取请求。例如，实现可以包括跟踪迭代写入序列的进展以将数据写入到存储器模块的存储器元件。检测到接收到的读取请求被寻址到包括正在经历迭代写入序列的存储器元件的存储体。基于追踪的进度，确定时间以插入读取请求来中断迭代写入序列。在预定的读取延迟内返回迭代写入序列和数据的操作之间的时间对准。

5. 发明申请

WO2016195637A1 MEMRISTANCE FEEDBACK TUNING 审中-公开
标题翻译：弹性反馈调谐
公开(公告)号：WO2016195637A1
公开(公告)日：2016-12-08
申请号：PCT/US2015/033297
申请日：2015-05-29
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： WHITAKER, Luke , MERCED GRAFALS, Emmanuelle J , FOLTIN, Martin
IPC分类号： G11C11/15
CPC分类号： G11C13/0064 , G11C11/56 , G11C13/0069 , G11C2013/005 , G11C2013/0073 , G11C2013/0076 , G11C2013/009 , G11C2013/0092
摘要： An example device in accordance with an aspect of the present disclosure includes at least one current comparator, a plurality of threshold currents, and a controller. The current comparator is to compare a memristor current to a plurality of threshold currents. The controller is to set a desired memristance state of a memristor according to a memristance feedback tuning loop based on a plurality of threshold levels. The controller is to apply positive and negative voltages to the memristor during the feedback tuning loop to achieve the desired memristance state of the memristor.
摘要翻译：根据本公开的一个方面的示例性装置包括至少一个电流比较器，多个阈值电流和控制器。电流比较器是将忆阻器电流与多个阈值电流进行比较。控制器将根据多个阈值电平根据忆阻反馈调谐环来设置忆阻器的期望的忆阻状态。控制器将在反馈调谐回路期间将正和负电压施加到忆阻器，以实现忆阻器所需的忆阻状态。

6. 发明申请

WO2019212488A1 ACCELERATION OF MODEL/WEIGHT PROGRAMMING IN MEMRISTOR CROSSBAR ARRAYS 审中-公开
公开(公告)号：WO2019212488A1
公开(公告)日：2019-11-07
申请号：PCT/US2018/030219
申请日：2018-04-30
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： CHALAMALASETTI, Sai Rahul , FARABOSCHI, Paolo , FOLTIN, Martin , GRAVES, Catherine , MILOJICIC, Dejan S. , STRACHAN, John Paul , SEREBRYAKOV, Sergey
IPC分类号： G11C13/00
摘要： A crossbar array includes a number of memory elements. An analog-to-digital converter (ADC) is electronically coupled to the vector output register. A digital-to-analog converter (DAC) is electronically coupled to the vector input register. A processor is electronically coupled to the ADC and to the DAC. The processor may be configured to determine whether division of input vector data by output vector data from the crossbar array is within a threshold value, and if not within the threshold value, determine changed data values as between the output vector data and the input vector data, and write the changed data values to the memory elements of the crossbar array.

7. 发明申请

WO2019212455A1 CONVOLUTIONAL NEURAL NETWORK 审中-公开
公开(公告)号：WO2019212455A1
公开(公告)日：2019-11-07
申请号：PCT/US2018/030086
申请日：2018-04-30
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： FOLTIN, Martin , STRACHAN, John Paul , SEREBRYAKOV, Sergey
IPC分类号： G06N3/04 , G06N3/08
摘要： A convolutional neural network system includes a first part of the convolutional neural network comprising an initial processor configured to process an input data set and store a weight factor set in the first part of the convolutional neural network; and a second part of the convolutional neural network comprising a main computing system configured to process an export data set provided from the first part of the convolutional neural network.

8. 发明申请

WO2019209330A1 VERTICAL JFET DEVICE FOR MEMRISTOR ARRAY INTERFACE 审中-公开
公开(公告)号：WO2019209330A1
公开(公告)日：2019-10-31
申请号：PCT/US2018/029902
申请日：2018-04-27
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： SHARMA, Amit S. , STRACHAN, John, Paul , FOLTIN, Martin
IPC分类号： H01L29/78 , H01L29/66 , H01L29/732
摘要： Devices and methods are provided. In one aspect, a device for driving a memristor array includes a substrate including a well having a bottom layer, a first wall and a second wall. The substrate is formed of a strained layer of a first semiconductor material. A vertical JFET is formed in the well. The vertical JFET includes a vertical gate region formed in a middle portion of the well with a gate region height less than a depth of the well. A channel region is formed of an epitaxial layer of a second semiconductor wrapped around the vertical gate region. Vertical source regions are formed on both sides of a first end of the vertical gate region, and vertical drain regions are formed on both sides of a second end of the vertical gate region.

9. 发明申请

WO2017023245A1 DATA SENSING IN CROSSPOINT MEMORY STRUCTURES 审中-公开
标题翻译： CROSSPOINT记忆结构中的数据传感
公开(公告)号：WO2017023245A1
公开(公告)日：2017-02-09
申请号：PCT/US2015/043107
申请日：2015-07-31
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： LESARTRE, Gregg B. , FOLTIN, Martin , JEON, Yoocharn
IPC分类号： G11C7/06 , G11C8/06
CPC分类号： G11C7/067 , G11C7/106 , G11C2207/063
摘要： The present disclosure provides a data storage device that includes a memory cell array and sense circuitry to detect a data value stored to a memory cell of the memory cell array. The data storage device also includes a controller to bias the sense circuitry during a read phase of a write operation to increase the probability that the sense circuitry will detect an opposite value that is opposite from the value being written to the memory cell.
摘要翻译：本公开提供了一种数据存储设备，其包括存储单元阵列和感测电路，用于检测存储到存储单元阵列的存储单元的数据值。数据存储设备还包括控制器，用于在写入操作的读取阶段期间偏置感测电路，以增加感测电路将检测与被写入存储器单元的值相反的相反值的概率。

10. 发明申请

WO2016122627A1 DETERMINING A CURRENT IN A MEMORY ELEMENT OF A CROSSBAR ARRAY 审中-公开
标题翻译：确定十字架阵列的记忆元素中的电流
公开(公告)号：WO2016122627A1
公开(公告)日：2016-08-04
申请号：PCT/US2015/013877
申请日：2015-01-30
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： MURALIMANOHAR, Naveen , BALASUBRAMONIAN, Rajeev , FOLTIN, Martin
IPC分类号： G11C13/00 , G11C5/06
CPC分类号： G11C13/003 , G11C13/0033 , G11C13/004 , G11C13/0069 , G11C29/50 , G11C2013/0054 , G11C2013/0057 , G11C2029/5006 , G11C2213/72 , G11C2213/76
摘要： A method of determining a current in a memory element of a crossbar array is described. In the method, a number of pre-access operations are initiated. Each pre-access operation includes discarding a previously stored sneak current, determining a new sneak current for the crossbar array, discarding a previously stored sneak current, and storing the new sneak current. In the method, in response to a received access command, an access voltage is applied to a target memory element of the crossbar array and an element current for the target memory element is determined based on an access current and a stored sneak current.
摘要翻译：描述了确定交叉开关阵列的存储元件中的电流的方法。在该方法中，启动了许多预访问操作。每个预访问操作包括丢弃先前存储的潜行电流，确定交叉开关阵列的新潜行电流，丢弃先前存储的潜行电流并存储新的潜行电流。在该方法中，响应于接收到的访问命令，将访问电压施加到交叉开关阵列的目标存储器元件，并且基于存取电流和存储的潜行电流来确定目标存储器元件的元件电流。

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