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1. 发明申请

WO2006027026A1 APPARATUS AND CONTROL INTERFACE THEREFOR 审中-公开
标题翻译：设备和控制接口
公开(公告)号：WO2006027026A1
公开(公告)日：2006-03-16
申请号：PCT/EP2004/052070
申请日：2004-09-07
申请人： FREESCALE SEMICONDUCTORS, INC , O'KEEFFE, Connor J , KELLEHER, Paul , SCHWARTZ, Daniel
发明人： O'KEEFFE, Connor J , KELLEHER, Paul , SCHWARTZ, Daniel
IPC分类号： G06F13/38
CPC分类号： G06F13/4291
摘要： An apparatus (100) comprises a number of sub-systems (110, 120) and a control interface (105) operably coupled to sub-systems (110, 120) for routeing data therebetween. A strobe generation function (225, 325) is operably coupled to the control interface (105) and configured to generate a plurality of different strobe signals to differentiate between different intended receiving devices. Thus, different strobe signals may be multiplexed onto a single control interface link, based on a pulse width or voltage magnitude characteristics of the respective strobe signals. A strobe decoder function is operably coupled to the control interface (105) and configured to decode a plurality of different strobe signals to differentiate between triggering sub-systems on receiving devices.
摘要翻译：装置（100）包括多个子系统（110,120）和可操作地耦合到子系统（110,120）的控制接口（105），用于在其间路由数据。选通生成功能（225,325）可操作地耦合到控制接口（105）并且被配置为生成多个不同的选通信号以区分不同的预期接收设备。因此，不同的选通信号可以基于各个选通信号的脉冲宽度或电压幅度特性而复用到单个控制接口链路上。选通解码器功能可操作地耦合到控制接口（105）并且被配置为解码多个不同的选通信号以区分接收设备上的触发子系统。

2. 发明申请

WO2006027025A1 WIRELESS COMMUNICATION DEVICE AND DATA INTERFACE 审中-公开
标题翻译：无线通信设备和数据接口
公开(公告)号：WO2006027025A1
公开(公告)日：2006-03-16
申请号：PCT/EP2004/052054
申请日：2004-09-06
申请人： FREESCALE SEMICONDUCTORS, INC , O'KEEFFE, Connor, J. , KELLEHER, Paul
发明人： O'KEEFFE, Connor, J. , KELLEHER, Paul
IPC分类号： H04B1/40
CPC分类号： H04B1/40 , H04B15/02 , H04B2215/064 , H04B2215/065
摘要： A wireless communication device (100) comprises a number of sub-systems (110, 120) operably coupled to a data interface (105) for routeing data between the number of sub-systems (110, 120). A clock generation function (615) generates a clock signal substantially at a data transfer rate to be used over the data interface (105) whereby the clock signal is generated at a rate that minimises harmonic content of the clock signal at operational frequencies of the wireless communication device (100). Thus, a suitable data rate is selected and supported by the data interface that accommodates the desired bandwidth, clock rate and/or chip rate of the functional elements that are coupled by the data interface within the wireless communication device (100), whilst minimising the effects of harmonic interference from the clock signal(s).
摘要翻译：无线通信设备（100）包括可操作地耦合到数据接口（105）的多个子系统（110,120），用于在子系统（110,120）的数量之间路由数据。时钟生成功能（615）基本上以数据传输速率生成要在数据接口（105）上使用的数据传输速率的时钟信号，从而以无线电的工作频率使时钟信号的谐波含量最小化的速率产生时钟信号通信设备（100）。因此，数据接口选择并支持合适的数据速率，该数据接口适应由无线通信设备（100）内的数据接口耦合的功能元件的期望带宽，时钟速率和/或码片速率，同时最小化来自时钟信号的谐波干扰的影响。

3. 发明申请

WO2008146090A1 WIRELESS COMMUNICATION UNIT, BASEBAND MODULE, RADIO FREQUENCY MODULE, WIRELESS TERMINAL AND COMPUTER PROGRAM PRODUCT 审中-公开
标题翻译：无线通信单元，基带模块，无线电频率模块，无线终端和计算机程序产品
公开(公告)号：WO2008146090A1
公开(公告)日：2008-12-04
申请号：PCT/IB2007/051979
申请日：2007-05-25
申请人： FREESCALE SEMICONDUCTOR, INC. , KELLEHER, Paul , O'KEEFFE, Conor , SCHWARTZ, Daniel B , TRAYLOR, Kevin
发明人： KELLEHER, Paul , O'KEEFFE, Conor , SCHWARTZ, Daniel B , TRAYLOR, Kevin
IPC分类号： H04B1/40
CPC分类号： H04B1/406 , H03L7/1976
摘要： A wireless communication unit (1) has two or more communication modes including one or more mobile phone mode. The unit (1) includes a baseband module (2) and a radio frequency module (3). A radio frequency interface (RF Int) of the baseband module (2) is connected to the radio frequency module (3). The radio frequency module (3) includes a baseband interface (BB Int). A clock system (22, 31) is connected to the radio frequency interface and the baseband interface. The clock system can provide a clock signal with a clock rate to the radio frequency interface and the baseband interface in one or more of the one or more mobile phone modes.
摘要翻译：无线通信单元（1）具有包括一个或多个移动电话模式的两个或多个通信模式。单元（1）包括基带模块（2）和射频模块（3）。基带模块（2）的射频接口（RF Int）被连接到射频模块（3）。射频模块（3）包括基带接口（BB Int）。时钟系统（22,31）连接到射频接口和基带接口。时钟系统可以在一个或多个移动电话模式中的一个或多个中提供具有到射频接口和基带接口的时钟速率的时钟信号。

4. 发明申请

WO2008080634A1 WIRELESS COMMUNICATION DEVICE, INTEGRATED CIRCUIT AND METHOD OF TIMING SYNCHRONISATION 审中-公开
标题翻译：无线通信设备，集成电路和时序同步的方法
公开(公告)号：WO2008080634A1
公开(公告)日：2008-07-10
申请号：PCT/EP2007/050016
申请日：2007-01-02
申请人： FREESCALE SEMICONDUCTOR, INC. , BEAMISH, Norman , KELLEHER, Paul , SCHWARTZ, Daniel B
发明人： BEAMISH, Norman , KELLEHER, Paul , SCHWARTZ, Daniel B
IPC分类号： H04B1/40
CPC分类号： H04L7/04 , H04J3/0685
摘要： A wireless communication device (100) comprises a first sub-system arranged to pass data to a second sub-system comprising timing synchronisation logic (132) operably coupled to a counter (134), such that data is sampled by the timing synchronisation logic (132) when passed to the second sub-system from the first sub-system wherein the wireless communication device (100) is characterised in that the timing synchronisation logic (132) is arranged to determine a position of a first data frame and in response thereto initiate a counting process of the counter (134) and determine a position of a second data frame and in response thereto determine a count value from the counting process of the counter (134) and in response to the count value determine whether to initiate a timing advance or timing retard operation on the data being passed to the second sub-system. In this manner, the inventive concept provides the wireless communication device with a mechanism to achieve timing synchronisation. In particular, the inventive concept may allow a radio frequency integrated circuit (RFIC) to implement timing synchronisation by advancing or retarding an 'actual' signal sent from digital baseband circuits in a 3G DigRF wireless communication device (100).
摘要翻译：无线通信设备（100）包括被配置为将数据传递到第二子系统的第一子系统，该第二子系统包括可操作地耦合到计数器（134）的定时同步逻辑（132），使得数据被定时同步逻辑 132）当从第一子系统传递到第二子系统时，其中无线通信装置（100）的特征在于定时同步逻辑（132）被布置成确定第一数据帧的位置并响应于此启动计数器（134）的计数过程并确定第二数据帧的位置，并响应于此从计数器（134）的计数处理确定计数值，并且响应于计数值确定是否启动定时对正在传送到第二子系统的数据进行提前或定时延迟操作。以这种方式，本发明的概念为无线通信设备提供了实现定时同步的机制。特别地，本发明的概念可以允许射频集成电路（RFIC）通过推进或延迟在3G DigRF无线通信设备（100）中从数字基带电路发送的“实际”信号来实现定时同步。

5. 发明申请

WO2014175915A1 HARDWARE DE-CONVOLUTION BLOCK FOR MULTI-PHASE SCANNING 审中-公开
标题翻译：用于多相扫描的硬件解调块
公开(公告)号：WO2014175915A1
公开(公告)日：2014-10-30
申请号：PCT/US2013/060385
申请日：2013-09-18
申请人： CYPRESS SEMICONDUCTOR CORPORATION , VAN DE WAERDT, Jan-Willem , HOGAN, Aaron , O'KEEFFE, Colm , KREMIN, Victor , BIHDAY, Volodymyr , KELLEHER, Paul
发明人： VAN DE WAERDT, Jan-Willem , HOGAN, Aaron , O'KEEFFE, Colm , KREMIN, Victor , BIHDAY, Volodymyr , KELLEHER, Paul
IPC分类号： G01R27/26
CPC分类号： G01R27/2605 , G06F3/0416 , G06F3/044
摘要： Apparatuses and methods of hardware de-convolution for multi-phase scanning of a touch arrays are described. One apparatus includes a memory device configured to store a capacitance map including convolved capacitance data. The convolved data are results of multi-phase transmit (TX) scanning of a sense array with multiple TX patterns. The apparatus further comprises a de-convolution circuit block coupled to the memory device. The de-convolution circuit block is configured to de-convolve the convolved capacitance data with inverses of the multiple TX patterns to obtain capacitance data for a de-convolved capacitance map.
摘要翻译：描述了用于触摸阵列的多相扫描的硬件去卷积的装置和方法。一种装置包括被配置为存储包括卷积电容数据的电容映射的存储器件。卷积数据是具有多个TX模式的感测阵列的多相位发射（TX）扫描的结果。该装置还包括耦合到存储器件的去卷积电路块。去卷积电路块被配置为使卷积电容数据与多个TX模式的反相去卷积，以获得用于去卷积电容图的电容数据。

6. 发明申请

WO2010026448A1 METHOD AND APPARATUS FOR TRANSMITTING DATA 审中-公开
标题翻译：用于发送数据的方法和装置
公开(公告)号：WO2010026448A1
公开(公告)日：2010-03-11
申请号：PCT/IB2008/053605
申请日：2008-09-05
申请人： FREESCALE SEMICONDUCTOR, INC. , KELLEHER, Paul , O'BRIEN, Michael , O'KEEFFE, Conor
发明人： KELLEHER, Paul , O'BRIEN, Michael , O'KEEFFE, Conor
IPC分类号： H04B1/40 , H04B15/02
CPC分类号： H04W56/0045 , H04B1/40 , H04B15/02 , H04B2215/067
摘要： A semiconductor device (110, 120, 200, 600) comprising interface logic (210, 610) for transmitting data bursts across an interface (105, 205, 605). The interface logic (210, 610) is arranged to transmit bursts of data across the interface (105, 205, 605) such that the start of a burst of data is substantially aligned with a symbol interval (Sl) boundary. The interface logic (210, 610) is further arranged to apply an offset to the SI boundary at the start of the burst of data.
摘要翻译：包括用于通过接口（105,205,605）发送数据脉冲串的接口逻辑（210,610）的半导体器件（110,120,200,600）。接口逻辑（210,610）被布置成通过接口（105,205,605）传输数据脉冲串，使得数据突发的开始基本上与符号间隔（S1）边界对齐。接口逻辑（210,610）还被布置为在数据突发的开始处向SI边界应用偏移。

7. 发明申请

WO2008100686A1 SELF-TEST STRUCTURE AND METHOD OF TESTING A DIGITAL INTERFACE 审中-公开
标题翻译：自测试结构和测试数字接口的方法
公开(公告)号：WO2008100686A1
公开(公告)日：2008-08-21
申请号：PCT/US2008/051838
申请日：2008-01-24
申请人： FREESCALE SEMICONDUCTOR INC. , LUCE, Lawrence B. , KELLEHER, Paul , MCSWINEY, Diarmuid
发明人： LUCE, Lawrence B. , KELLEHER, Paul , MCSWINEY, Diarmuid
IPC分类号： H04B1/38 , H04B1/48
CPC分类号： G01R31/31716
摘要： A digital interface (22) includes a self-test structure (56). The structure (56) includes a transmit section (52) and a receive section (36) having a correlator (68). A method (114) of testing the interface (22) entails coupling the receive section (36) with the transmit section (52) and communicating a test data structure (86) from the transmit section (52) to the receive section (36) at a high data rate. The test data structure (86) includes a pre-defined sync pattern (88), a header (90), and a payload (92). The receive section (36) detects the sync pattern (88) and performs time frame synchronization (148) at the correlator (68). When synchronization (148) is successful, the receive section (36) decodes (154, 162) the header (90) and the payload (92). If time frame synchronization (148) and decoding (154, 162) are successful, a validation indicator (100) is output for external observation at a low data rate.
摘要翻译：数字接口（22）包括自检结构（56）。结构（56）包括具有相关器（68）的发射部分（52）和接收部分（36）。测试接口（22）的方法（114）需要将接收部分（36）与发送部分（52）耦合并将测试数据结构（86）从发送部分（52）传送到接收部分（36）以高数据速率。测试数据结构（86）包括预定义同步模式（88），报头（90）和有效载荷（92）。接收部分（36）检测同步模式（88）并在相关器（68）处执行时间帧同步（148）。当同步（148）成功时，接收部分（36）解码（154,162）标题（90）和有效载荷（92）。如果时间帧同步（148）和解码（154,162）成功，则以低数据速率输出验证指示符（100）以进行外部观察。

8. 发明申请

WO2008083856A1 COMMUNICATION DEVICE, INTEGRATED CIRCUIT AND METHOD THEREFOR 审中-公开
标题翻译：通信设备，集成电路及其方法
公开(公告)号：WO2008083856A1
公开(公告)日：2008-07-17
申请号：PCT/EP2007/050268
申请日：2007-01-11
申请人： FREESCALE SEMICONDUCTOR, INC. , KELLEHER, Paul , GAYER, Patrick , MCSWINEY, Diarmuid
发明人： KELLEHER, Paul , GAYER, Patrick , MCSWINEY, Diarmuid
IPC分类号： H04B1/16
CPC分类号： H04W52/0241 , H04J3/0697 , H04L7/042 , H04W88/06 , Y02D70/122 , Y02D70/124 , Y02D70/144
摘要： A communication device (300) is capable of supporting communication compliant with a Dual- Mode 2.5G and 3G interface baseband (BB)-radio frequency (RF) interface standard and comprises a data interface (305) operably coupled to a number sub-systems (310, 120) and a clock circuit generating a plurality of clock phases for supporting communication there between. At least one of the number of sub-systems (310, 320) comprises a line driver and a line receiver (430); wherein the communication device (300) is characterised in that the line receiver (430) determines an end of a received data frame sent across the data interface (305) and in response thereto switches itself off.
摘要翻译：通信设备（300）能够支持符合双模2.5G和3G接口基带（BB） - 射频（RF）接口标准的通信，并且包括数据接口（305），其可操作地耦合到多个子系统（310,120）和产生多个时钟相位的时钟电路，用于支持其间的通信。多个子系统（310,320）中的至少一个包括线路驱动器和线路接收器（430）; 其特征在于，所述通信设备（300）的特征在于，所述线路接收器（430）确定通过所述数据接口（305）发送的接收数据帧的结束，并响应于此自身断开。

9. 发明申请

WO2012138396A1 A SYSTEM AND METHOD FOR SYNCHRONIZATION OF TOUCH PANEL DEVICES 审中-公开
标题翻译：用于触摸面板设备同步的系统和方法
公开(公告)号：WO2012138396A1
公开(公告)日：2012-10-11
申请号：PCT/US2011/067121
申请日：2011-12-23
申请人： CYPRESS SEMICONDUCTOR CORPORATION , VAN ANTWERPEN, Hans , SWINDLE, Scott , HOGAN, Aaron , KELLEHER, Paul
发明人： VAN ANTWERPEN, Hans , SWINDLE, Scott , HOGAN, Aaron , KELLEHER, Paul
IPC分类号： G06F3/041
CPC分类号： G06F3/0416
摘要： A system and method for synchronization of touch-panel devices is described. In one embodiment, the system includes a first controller device configured to control operations of a first portion of a touch-panel device such that the first controller device is further configured to generate a single master timing signal. The single master timing signal is configured to synchronize operation of the first controller device and a second controller device that is configured to control operations of a second portion of a touch-panel device.
摘要翻译：描述了用于触摸面板设备的同步的系统和方法。在一个实施例中，系统包括被配置为控制触摸面板设备的第一部分的操作的第一控制器设备，使得第一控制器设备进一步被配置为生成单个主定时信号。单个主定时信号被配置为使第一控制器设备和被配置为控制触摸面板设备的第二部分的操作的第二控制器设备的操作同步。

10. 发明申请

WO2010136225A1 PULSE WIDTH MODULATION SYNCHRONIZATION OF SWITCHED MODE POWER CONVERTERS 审中-公开
标题翻译：开关模式电源转换器的脉宽调制同步
公开(公告)号：WO2010136225A1
公开(公告)日：2010-12-02
申请号：PCT/EP2010/051326
申请日：2010-02-03
申请人： POWERVATION LIMITED , O'MALLEY, Eamon , KELLEHER, Paul , RINNE, Karl , ALMUKHTAR, Basil
发明人： O'MALLEY, Eamon , KELLEHER, Paul , RINNE, Karl , ALMUKHTAR, Basil
IPC分类号： H03K7/00
CPC分类号： H03K7/00 , H02J1/102 , H02M3/1584 , H03K5/1565 , H03K7/08 , H03L7/07
摘要： The present application is directed generally to switch mode power supplies operating in a master-slave configuration and provides a method of synchronizing the PWM outputs from the master and slave devices to avoid problems such, for example, the generation of beat frequencies.
摘要翻译：本申请一般涉及以主从配置工作的开关模式电源，并且提供了一种使来自主设备和从设备的PWM输出同步的方法，以避免例如产生拍频的问题。

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