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1. 发明申请

WO2012076924A1 RF AMPLIFIER CIRCUIT AND ELECTRONIC SYSTEM COMPRISING SUCH A CIRCUIT 审中-公开
标题翻译：包括这种电路的射频放大器电路和电子系统
公开(公告)号：WO2012076924A1
公开(公告)日：2012-06-14
申请号：PCT/IB2010/003412
申请日：2010-12-09
申请人： FREESCALE SEMICONDUCTORS, INC. , BOUNY, Jean Jacques
发明人： BOUNY, Jean Jacques
IPC分类号： H03F1/02 , H03F1/56 , H03F3/195 , H03F3/24
CPC分类号： H03F3/24 , H03F1/0288 , H03F1/56 , H03F3/195 , H03F3/602 , H03F2200/318 , H03F2200/387 , H03F2200/423 , H03F2200/451 , H03F2200/543
摘要： A radiofrequency, RF, amplifier circuit comprises an input for receiving an, RF, input signal and a circuit output for outputting an, amplified RF, output signal to a load. A carrier amplifier path comprises a carrier amplifier having a carrier amplifier input connected to the input for receiving the input signal and a carrier amplifier output for outputting an amplified carrier signal in both a low input power mode of the RF amplifier circuit and a high power input mode of the RF amplifier circuit. A first peak amplifier path comprises a first peak amplifier connected to the input, for receiving the input signal and outputting a first amplified peak signal, the first peak amplifier being inactive in the low input power mode. A second peak amplifier path comprises a second peak amplifier connected to the input, for receiving the input signal and outputting a second amplified peak signal, the second peak amplifier being inactive in the low input power mode. The first peak amplifier path and the second peak amplifier path have shared sub-paths in common with the carrier amplifier path. An output stage connects the paths to the circuit output and comprises the shared sub-paths, the shared sub-paths presenting a non-zero impedance to the carrier amplifier, both in the low input power mode and the high input power mode.
摘要翻译：射频RF放大器电路包括用于接收RF，输入信号的输入端和用于将放大的RF输出信号输出到负载的电路输出。载波放大器路径包括具有连接到用于接收输入信号的输入的载波放大器输入的载波放大器和用于在RF放大器电路的低输入功率模式和高功率输入两者中输出放大的载波信号的载波放大器输出模式的RF放大器电路。第一峰值放大器路径包括连接到输入端的第一峰值放大器，用于接收输入信号并输出第一放大峰值信号，第一峰值放大器在低输入功率模式下是无效的。第二峰值放大器路径包括连接到输入端的第二峰值放大器，用于接收输入信号并输出第二放大峰值信号，第二峰值放大器在低输入功率模式下是无效的。第一峰值放大器路径和第二峰值放大器路径具有与载波放大器路径共同的共享子路径。在低输入功率模式和高输入功率模式中，输出级将路径连接到电路输出并且包括共享子路径，共享子路径对载波放大器呈现非零阻抗。

2. 发明申请

WO2010077467A1 METHOD OF FORMING GATE STACK AND STRUCTURE THEREOF 审中-公开
标题翻译：形成门架及其结构的方法
公开(公告)号：WO2010077467A1
公开(公告)日：2010-07-08
申请号：PCT/US2009/065031
申请日：2009-11-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , FREESCALE SEMICONDUCTORS INC. , RAMACHANDRAN, Ravikumar , YAN, Hongwen , MOUMEN, Naim , SCHAEFFER, James, Kenyon , KRISHNAN, Siddarth, A. , WONG, Keith, Kwong Hon , KWON, Unoh , BELYANSKY, Michael, P. , WISE, Richard
发明人： RAMACHANDRAN, Ravikumar , YAN, Hongwen , MOUMEN, Naim , SCHAEFFER, James, Kenyon , KRISHNAN, Siddarth, A. , WONG, Keith, Kwong Hon , KWON, Unoh , BELYANSKY, Michael, P. , WISE, Richard
IPC分类号： H01L21/3205
CPC分类号： H01L21/823842 , H01L21/823857
摘要： Embodiments of the present invention provide a method of forming gate stacks for field-effect- transistors. The method includes forming a metal-containing layer directly on a first titanium-nitride (TiN) layer, the first TiN layer covering areas of a semiconductor substrate designated for first and second types of field-effect-transistors; forming a capping layer of a second TiN layer on top of the metal-containing layer; patterning the second TiN layer and the metal-containing layer to cover only a first portion of the first TiN layer, the first portion of the first TiN layer covering an area designated for the first type of field-effect-transistors; etching away a second portion of the first TiN layer exposed by the patterning while protecting the first portion of the first TiN layer, from the etching, through covering with at least a portion of thickness of the patterned metal-containing layer; and forming a third TiN layer covering an areas of the semiconductor substrate designated for the second type of field-effect-transistors.
摘要翻译：本发明的实施例提供了一种形成场效应晶体管的栅叠层的方法。该方法包括直接在第一氮化钛（TiN）层上形成含金属层，第一TiN层覆盖用于第一和第二类场效应晶体管的半导体衬底的区域; 在所述含金属层的顶部上形成第二TiN层的覆盖层; 图案化第二TiN层和含金属层以仅覆盖第一TiN层的第一部分，第一TiN层的第一部分覆盖指定用于第一类型的场效应晶体管的区域; 蚀刻通过图案化暴露的第一TiN层的第二部分，同时通过覆盖图案化的含金属层的厚度的至少一部分来保护第一TiN层的第一部分免受蚀刻; 以及形成覆盖指定用于第二类场效应晶体管的半导体衬底的区域的第三TiN层。

3. 发明申请

WO2006027026A1 APPARATUS AND CONTROL INTERFACE THEREFOR 审中-公开
标题翻译：设备和控制接口
公开(公告)号：WO2006027026A1
公开(公告)日：2006-03-16
申请号：PCT/EP2004/052070
申请日：2004-09-07
申请人： FREESCALE SEMICONDUCTORS, INC , O'KEEFFE, Connor J , KELLEHER, Paul , SCHWARTZ, Daniel
发明人： O'KEEFFE, Connor J , KELLEHER, Paul , SCHWARTZ, Daniel
IPC分类号： G06F13/38
CPC分类号： G06F13/4291
摘要： An apparatus (100) comprises a number of sub-systems (110, 120) and a control interface (105) operably coupled to sub-systems (110, 120) for routeing data therebetween. A strobe generation function (225, 325) is operably coupled to the control interface (105) and configured to generate a plurality of different strobe signals to differentiate between different intended receiving devices. Thus, different strobe signals may be multiplexed onto a single control interface link, based on a pulse width or voltage magnitude characteristics of the respective strobe signals. A strobe decoder function is operably coupled to the control interface (105) and configured to decode a plurality of different strobe signals to differentiate between triggering sub-systems on receiving devices.
摘要翻译：装置（100）包括多个子系统（110,120）和可操作地耦合到子系统（110,120）的控制接口（105），用于在其间路由数据。选通生成功能（225,325）可操作地耦合到控制接口（105）并且被配置为生成多个不同的选通信号以区分不同的预期接收设备。因此，不同的选通信号可以基于各个选通信号的脉冲宽度或电压幅度特性而复用到单个控制接口链路上。选通解码器功能可操作地耦合到控制接口（105）并且被配置为解码多个不同的选通信号以区分接收设备上的触发子系统。

4. 发明申请

WO2006027025A1 WIRELESS COMMUNICATION DEVICE AND DATA INTERFACE 审中-公开
标题翻译：无线通信设备和数据接口
公开(公告)号：WO2006027025A1
公开(公告)日：2006-03-16
申请号：PCT/EP2004/052054
申请日：2004-09-06
申请人： FREESCALE SEMICONDUCTORS, INC , O'KEEFFE, Connor, J. , KELLEHER, Paul
发明人： O'KEEFFE, Connor, J. , KELLEHER, Paul
IPC分类号： H04B1/40
CPC分类号： H04B1/40 , H04B15/02 , H04B2215/064 , H04B2215/065
摘要： A wireless communication device (100) comprises a number of sub-systems (110, 120) operably coupled to a data interface (105) for routeing data between the number of sub-systems (110, 120). A clock generation function (615) generates a clock signal substantially at a data transfer rate to be used over the data interface (105) whereby the clock signal is generated at a rate that minimises harmonic content of the clock signal at operational frequencies of the wireless communication device (100). Thus, a suitable data rate is selected and supported by the data interface that accommodates the desired bandwidth, clock rate and/or chip rate of the functional elements that are coupled by the data interface within the wireless communication device (100), whilst minimising the effects of harmonic interference from the clock signal(s).
摘要翻译：无线通信设备（100）包括可操作地耦合到数据接口（105）的多个子系统（110,120），用于在子系统（110,120）的数量之间路由数据。时钟生成功能（615）基本上以数据传输速率生成要在数据接口（105）上使用的数据传输速率的时钟信号，从而以无线电的工作频率使时钟信号的谐波含量最小化的速率产生时钟信号通信设备（100）。因此，数据接口选择并支持合适的数据速率，该数据接口适应由无线通信设备（100）内的数据接口耦合的功能元件的期望带宽，时钟速率和/或码片速率，同时最小化来自时钟信号的谐波干扰的影响。

5. 发明申请

WO2005015833A1 ARRANGEMENT AND METHOD FOR CONNECTING A PROCESSING NODE IN A DISTRIBUTED SYSTEM 审中-公开
标题翻译：在分布式系统中连接加工节点的布置和方法
公开(公告)号：WO2005015833A1
公开(公告)日：2005-02-17
申请号：PCT/EP2004/051700
申请日：2004-08-03
申请人： FREESCALE SEMICONDUCTORS, INC , TEMPLE, Christopher P
发明人： TEMPLE, Christopher P
IPC分类号： H04L12/26
CPC分类号： H04L43/50
摘要： An arrangement for connecting a processing node in a distributed system containing fail-uncontrolled processing nodes, the arrangement comprising: receiver means for receiving signals from another processing node of the system, and node guardian means coupled to the receiver means wherein the node guardian means includes switch means for receiving a plurality of unidirectional input signals, logic means coupled to the switch means for combining the plurality of received input signals according to a predetermined logic function, and control means coupled to the switch means for controlling application of the plurality of received signals to the logic means for controlling reception of signals thereat so as to reduce reception by the processing node of uncontrolled transmission from another processing node of the system.
摘要翻译：一种用于连接包含故障不受控制的处理节点的分布式系统中的处理节点的装置，所述装置包括：用于从系统的另一个处理节点接收信号的接收器装置，以及耦合到接收器装置的节点监护装置，其中节点监护装置包括用于接收多个单向输入信号的开关装置，耦合到所述开关装置的逻辑装置，用于根据预定的逻辑功能组合所述多个接收的输入信号，以及耦合到所述开关装置的控制装置，用于控制所述多个接收信号的应用涉及用于控制信号接收的逻辑装置，以便减少处理节点从系统的另一个处理节点接收不受控制的传输。

6. 发明申请

WO2004114525A1 PHASE LOCKED LOOP FILTER 审中-公开
标题翻译：相锁式环路滤波器
公开(公告)号：WO2004114525A1
公开(公告)日：2004-12-29
申请号：PCT/EP2004/006481
申请日：2004-06-16
申请人： FREESCALE SEMICONDUCTORS, INC , GUENAIS, Mikael
发明人： GUENAIS, Mikael
IPC分类号： H03L7/093
CPC分类号： H03L7/093 , H03L7/0893 , H03L7/18
摘要： A phase locked loop filter comprising a first capacitor for connecting to a first charge pump path; and a parallel resistor/capacitor circuit for connecting to a second charge pump path with the resistor/capacitor circuit having a second capacitor; wherein the first capacitor and second capacitor are connected in series to allow a voltage associated with the first capacitor and a voltage associated with the parallel resistor/capacitor circuit to be added together.
摘要翻译：一种锁相环滤波器，包括用于连接到第一电荷泵路径的第一电容器; 以及用于连接到具有第二电容器的电阻器/电容器电路的第二电荷泵路径的并联电阻器/电容器电路; 其中所述第一电容器和所述第二电容器串联连接以允许与所述第一电容器相关联的电压和与所述并联电阻器/电容器电路相关联的电压加在一起。

7. 发明申请

WO2007106959A3 RECONFIGURABLE MULTI-PROCESSING COARSE-GRAIN ARRAY 审中-公开
公开(公告)号：WO2007106959A3
公开(公告)日：2007-09-27
申请号：PCT/BE2007/000027
申请日：2007-03-19
申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW , FREESCALE SEMICONDUCTORS INC. , KANSTEIN, Andreas , BEREKOVIC, Mladen
发明人： KANSTEIN, Andreas , BEREKOVIC, Mladen
IPC分类号： G06F15/80
摘要： A signal processing device adapted for simultaneous processing of at least two process threads in a multi-processing manner is described. It comprises a plurality of functional units capable of executing word- or subword- level operations on data, a means for interconnecting said plurality of functional units, said means for interconnecting supporting a plurality of interconnect arrangements that can be dynamically switched, at least one of said interconnect arrangements interconnecting said plurality of functional units into at least two non- overlapping processing units each with a pre-determined topology, the signal processing device furthermore comprising at least two control modules, each control module being assigned to one of said processing units. The present invention also provides a method for executing an application on such a signal processing device, a method for compilation of application source code in order to obtain compiled code being executable on such a signal processing device, and to optimisation methods for applications to be executed on such a signal processing device.

8. 发明申请

WO2005013523A1 NETWORK NODE 审中-公开
标题翻译：网络节点
公开(公告)号：WO2005013523A1
公开(公告)日：2005-02-10
申请号：PCT/EP2004/051504
申请日：2004-07-15
申请人： FREESCALE SEMICONDUCTORS, INC , RAUSCH, Mathias P , TEMPLE, Christopher P
发明人： RAUSCH, Mathias P , TEMPLE, Christopher P
IPC分类号： H04J3/06
CPC分类号： H04J3/0652 , H04L12/66
摘要： A computer node (16) comprising a synchronisation unit (21) for comparing network timing information for a first network (11) with network timing information for a second network (112) and for communicating to the first network (11) the sign of the difference between the first network timing information and the second network timing information to allow the first network (11) to alter its network timing information using the sign of the difference to allow the network timing difference between the first network (11) and the second network (12) to be reduced.
摘要翻译：一种计算机节点（16），包括同步单元（21），用于将用于第一网络（11）的网络定时信息与用于第二网络（112）的网络定时信息进行比较，并用于与所述第一网络（11）通信所述第一网络第一网络定时信息和第二网络定时信息之间的差异，以允许第一网络（11）使用差异的符号来改变其网络定时信息，以允许第一网络（11）和第二网络（12）减少。

9. 发明申请

WO2006027643A1 A VIRTUAL ADDRESS CACHE AND METHOD FOR SHARING DATA STORED IN A VIRTUAL ADDRESS CACHE 审中-公开
标题翻译：用于共享虚拟地址高速缓存中存储数据的虚拟地址高速缓存和方法
公开(公告)号：WO2006027643A1
公开(公告)日：2006-03-16
申请号：PCT/IB2004/052943
申请日：2004-09-07
申请人： FREESCALE SEMICONDUCTORS, INC , BACHER, Moshe , EFRAT, Jacob , ELDOR, Alon , TOKAR, Yakov , PELED, Itay , ANSCHEL, Moshe
发明人： PELED, Itay , ANSCHEL, Moshe
IPC分类号： G06F12/08
CPC分类号： G06F12/0842
摘要： A virtual address cache comprising a comparator arranged to receive a virtual address for addressing data associated with a task and a memory, wherein the comparator is arranged to make a determination as to whether data associated with the received virtual address is stored in the memory based upon an indication that the virtual address is associated with data shared between a first task and a second task and a comparison of the received virtual address with an address associated with data stored in memory.
摘要翻译：一种虚拟地址高速缓存，包括一个比较器，被配置为接收用于寻址与任务和存储器相关联的数据的虚拟地址，其中该比较器被设置为基于与该接收到的虚拟地址相关联的数据是否基于指示虚拟地址与第一任务和第二任务之间共享的数据相关联，以及所接收的虚拟地址与与存储在存储器中的数据相关联的地址的比较。

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