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1. 发明申请

WO2008100686A1 SELF-TEST STRUCTURE AND METHOD OF TESTING A DIGITAL INTERFACE 审中-公开
标题翻译：自测试结构和测试数字接口的方法
公开(公告)号：WO2008100686A1
公开(公告)日：2008-08-21
申请号：PCT/US2008/051838
申请日：2008-01-24
申请人： FREESCALE SEMICONDUCTOR INC. , LUCE, Lawrence B. , KELLEHER, Paul , MCSWINEY, Diarmuid
发明人： LUCE, Lawrence B. , KELLEHER, Paul , MCSWINEY, Diarmuid
IPC分类号： H04B1/38 , H04B1/48
CPC分类号： G01R31/31716
摘要： A digital interface (22) includes a self-test structure (56). The structure (56) includes a transmit section (52) and a receive section (36) having a correlator (68). A method (114) of testing the interface (22) entails coupling the receive section (36) with the transmit section (52) and communicating a test data structure (86) from the transmit section (52) to the receive section (36) at a high data rate. The test data structure (86) includes a pre-defined sync pattern (88), a header (90), and a payload (92). The receive section (36) detects the sync pattern (88) and performs time frame synchronization (148) at the correlator (68). When synchronization (148) is successful, the receive section (36) decodes (154, 162) the header (90) and the payload (92). If time frame synchronization (148) and decoding (154, 162) are successful, a validation indicator (100) is output for external observation at a low data rate.
摘要翻译：数字接口（22）包括自检结构（56）。结构（56）包括具有相关器（68）的发射部分（52）和接收部分（36）。测试接口（22）的方法（114）需要将接收部分（36）与发送部分（52）耦合并将测试数据结构（86）从发送部分（52）传送到接收部分（36）以高数据速率。测试数据结构（86）包括预定义同步模式（88），报头（90）和有效载荷（92）。接收部分（36）检测同步模式（88）并在相关器（68）处执行时间帧同步（148）。当同步（148）成功时，接收部分（36）解码（154,162）标题（90）和有效载荷（92）。如果时间帧同步（148）和解码（154,162）成功，则以低数据速率输出验证指示符（100）以进行外部观察。

2. 发明申请

WO2012036987A3 HIGH THROUGHPUT SEMICONDUCTOR DEVICE TESTING 审中-公开
标题翻译：高通量半导体器件测试
公开(公告)号：WO2012036987A3
公开(公告)日：2012-06-07
申请号：PCT/US2011051038
申请日：2011-09-09
申请人： TERADYNE INC , LUCE LAWRENCE B
发明人： LUCE LAWRENCE B
IPC分类号： G01R31/28
CPC分类号： G01R31/316 , G01R31/2839
摘要： A test system that provides an output signal for analysis without requiring the test hardware to be idle during a settling interval. The test system includes a preprocessor that identifies the near-DC drift that occurs in the output signal and then adjusts the output signal to remove the near-DC drift. A set of values representing the near-DC drift at each of multiple times during the acquisition of a signal for analysis may be computed and used to model a settling profile of the signal by fitting a curve to the set of values. The model of the settling profile may then be subtracted from samples representing the output signal to provide an adjusted signal for further analysis.
摘要翻译：测试系统提供输出信号用于分析，而不需要测试硬件在建立间隔期间闲置。该测试系统包括一个预处理器，用于识别输出信号中发生的接近DC漂移，然后调整输出信号以消除近DC漂移。可以计算在获取用于分析的信号期间多次表示多次接近DC漂移的一组值，并通过将曲线拟合到该组值来对信号的建立曲线进行建模。然后可以从表示输出信号的采样中减去建立曲线的模型，以提供用于进一步分析的调整信号。

3. 发明申请

WO2012036987A2 HIGH THROUGHPUT SEMICONDUCTOR DEVICE TESTING 审中-公开
标题翻译：高通量半导体器件测试
公开(公告)号：WO2012036987A2
公开(公告)日：2012-03-22
申请号：PCT/US2011/051038
申请日：2011-09-09
申请人： TERADYNE, INC. , LUCE, Lawrence, B.
发明人： LUCE, Lawrence, B.
IPC分类号： G01R31/28
CPC分类号： G01R31/316 , G01R31/2839
摘要： A test system that provides an output signal for analysis without requiring the test hardware to be idle during a settling interval. The test system includes a preprocessor that identifies the near-DC drift that occurs in the output signal and then adjusts the output signal to remove the near-DC drift. A set of values representing the near-DC drift at each of multiple times during the acquisition of a signal for analysis may be computed and used to model a settling profile of the signal by fitting a curve to the set of values. The model of the settling profile may then be subtracted from samples representing the output signal to provide an adjusted signal for further analysis.
摘要翻译：提供输出信号进行分析的测试系统，而不需要测试硬件在稳定间隔期间空闲。测试系统包括一个预处理器，用于识别在输出信号中发生的近DC漂移，然后调整输出信号以去除近DC漂移。可以计算表示在用于分析的信号获取期间的多次中的近DC漂移的一组值，并且用于通过将曲线拟合到该组值来建模信号的建立分布。然后可以从表示输出信号的样本中减去沉降曲线的模型，以提供调整后的信号用于进一步分析。

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