专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2007053339A2 METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE AND STRUCTURE THEREOF 审中-公开
标题翻译：形成半导体结构及其结构的方法
公开(公告)号：WO2007053339A2
公开(公告)日：2007-05-10
申请号：PCT/US2006041146
申请日：2006-10-20
申请人： FREESCALE SEMICONDUCTOR INC , THEAN VOON-YEW , CHEN JIAN , NGUYEN BICH-YEN , SADAKA MARIAM G , ZHANG DA
发明人： THEAN VOON-YEW , CHEN JIAN , NGUYEN BICH-YEN , SADAKA MARIAM G , ZHANG DA
IPC分类号： H01L21/84
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/7842 , H01L29/785 , Y10S438/938
摘要： Forming a semiconductor structure includes providing a substrate (10) having a strained semiconductor layer (14) overlying an insulating layer (12), providing a first device region (18) for forming a first plurality of devices having a first conductivity type, providing a second device region (20) for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region (18) having a first conductivity type, forming an insulating layer (34) overlying at least an active area (32) of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material (46) overlying at least a portion of the insulating layer.
摘要翻译：形成半导体结构包括提供具有覆盖在绝缘层（12）上的应变半导体层（14）的衬底（10），提供用于形成具有第一导电类型的第一多个器件的第一器件区域（18）用于形成具有第二导电类型的第二多个器件的第二器件区域（20），并且使第二器件区域中的应变半导体层变厚，使得第二器件区域中的应变半导体层具有较小的应变半导体层的应变第一个设备区域。或者，形成半导体结构包括提供具有第一导电类型的第一区域（18），形成覆盖第一区域的至少有源区域（32）的绝缘层（34），各向异性地蚀刻绝缘层，以及各向异性蚀刻绝缘层，去除覆盖绝缘层的至少一部分的栅电极材料（46）。

2. 发明申请

WO2006039038A3 METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A STRAINED CHANNEL AND A HETEROJUNCTION SOURCE/DRAIN 审中-公开
标题翻译：形成具有应变通道和异质结源极/漏极的半导体器件的方法
公开(公告)号：WO2006039038A3
公开(公告)日：2006-11-09
申请号：PCT/US2005031001
申请日：2005-08-31
申请人： FREESCALE SEMICONDUCTOR INC , THEAN VOON-YEW , SADAKA MARIAM G , WHITE TED R , BARR ALEXANDER L , KOLAGUNTA VENKAT R , NGUYEN BICH-YEN , VARTANIAN VICTOR H , ZHANG DA
发明人： THEAN VOON-YEW , SADAKA MARIAM G , WHITE TED R , BARR ALEXANDER L , KOLAGUNTA VENKAT R , NGUYEN BICH-YEN , VARTANIAN VICTOR H , ZHANG DA
IPC分类号： H01L21/44 , H01L21/3205 , H01L21/331 , H01L21/336 , H01L21/338 , H01L21/4763 , H01L21/8222
CPC分类号： H01L21/2254 , H01L29/665 , H01L29/66787 , H01L29/7848 , H01L29/785 , H01L29/78648
摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.
摘要翻译：通过将栅极（22）置于优选为硅的半导体层（16）上来形成半导体器件（10）。例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域上方。热过程将应力源材料扩散到半导体层中。发生横向扩散以形成应变材料层（30）紧邻应变通道的应变通道（17）的形成。扩展注入从应力源材料层的第一部分创建源极和漏极注入。应力源材料层的第二部分保留在应变沟道与源极和漏极注入物之间的沟道中。因此在应变通道中形成异质结。在另一种形式中，发生应激材料的氧化而不是延伸植入物以形成应变通道。

3. 发明申请

WO2006107419A2 METHOD OF MAKING A DUAL STRAINED CHANNEL SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造双应变通道半导体器件的方法
公开(公告)号：WO2006107419A2
公开(公告)日：2006-10-12
申请号：PCT/US2006005471
申请日：2006-02-16
申请人： FREESCALE SEMICONDUCTOR INC , SADAKA MARIAM G , BARR ALEXANDER L , JOVANOVIC DEJAN , NGUYEN BICH-YEN , THEAN VOON-YEW , THOMAS SHAWN G , WHITE TED R
发明人： SADAKA MARIAM G , BARR ALEXANDER L , JOVANOVIC DEJAN , NGUYEN BICH-YEN , THEAN VOON-YEW , THOMAS SHAWN G , WHITE TED R
IPC分类号： H01L21/8238
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device (10) includes integrating strained Si (16) and compressed SiGe (28) with trench isolation (24) for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.
摘要翻译：根据本公开的实施例，制造双应变通道半导体器件（10）的过程包括将应变Si（16）和压缩SiGe（28）与沟槽隔离（24）集成，以实现同时的NMOS和PMOS性能增强。如本文所述，NMOS和PMOS的集成可以以几种方式实现，以实现与浅沟槽隔离兼容的NMOS和PMOS沟道。

4. 发明申请

WO2007130728A3 ELECTRONIC DEVICE INCLUDING SEMICONDUCTOR ISLANDS OF DIFFERENT THICKNESSES OVER AN INSULATING LAYER AND A PROCESS OF FORMING THE SAME 审中-公开
标题翻译：包含绝缘层的半导体岛的电子器件及其形成方法
公开(公告)号：WO2007130728A3
公开(公告)日：2008-11-06
申请号：PCT/US2007062534
申请日：2007-02-22
申请人： FREESCALE SEMICONDUCTOR INC , SADAKA MARIAM G , NGUYEN BICH-YEN , THEAN VOON-YEW
发明人： SADAKA MARIAM G , NGUYEN BICH-YEN , THEAN VOON-YEW
IPC分类号： H01L21/8238
CPC分类号： H01L21/32 , H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L21/84
摘要： A process of forming an electronic device can include forming a patterned oxidation-resistant layer (124) over a semiconductor layer (106) that overlies a substrate (100), and patterning the semiconductor layer to form a semiconductor island (202, 204, 206, 208). The semiconductor island includes a first surface and a second surface opposite the first surface, and the first surface lies closer to the substrate, as compared to the second surface. The process can also include forming an oxidation-resistant material (424) along a side of the semiconductor island or selectively depositing a semiconductor material along a side of the semiconductor island. The process can further include exposing the patterned oxidation-resistant layer and the semiconductor island to an oxygen-containing ambient, wherein a first portion of the semiconductor island along the first surface is oxidized during exposing the patterned oxidation-resistant layer, the semiconductor island, and the oxidation-resistant material to an oxygen-containing ambient.
摘要翻译：形成电子器件的工艺可以包括在覆盖在衬底（100）上的半导体层（106）上形成图案化的抗氧化层（124），并且图案化半导体层以形成半导体岛（202,204,206 ，208）。半导体岛包括与第一表面相对的第一表面和第二表面，并且第一表面与第二表面相比更靠近基底。该方法还可以包括沿着半导体岛的一侧形成抗氧化材料（424）或沿着半导体岛的一侧选择性地沉积半导体材料。该方法还可以包括将图案化的抗氧化层和半导体岛暴露于含氧环境中，其中沿着第一表面的半导体岛的第一部分在曝光图案化的抗氧化层，半导体岛，并将抗氧化材料转化为含氧环境。

5. 发明申请

WO2007092655A3 METHOD TO SELECTIVELY FORM REGIONS HAVING DIFFERING PROPERTIES AND STRUCTURE 审中-公开
标题翻译：选择性区域具有不同性质和结构的方法
公开(公告)号：WO2007092655A3
公开(公告)日：2007-12-21
申请号：PCT/US2007060259
申请日：2007-01-09
申请人： FREESCALE SEMICONDUCTOR INC , SADAKA MARIAM G , NGUYEN BICH-YEN , THEAN VOON-YEW , WHITE TED R
发明人： SADAKA MARIAM G , NGUYEN BICH-YEN , THEAN VOON-YEW , WHITE TED R
IPC分类号： H01L29/00
CPC分类号： H01L21/823807 , H01L21/76264 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , Y10S438/973
摘要： A semiconductor device is formed having two physically separate regions (16, 28) with differing properties such as different surface orientation, crystal rotation, strain or composition. In one form a first layer (16) having a first property is formed on an insulating layer (14). The first layer is isolated into first (16) and second (28) physically separate areas. After this physical separation, only the first area (28) is amorphized. A donor wafer (30) is placed in contact with the first (28) and second (16) areas. The semiconductor device (10) is annealed to modify the first (28) of the first (28) and second (16) separate areas to have a different property from the second of the first and second separate areas. The donor wafer (30) is removed and at least one semiconductor structure (32, 34) is formed in each of the first (28) and second (16) physically separate areas. In another form, the separate regions (114) are a bulk substrate (112) and an electrically isolated region (116) within the bulk substrate (112).
摘要翻译：形成具有两个物理上分离的区域（16,28）的半导体器件，所述区域具有不同的性质，例如不同的表面取向，晶体旋转，应变或组成。在一种形式中，在绝缘层（14）上形成具有第一特性的第一层（16）。第一层被隔离成第一（16）和第二（28）物理上分开的区域。在物理分离之后，只有第一区域（28）被非晶化。施主晶片（30）放置成与第一（28）和第二（16）区域接触。对半导体器件（10）进行退火以修改第一（28）和第二（16）分离区域的第一（28）以具有与第一和第二分离区域中的第二个不同的特性。施主晶片（30）被移除并且在第一（28）和第二（16）物理分离区域中的每一个中形成至少一个半导体结构（32,34）。在另一种形式中，分离区域（114）是体衬底（112）内的体衬底（112）和电隔离区域（116）。

6. 发明申请

WO2005034191A3 TEMPLATE LAYER FORMATION 审中-公开
标题翻译：模板层形成
公开(公告)号：WO2005034191A3
公开(公告)日：2006-03-09
申请号：PCT/US2004030088
申请日：2004-09-14
申请人： FREESCALE SEMICONDUCTOR INC , LIU CHUN-LI , SADAKA MARIAM G , BARR ALEXANDER L , NGUYEN BICH-YEN , THEAN VOON-YEW , THOMAS SHAWN G , WHITE TED R , XIE QIANGHUA
发明人： LIU CHUN-LI , SADAKA MARIAM G , BARR ALEXANDER L , NGUYEN BICH-YEN , THEAN VOON-YEW , THOMAS SHAWN G , WHITE TED R , XIE QIANGHUA
IPC分类号： H01L20060101 , H01L21/00 , H01L21/31 , H01L21/331 , H01L21/336 , H01L21/338 , H01L21/8234 , H01L21/84
摘要： A process for forming strained semiconductor layers. The process include flowing a chlorine bearing gas (e.g. hydrogen chloride, chlorine, carbon tetrachloride, and trichloroethane) over the wafer while heating the wafer. In one example, the chorine bearing gas is flowed during a condensation process on a semiconductor layer that is used as a template layer for forming a strain semiconductor layer (e.g. strain silicon). In other examples, the chlorine bearing gas is flowed during a post bake of the wafer after the condensation operation.
摘要翻译：一种形成应变半导体层的工艺。该方法包括在加热晶片的同时使含氯气体（例如氯化氢，氯气，四氯化碳和三氯乙烷）流过晶片。在一个实例中，在用作形成应变半导体层（例如应变硅）的模板层的半导体层上的冷凝过程中，含有轴承气体流动。在其他实例中，在冷凝操作之后，在晶片的后烘烤期间，含氯气体流动。

7. 发明申请

WO2005081748A3 SEMICONDUCTOR STRUCTURE HAVING STRAINED SEMICONDUCTOR AND METHOD THEREFOR 审中-公开
标题翻译：具有应变半导体的半导体结构及其方法
公开(公告)号：WO2005081748A3
公开(公告)日：2006-06-08
申请号：PCT/US2005001532
申请日：2005-01-12
申请人： FREESCALE SEMICONDUCTOR INC , BARR ALEXANDER L , JOVANOVIC DEJAN , NGUYEN BICH-YEN , SADAKA MARIAM G , THEAN VOON-YEW , WHITE TED R
发明人： BARR ALEXANDER L , JOVANOVIC DEJAN , NGUYEN BICH-YEN , SADAKA MARIAM G , THEAN VOON-YEW , WHITE TED R
IPC分类号： H01L21/336 , H01L21/00 , H01L21/46 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/04
CPC分类号： H01L27/1203 , H01L21/76254 , H01L21/823412 , H01L21/823807 , H01L21/84
摘要： A first semiconductor structure (10) has a silicon substrate (12), a first silicon germanium layer (14) grown on the silicon, a second silicon germanium layer (16) on the first silicon germanium layer (14), and a strained silicon layer (18) on the second silicon germanium layer (16). A second semiconductor structure (22) has a silicon substrate (24) and an insulating top layer (26). The silicon layer (18) of the first semiconductor structure (10) is bonded to the insulator layer (26) to form a third semiconductor structure (30). The second silicon germanium layer (16) is cut to separate most of the first semiconductor structure (10) from the third semiconductor structure (30). The silicon germanium layer (16) is removed to expose the strained silicon layer (18) where transistors (32 & 34) are subsequently formed, which is then the only layer remaining from the first semiconductor structure (10). The transistors (32 & 34) are oriented along the direction and at a 45 degree angle to the direction of the base silicon layer (24) of the second semiconductor structure.
摘要翻译：第一半导体结构（10）具有硅衬底（12），在硅上生长的第一硅锗层（14），第一硅锗层（14）上的第二硅锗层（16）和应变硅层（18）在第二硅锗层（16）上。第二半导体结构（22）具有硅衬底（24）和绝缘顶层（26）。第一半导体结构（10）的硅层（18）接合到绝缘体层（26）以形成第三半导体结构（30）。切割第二硅锗层（16）以将大部分第一半导体结构（10）与第三半导体结构（30）分离。去除硅锗层（16）以暴露应变硅层（18），其中随后形成晶体管（32和34），其然后是从第一半导体结构（10）剩余的唯一层。晶体管（32和34）沿第一半导体结构的基极硅层（24）的<100>方向和<100>方向成45度角。

8. 发明申请

WO2007133870A3 SELECTIVE UNIAXIAL STRESS RELAXATION BY LAYOUT OPTIMIZATION IN STRAINED SILICON ON INSULATOR INTEGRATED CIRCUIT 审中-公开
标题翻译：绝缘子集成电路中应变硅中布线优化的选择性单相应力放松
公开(公告)号：WO2007133870A3
公开(公告)日：2008-05-08
申请号：PCT/US2007066436
申请日：2007-04-11
申请人： FREESCALE SEMICONDUCTOR INC , NGUYEN BICH-YEN , THEAN VOON-YEW
发明人： NGUYEN BICH-YEN , THEAN VOON-YEW
IPC分类号： H01L29/76
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/0207 , H01L29/1033 , H01L29/41758 , H01L29/41775 , H01L29/6659 , H01L29/7843 , H01L29/7848 , H01L29/78654
摘要： An integrated circuit (200) includes NMOS and PMOS transistors (220, 230). The NMOS (220) has a strained channel having first and second stress values along first and second axes respectively. The PMOS (230) has a strained channel having third and fourth stress values along the first and second axes. The first value stress differs from the third value and the second value differs from the fourth value. The NMOS (220) and PMOS (230) have a common length (L) and effective width (W), but differ in length of diffusion (SA) and/ width of source/drain (WS). The NMOS WS may exceed the PMOS WS. The NMOS (220) may include multiple dielectric structures in the active layer underlying the gate The SA of the PMOS (230) may be less than the SA of the NMOS (220).
摘要翻译：集成电路（200）包括NMOS和PMOS晶体管（220,230）。 NMOS（220）具有分别具有沿着第一和第二轴的第一和第二应力值的应变通道。 PMOS（230）具有沿第一和第二轴具有第三和第四应力值的应变通道。第一值应力与第三值不同，第二值与第四值不同。 NMOS（220）和PMOS（230）具有公共长度（L）和有效宽度（W），但扩散长度（SA）和源极/漏极（WS）的宽度不同。 NMOS WS可能超过PMOS WS。 NMOS（220）可以包括位于栅极下方的有源层中的多个电介质结构，PMOS（230）的SA可以小于NMOS（220）的SA。

9. 发明申请

WO2006023197A3 SEMICONDUCTOR TRANSISTOR HAVING STRUCTURAL ELEMENTS OF DIFFERING MATERIALS AND METHOD OF FORMATION 审中-公开
标题翻译：具有不同材料结构元素的半导体晶体管及其形成方法
公开(公告)号：WO2006023197A3
公开(公告)日：2006-04-27
申请号：PCT/US2005026063
申请日：2005-07-22
申请人： FREESCALE SEMICONDUCTOR INC , THEAN VOON-YEW , TRIYOSO DINA H , NGUYEN BICH-YEN
发明人： THEAN VOON-YEW , TRIYOSO DINA H , NGUYEN BICH-YEN
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/84 , H01L29/165 , H01L29/51
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L21/823878 , H01L21/84 , H01L29/165 , H01L29/517 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7848
摘要： A transistor (10) is formed using a semiconductor substrate (14) and forming a control electrode (49) overlying the semiconductor substrate. A first current electrode (70) is formed within the semiconductor substrate and adjacent the control electrode. The first current electrode has a first predetermined semiconductor material. A second current electrode (84) is formed within the semiconductor substrate and adjacent the control electrode to form a channel (26) within the semiconductor substrate. The second current electrode has a second predetermined semiconductor material that is different from the first predetermined semiconductor material. The first predetermined semiconductor material is chosen to optimize bandgap energy of the first current electrode, and the second predetermined semiconductor material is chosen to optimize strain of the channel.
摘要翻译：使用半导体衬底（14）形成晶体管（10）并形成覆盖在半导体衬底上的控制电极（49）。第一电流电极（70）形成在半导体衬底内并与控制电极相邻。第一电流电极具有第一预定半导体材料。第二电流电极（84）形成在半导体衬底内并与控制电极相邻以在半导体衬底内形成通道（26）。第二电流电极具有与第一预定半导体材料不同的第二预定半导体材料。选择第一预定半导体材料以优化第一电流电极的带隙能量，并且选择第二预定半导体材料以优化通道的应变。

10. 发明申请

WO2006033746A2 METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A METAL LAYER 审中-公开
标题翻译：形成具有金属层的半导体器件的方法
公开(公告)号：WO2006033746A2
公开(公告)日：2006-03-30
申请号：PCT/US2005029772
申请日：2005-08-23
申请人： FREESCALE SEMICONDUCTOR INC , STEVENS TAB A , GOOLSBY BRIAN J , NGUYEN BICH-YEN , THEAN VOON-YEW
发明人： STEVENS TAB A , GOOLSBY BRIAN J , NGUYEN BICH-YEN , THEAN VOON-YEW
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28088 , H01L21/32136 , H01L21/32137 , H01L29/4908 , H01L29/4966 , H01L29/517 , H01L29/785 , Y10S438/963
摘要： A metal layer (24) is formed over a metal oxide (14), where the metal oxide is formed over a semiconductor substrate (12). A predetermined critical dimension of the metal layer is determined. A first etch is performed to etch the metal layer down to the metal oxide and form footings (26) at the sidewalls of the metal layer. A second etch to remove the footings to target a predetermined critical dimension, wherein the second etch is selective to the metal oxide. In one embodiment, a conductive layer (22) is formed over the metal layer. The bulk of the conductive layer may be etched leaving a portion in contact with the metal layer. Next, the portion left in contact with the metal layer may be etched using chemistry selective to the metal layer.
摘要翻译：在金属氧化物（14）上形成金属层（24），其中在半导体衬底（12）上形成金属氧化物。确定金属层的预定临界尺寸。执行第一蚀刻以将金属层向下蚀刻到金属氧化物并在金属层的侧壁处形成基脚（26）。用于移除基脚以靶向预定临界尺寸的第二蚀刻，其中第二蚀刻对金属氧化物是选择性的。在一个实施例中，在金属层上形成导电层（22）。可以蚀刻导电层的主体，留下与金属层接触的部分。接下来，可以使用化学选择性地蚀刻与金属层接触的部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式