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1. 发明申请

WO2012106332A1 METHOD OF WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY 审中-公开
标题翻译：写入旋转磁力随机存取存储器的方法
公开(公告)号：WO2012106332A1
公开(公告)日：2012-08-09
申请号：PCT/US2012/023316
申请日：2012-01-31
申请人： EVERSPIN TECHNOLOGIES, INC. , ALAM, Syed M. , ANDRE, Thomas , CROFT, Matthew R. , SUBRAMANIAN, Chitra , LIN, Halbert
发明人： ALAM, Syed M. , ANDRE, Thomas , CROFT, Matthew R. , SUBRAMANIAN, Chitra , LIN, Halbert
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G06F11/1048 , G06F11/1076 , G11C11/00 , G11C11/16 , G11C11/1673 , G11C11/1693 , G11C2013/0076 , G11C2029/0411
摘要： A method includes destructively reading bits of a spin torque magnetic random access memory and immediately writing back the original or inverted values. A detection of the majority state of the write back bits and a conditional inversion of write back bits are employed to reduce the number of write back pulses. A subsequent write command received within a specified time or before an original write operation is commenced will cause a portion of the write back pulses or the original write operation pulses to abort. Write pulses during subsequent write operations will follow the conditional inversion determined for the write back bits during destructive read.
摘要翻译：一种方法包括破坏性地读取自旋扭矩磁随机存取存储器的位并立即写回原始值或反相值。采用回写位的多数状态的检测和回写位的条件反转来减少回写脉冲的数量。在指定时间内或在原始写入操作开始之前接收到的后续写入命令将导致回写脉冲的一部分或原始写入操作脉冲中止。在后续写入操作期间的写入脉冲将遵循在破坏性读取期间为回写位确定的条件反演。

2. 发明申请

WO2012106358A1 METHOD OF READING AND WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY WITH ERROR CORRECTING CODE 审中-公开
标题翻译：读取和写入具有错误校正代码的旋转扭矩随机存取存储器的方法
公开(公告)号：WO2012106358A1
公开(公告)日：2012-08-09
申请号：PCT/US2012/023364
申请日：2012-01-31
申请人： EVERSPIN TECHNOLOGIES, INC. , ALAM, Syed M. , ANDRE, Thomas , CROFT, Matthew R.
发明人： ALAM, Syed M. , ANDRE, Thomas , CROFT, Matthew R.
IPC分类号： G06F11/00
CPC分类号： G06F11/1076 , G06F11/1012 , G06F11/1048 , G11C11/1673 , G11C11/1675 , H03M13/2906
摘要： A method includes destructively reading bits of a spin torque magnetic random access memory, using error correcting code (ECC) for error correction, and storing inverted or non-inverted data in data-store latches. When a subsequent write operation changes the state of data-store latches, parity calculation and majority detection of the bits are initiated. A majority bit detection and potential inversion of write data minimizes the number of write current pulses. A subsequent write operation received within a specified time or before an original write operation is commenced will cause the majority detection operation to abort.
摘要翻译：一种方法包括使用用于纠错的纠错码（ECC）和将反相或非反相数据存储在数据存储锁存器中来自动读取自旋扭矩磁随机存取存储器的位。当随后的写入操作改变数据存储锁存器的状态时，启动奇偶校验计算和多数位的检测。写入数据的多数位检测和潜在反转使写入电流脉冲的数量最小化。在指定时间内或原始写入操作开始之前接收到的后续写入操作将导致多数检测操作中止。

3. 发明申请

WO2015009331A1 MEMORY DEVICE WITH PAGE EMULATION MODE 审中-公开
标题翻译：具有页面模拟模式的存储器件
公开(公告)号：WO2015009331A1
公开(公告)日：2015-01-22
申请号：PCT/US2014/011634
申请日：2014-01-15
申请人： ALAM, Syed M. , ANDRE, Thomas , EVERSPIN TECHNOLOGIES, INC.
发明人： ALAM, Syed M. , ANDRE, Thomas
IPC分类号： G06F12/00 , G06F12/10
CPC分类号： G06F11/1096 , G06F11/1064 , G06F12/0882 , G06F2211/109 , G06F2212/652 , G11C14/0036
摘要： In some examples, a memory device is configured to load multiple pages of an internal page size into a cache in response to receiving an activate command and to write multiple pages of the internal page size into a memory array in response to receiving a precharge command. In some implementations, the memory array is arranged to store multiple pages of the internal page size in a single physical row.
摘要翻译：在一些示例中，存储器设备被配置为响应于接收到激活命令而将内部页面大小的页面加载到高速缓存中，并且响应于接收到预充电命令而将内部页面大小的多页写入存储器阵列。在一些实现中，存储器阵列被布置成在单个物理行中存储内部页面大小的多个页面。

4. 发明申请

WO2014124271A1 TAMPER DETECTION AND RESPONSE IN A MEMORY DEVICE 审中-公开
标题翻译：在记忆体设备中的篡改检测和响应
公开(公告)号：WO2014124271A1
公开(公告)日：2014-08-14
申请号：PCT/US2014/015319
申请日：2014-02-07
申请人： SUBRAMANIAN, Chitra K. , LIN, Halbert S. , ALAM, Syed M. , ANDRE, Thomas , EVERSPIN TECHNOLOGIES, INC.
发明人： SUBRAMANIAN, Chitra K. , LIN, Halbert S. , ALAM, Syed M. , ANDRE, Thomas
IPC分类号： G06F11/00
CPC分类号： G06F21/79 , G06F21/60 , G11C7/14 , G11C7/24 , G11C11/1659 , G11C11/1673 , G11C11/1695 , G11C13/0002 , G11C13/004 , G11C13/0059 , G11C13/0069 , G11C2013/0054 , G11C2013/0073
摘要： A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements.
摘要翻译：用于检测针对存储器件的篡改尝试的技术包括将多个检测存储器单元中的每一个设置为初始预定状态，其中多个检测存储器单元的相应部分被包括在每个数据存储单元阵列中存储设备。存储器装置上的多个对应的参考位永久地存储表示每个检测存储器元件的初始预定状态的信息。

5. 发明申请

WO2014058994A2 MEMORY DEVICE WITH TIMING OVERLAP MODE 审中-公开
标题翻译：具有时序重叠模式的存储器件
公开(公告)号：WO2014058994A2
公开(公告)日：2014-04-17
申请号：PCT/US2013/064088
申请日：2013-10-09
申请人： ANDRE, Thomas , ALAM, Syed M. , LIN, Halbert S. , EVERSPIN TECHNOLOGIES, INC.
发明人： ANDRE, Thomas , ALAM, Syed M. , LIN, Halbert S.
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G06F12/0802 , G06F2212/222 , G11C7/00 , G11C7/1042 , G11C7/12 , G11C7/22 , G11C11/1673 , G11C11/1693 , G11C11/4076
摘要： In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.
摘要翻译：在一些示例中，存储器设备被配置为接收预充电命令和激活命令。响应于接收到所述预充电命令，响应于接收到所述激活命令，所述存储器装置执行与所述预充电命令相关的第一系列事件和与所述激活命令相关的第二系列事件。存储器件延迟第二系列事件的开始直到第一系列事件完成。

6. 发明申请

WO2013173538A3 CONTROLLING MRAM CELL BIAS VOLTAGES 审中-公开
公开(公告)号：WO2013173538A3
公开(公告)日：2013-11-21
申请号：PCT/US2013/041272
申请日：2013-05-16
申请人： GOGL, Dietmar , ALAM, Syed M. , ANDRE, Thomas , EVERSPIN TECHNOLOGIES, INC.
发明人： GOGL, Dietmar , ALAM, Syed M. , ANDRE, Thomas
IPC分类号： G11C11/15 , G11C11/16 , G11C11/40
摘要： A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device + transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.

7. 发明申请

WO2012166910A1 MRAM FIELD DISTURB DETECTION AND RECOVERY 审中-公开
标题翻译： MRAM场干扰检测和恢复
公开(公告)号：WO2012166910A1
公开(公告)日：2012-12-06
申请号：PCT/US2012/040196
申请日：2012-05-31
申请人： EVERSPIN TECHNOLOGIES, INC. , ANDRE, Thomas , ALAM, Syed M. , ENGEL, Bradley , BUTCHER, Brian
发明人： ANDRE, Thomas , ALAM, Syed M. , ENGEL, Bradley , BUTCHER, Brian
IPC分类号： G06F11/00
CPC分类号： G06F11/1048 , G11C29/44 , H03M13/11
摘要： A method and memory device is provided for reading data from an ECC word of a plurality of reference bits associated with a plurality of memory device bits and determining if a double bit error in the ECC word exists. The ECC word may be first toggled twice and the reference bits reset upon detecting the double bit error.
摘要翻译：提供一种方法和存储装置，用于从与多个存储器件位相关联的多个参考位的ECC字中读取数据，并确定是否存在ECC字中的双位错误。 ECC字可以首先切换两次，并且在检测到双位错误时参考位复位。

8. 发明申请

WO2012083211A1 MEMORY CONTROLLER AND METHOD FOR INTERLEAVING DRAM AND MRAM ACCESSES 审中-公开
标题翻译：用于交互DRAM和MRAM访问的存储器控制器和方法
公开(公告)号：WO2012083211A1
公开(公告)日：2012-06-21
申请号：PCT/US2011/065571
申请日：2011-12-16
申请人： EVERSPIN TECHNOLOGIES, INC. , ALAM, Syed M. , ANDRE, Thomas , GOGL, Dietmar
发明人： ALAM, Syed M. , ANDRE, Thomas , GOGL, Dietmar
IPC分类号： G11C16/04
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0685 , G06F12/0246 , G06F12/0638 , G06F13/1694 , G06F2212/205 , G06F2212/7201 , G11C7/1042 , G11C7/1072 , G11C8/04 , G11C11/005 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C14/0036
摘要： A memory controller and method for interleaving volatile and non-volatile memory different latencies and page sizes are described wherein a single DDR3 memory controller communicates with a number of memory modules comprising of at least non-volatile memory, e, g. spin torque magnetic random access memory, integrated in a different Rank or Channel with a volatile memory, e.g., dynamic random access memory (DRAM).
摘要翻译：描述了用于交错易失性和非易失性存储器的存储器控制器和方法，其不同的延迟和页面大小，其中单个DDR3存储器控制器与包括至少非易失性存储器（即g）的多个存储器模块进行通信。旋转扭矩磁随机存取存储器，其集成在具有易失性存储器的不同等级或通道中，例如动态随机存取存储器（DRAM）。

9. 发明申请

WO2013169593A2 SELF REFERENCING SENSE AMPLIFIER FOR SPIN TORQUE MRAM 审中-公开
标题翻译：自适应感应放大器用于旋转扭矩MRAM
公开(公告)号：WO2013169593A2
公开(公告)日：2013-11-14
申请号：PCT/US2013/039466
申请日：2013-05-03
申请人： SUBRAMANIAN, Chitra , ALAM, Syed M. , EVERSPIN TECHNOLOGIES, INC.
发明人： SUBRAMANIAN, Chitra , ALAM, Syed M.
IPC分类号： G11C11/16
CPC分类号： G11C11/1673
摘要： Circuitry and a method provide self-referenced sensing of a resistive memory cell by using its characteristic of resistance variation with applied voltage in one state versus a relatively constant resistance regardless of the applied voltage in its opposite state. Based on an initial bias state with equalized resistances, a current comparison at a second bias state between a mock bit line and a bit line is used to determine the state of the memory cell, since a significant difference in current implies that the memory cell state has a significant voltage coefficient of resistance. An offset current applied to the mock bit line optionally may be used to provide symmetry and greater sensing margin.
摘要翻译：电路和方法通过使用其在一个状态下的施加电压与相对恒定电阻的电阻变化的特性来提供电阻性存储单元的自参考感测，而不管其相反状态下的施加电压如何。基于具有均衡电阻的初始偏置状态，使用模拟位线和位线之间的第二偏置状态下的电流比较来确定存储器单元的状态，因为电流的显着差异意味着存储单元状态具有显着的电阻系数。施加到模拟位线的偏移电流可选地可以用于提供对称性和更大的感测余量。

10. 发明申请

WO2012125681A2 METHOD TO MITIGATE THROUGH-SILICON VIA-INDUCED SUBSTRATE NOISE 审中-公开
标题翻译：通过硅氧化膜消除基底噪声的方法
公开(公告)号：WO2012125681A2
公开(公告)日：2012-09-20
申请号：PCT/US2012/029003
申请日：2012-03-14
申请人： TUFTS UNIVERSITY , KHAN, Nauman H. , HASSOUN, Soha , ALAM, Syed M.
发明人： KHAN, Nauman H. , HASSOUN, Soha , ALAM, Syed M.
IPC分类号： H01L21/28 , H01L21/768
CPC分类号： H01L21/768 , H01L23/481 , H01L23/552 , H01L23/585 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor manufacture includes a first semiconductor including a substrate die having a first surface and having a second surface upon which integrated circuitry is disposed; a second semiconductor die; a through-silicon via (TSV) extending through the first semiconductor die and electrically connected to the second semiconductor die; and at least one ground plug including an electrically conductive material, positioned proximally to the TSV and extending into the substrate of the first semiconductor die from one of the first surface or the second surface.
摘要翻译：半导体制造包括：第一半导体，包括具有第一表面并具有第二表面的衬底管芯，集成电路设置在第二表面上; 第二半导体管芯; 穿过所述第一半导体管芯并且电连接到所述第二半导体管芯的穿硅通孔（TSV）; 以及包括导电材料的至少一个接地插头，位于TSV的近侧并从第一表面或第二表面之一延伸到第一半导体管芯的衬底中。

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