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1. 发明申请

WO2012170160A1 METAL OXIDE TFT WITH IMPROVED SOURCE/DRAIN CONTACTS 审中-公开
标题翻译：具有改进源/漏联系的金属氧化物薄膜
公开(公告)号：WO2012170160A1
公开(公告)日：2012-12-13
申请号：PCT/US2012/038075
申请日：2012-05-16
申请人： CBRITE INC. , SHIEH, Chan-long , YU, Gang , FOONG, Fatt
发明人： SHIEH, Chan-long , YU, Gang , FOONG, Fatt
IPC分类号： H01L21/36 , H01L21/44 , H01L21/465
CPC分类号： H01L29/7869 , H01L21/428 , H01L29/45 , H01L29/66969 , H01L29/78606
摘要： A method of forming ohmic source/drain contacts in a metal oxide semiconductor thin film transistor includes providing a gate, a gate dielectric, a high carrier concentration metal oxide semiconductor active layer with a band gap and spaced apart source/drain metal contacts in a thin film transistor configuration. The spaced apart source/drain metal contacts define a channel region in the active layer. An oxidizing ambient is provided adjacent the channel region and the gate and the channel region are heated in the oxidizing ambient to reduce the carrier concentration in the channel area. Alternatively or in addition each of the source/drain contacts includes a very thin layer of low work function metal positioned on the metal oxide semiconductor active layer and a barrier layer of high work function metal is positioned on the low work function metal.
摘要翻译：在金属氧化物半导体薄膜晶体管中形成欧姆源极/漏极接触的方法包括：提供栅极，栅极电介质，具有带隙的高载流子浓度金属氧化物半导体有源层和间隔开的薄/弱金属氧化物半导体有源层薄膜晶体管配置。间隔开的源极/漏极金属触点限定有源层中的沟道区。在沟道区域附近提供氧化环境，并且在氧化环境中加热栅极和沟道区域以降低沟道区域中的载流子浓度。或者或另外每个源极/漏极触点包括位于金属氧化物半导体有源层上的非常薄的低功函数金属层，并且高功函数金属的阻挡层位于低功函数金属上。

2. 发明申请

WO2011022144A1 AMOLED WITH CASCADED OLED STRUCTURES 审中-公开
标题翻译：嵌入式OLED结构
公开(公告)号：WO2011022144A1
公开(公告)日：2011-02-24
申请号：PCT/US2010/042385
申请日：2010-07-19
申请人： CBRITE INC. , SHIEH, Chan-long , YU, Gang
发明人： SHIEH, Chan-long , YU, Gang
IPC分类号： H01L51/50
CPC分类号： H01L27/3244 , H01L27/3204 , H01L27/3246
摘要： An active matrix organic light emitting display includes a plurality of pixels with each pixel including at least one organic light emitting diode circuit. Each diode circuit producing a predetermined amount of light Im in response to power W applied to the circuit and including n organic light emitting diodes cascaded in series so as to increase voltage dropped across the cascaded diodes by the factor of n, where n is an integer greater than one. Each diode of the n organic light emitting diodes produces approximately 1/n of the predetermined amount of light Im so as to reduce current flowing in the diodes by 1/n. The organic light emitting diode circuit of each pixel includes a thin film transistor current driver with the cascaded diodes connected in the source/drain circuit so the current driver provides the current flowing in the diodes.
摘要翻译：有源矩阵有机发光显示器包括多个像素，每个像素包括至少一个有机发光二极管电路。每个二极管电路响应于施加到电路的功率W产生预定量的光Im，并且包括串联级联的n个有机发光二极管，以便增加跨越级联二极管的电压以n为因子，其中n是整数大于一。 n个有机发光二极管的每个二极管产生大约1 / n个预定量的光Im，以便将在二极管中流动的电流减少1 / n。每个像素的有机发光二极管电路包括薄膜晶体管电流驱动器，其中级联二极管连接在源极/漏极电路中，因此电流驱动器提供流过二极管的电流。

3. 发明申请

WO2015073502A1 MOTFT WITH UN-PATTERNED ETCH-STOP 审中-公开
标题翻译：具有不间断蚀刻的MOTFT
公开(公告)号：WO2015073502A1
公开(公告)日：2015-05-21
申请号：PCT/US2014/065161
申请日：2014-11-12
申请人： CBRITE INC.
发明人： YU, Gang , SHIEH, Chan-Long , MUSOLF, Juergen , FOONG, Fatt , XIAO, Tian
IPC分类号： H01L21/36 , H01L21/38 , H01L29/86
CPC分类号： H01L27/1203 , H01L21/02565 , H01L21/02664 , H01L29/24 , H01L29/66969 , H01L29/7869
摘要： A method of fabricating a high mobility semiconductor metal oxide thin film transistor including the steps of depositing a layer of semiconductor metal oxide material, depositing a blanket layer of etch-stop material on the layer of MO material, and patterning a layer of source/drain metal on the blanket layer of etch-stop material including etching the layer of source/drain metal into source/drain terminals positioned to define a channel area in the semiconductor metal oxide layer. The etch-stop material being electrically conductive in a direction perpendicular to the plane of the blanket layer at least under the source/drain terminals to provide electrical contact between each of the source/drain terminals and the layer of semiconductor metal oxide material. The etch-stop material is also chemical robust to protect the layer of semiconductor metal oxide channel material during the etching process.
摘要翻译：一种制造高迁移率半导体金属氧化物薄膜晶体管的方法，包括以下步骤：沉积半导体金属氧化物材料层，在MO材料层上沉积蚀刻停止材料的覆盖层，以及图案化源/漏层包括将源极/漏极金属层蚀刻成定位成限定半导体金属氧化物层中的沟道区域的源极/漏极端子的蚀刻停止材料的覆盖层上的金属。蚀刻停止材料至少在源极/漏极端子之下在垂直于覆盖层的平面的方向上导电，以提供每个源极/漏极端子和半导体金属氧化物材料层之间的电接触。蚀刻停止材料也是化学稳固的，以在蚀刻工艺期间保护半导体金属氧化物沟道材料层。

4. 发明申请

WO2014189681A2 STABLE HIGH MOBILITY MOTFT AND FABRICATION AT LOW TEMPERATURE 审中-公开
标题翻译：稳定的高移动性和低温制造
公开(公告)号：WO2014189681A2
公开(公告)日：2014-11-27
申请号：PCT/US2014/037191
申请日：2014-05-07
申请人： CBRITE INC.
发明人： SHIEH, Chan-long , YU, Gang , FOONG, Fatt , MUSOLF, Juergen
IPC分类号： H01L21/465
CPC分类号： H01L29/66969 , H01L21/02063 , H01L21/02565 , H01L21/02631 , H01L21/76805 , H01L21/76814 , H01L21/76895 , H01L27/1225 , H01L29/247 , H01L29/42384 , H01L29/517 , H01L29/518 , H01L29/66742 , H01L29/78603 , H01L29/78606 , H01L29/78618 , H01L29/78693 , H01L29/78696 , H01L2021/775
摘要： A method of fabricating a stable high mobility amorphous MOTFT includes a step of providing a substrate with a gate formed thereon and a gate dielectric layer positioned over the gate. A carrier transport structure is deposited by sputtering on the gate dielectric layer. The carrier transport structure includes a layer of amorphous high mobility metal oxide adjacent the gate dielectric and a relatively inert protective layer of material deposited on the layer of amorphous high mobility metal oxide both deposited without oxygen and in situ . The layer of amorphous metal oxide has a mobility above 40 cm 2 /Vs and a carrier concentration in a range of approximately 10 18 cm -3 to approximately 5xl0 19 cm -3 . Source/drain contacts are positioned on the protective layer and in electrical contact therewith.
摘要翻译：制造稳定的高迁移率无定形MOTFT的方法包括提供其上形成有栅极的基板和位于栅极上方的栅介质层的步骤。通过溅射将载流子传输结构沉积在栅极介电层上。载流子传输结构包括邻近栅极电介质的非晶高迁移率金属氧化物层，以及沉积在无氧和原位沉积的无定形高迁移率金属氧化物层上的相对惰性的材料保护层。无定形金属氧化物层的迁移率高于40cm 2 / Vs，载流子浓度在约1018cm-3至约5×1019cm-3的范围内。源极/漏极触点位于保护层上并与其电接触。

5. 发明申请

WO2018075404A1 METHOD OF RECOVERY OF MOTFT BACKPLANE AFTER A-SI PHOTODIODE FABRICATION 审中-公开
标题翻译：在A-Si光电二极管制造之后恢复MOTFT背板的方法
公开(公告)号：WO2018075404A1
公开(公告)日：2018-04-26
申请号：PCT/US2017/056792
申请日：2017-10-16
申请人： CBRITE INC.
发明人： SHIEH, Chan-Long , YU, Gang , WANG, Guangming
IPC分类号： H01L27/146
CPC分类号： H01L27/14616 , H01L27/1463 , H01L27/14643 , H01L27/14658 , H01L27/14689 , H01L27/1469 , H01L27/14692
摘要： A method of fabricating a structure including a high mobility backplane and a-Si photodiode imager includes forming a matrix of metal oxide thin film transistors on the surface of a rigid support member, depositing a planarizing layer on the matrix of transistors that is either porous or permissive/diffusive to oxygen at temperatures below approximately 200°C, and fabricating a matrix of passivated a-Si photodiodes over the matrix of transistors and electrically connected one each photodiode to each of the transistors. A continuous path is provided through the planarizing layer from the exterior of the structure to each of the transistors and the structure is annealed at a temperature below 200°C in an oxygen ambient to move oxygen from the oxygen ambient to an active layer of each of the transistors and repair loss of oxygen damage to the transistors caused by the fabrication of the passivated a-Si photodiodes.
摘要翻译：一种制造包括高迁移率背板和a-Si光电二极管成像器的结构的方法包括：在刚性支撑构件的表面上形成金属氧化物薄膜晶体管的矩阵;在所述刚性支撑构件的表面上沉积平坦化层在低于大约200℃的温度下多孔或者允许/扩散到氧的晶体管矩阵，以及在晶体管矩阵上制造钝化a-Si光电二极管矩阵并且将每个光电二极管与每个晶体管电连接。提供穿过平面化层从结构外部到每个晶体管的连续路径，并且结构在低于200℃的温度下在氧气环境中退火，以将氧气从氧气环境移动到每个晶体管的活性层晶体管和修复由于钝化a-Si光电二极管的制造而导致的晶体管的氧损伤的损失。

6. 发明申请

WO2016176216A1 MOTFT AND ARRAY CIRCUIT FOR CHEMICAL/BIOCHEMICAL APPLICATIONS 审中-公开
标题翻译：化学/生物化学应用的MOTFT和阵列电路
公开(公告)号：WO2016176216A1
公开(公告)日：2016-11-03
申请号：PCT/US2016/029384
申请日：2016-04-26
申请人： CBRITE INC.
发明人： SHIEH, Chan-Long , YU, Gang , ACKLEY, Donlad
IPC分类号： G01N33/487 , G01N27/327
CPC分类号： H01L29/7869 , G01N27/4148 , H01L27/1225 , H01L29/43
摘要： Electro-chemical manipulation and charge sensing apparatus includes a chemical/biochemical testing pad positioned on a dielectric substrate, a sensing circuit coupled to the testing pad, the sensing circuit including at least one MOTFT device, and a manipulation and control circuit coupled to the testing pad, the manipulation and control circuit including at least one MOTFT device. The electro-chemical manipulation and charge sensing apparatus can include a plurality of chemical/biochemical testing pads distributed in a matrix formation of rows and columns and positioned on a dielectric substrate.
摘要翻译：电化学操作和电荷感测装置包括位于电介质基底上的化学/生化测试垫，耦合到测试垫的感测电路，感测电路包括至少一个MOTFT装置，以及耦合到测试的操纵和控制电路所述操纵和控制电路包括至少一个MOTFT装置。电化学操作和电荷感测装置可以包括分布在行和列的矩阵形式中并定位在电介质基底上的多个化学/生化测试垫。

7. 发明申请

WO2016014345A2 TWO-TERMINAL ELECTRONIC DEVICES AND THEIR METHODS OF FABRICATION 审中-公开
标题翻译：双端电子器件及其制造方法
公开(公告)号：WO2016014345A2
公开(公告)日：2016-01-28
申请号：PCT/US2015/040815
申请日：2015-07-16
申请人： CBRITE INC.
发明人： YU, Gang , SHIEH, Chan-Tong , CHEN, Zhao
IPC分类号： H01L29/861
CPC分类号： H01L51/4273 , G02F1/1365 , H01L27/308 , H01L51/0081 , H01L51/0085 , H01L51/0587 , H01L2251/308 , Y02E10/549
摘要： Two-terminal electronic devices, such as photodetectors, photovoltaic devices and electroluminescent devices, are provided. The devices include a first electrode residing on a substrate, wherein the first electrode comprises a layer of metal; an I-layer comprising an inorganic insulating or broad band semiconducting material residing on top of the first electrode, and aligned with the first electrode, wherein the inorganic insulating or broad band semiconducting material is a compound of the metal of the first electrode; a semiconductor layer, preferably comprising a p-type semiconductor, residing over the I-layer; and a second electrode residing over the semiconductor layer, the electrode comprising a layer of a conductive material. The band gap of the material of the semiconductor layer, is preferably smaller than the band gap of the I-layer material. The band gap of the material of the I-layer is preferably greater than 2.5 eV.
摘要翻译：提供诸如光电检测器，光伏器件和电致发光器件的两端电子器件。所述器件包括位于衬底上的第一电极，其中所述第一电极包括金属层; I层，其包含位于所述第一电极顶部并与所述第一电极对准的无机绝缘或宽带半导体材料，其中所述无机绝缘或宽带半导体材料是所述第一电极的金属的化合物; 位于I层上的半导体层，优选包括p型半导体; 以及位于所述半导体层上方的第二电极，所述电极包括导电材料层。半导体层的材料的带隙优选小于I层材料的带隙。 I层的材料的带隙优选大于2.5eV。

8. 发明申请

WO2015142525A1 FLEXIBLE TFT BACKPANEL BY GLASS SUBSTRATE REMOVAL 审中-公开
标题翻译：透明玻璃底板去除柔性TFT背板
公开(公告)号：WO2015142525A1
公开(公告)日：2015-09-24
申请号：PCT/US2015/018807
申请日：2015-03-04
申请人： CBRITE INC.
发明人： YU, Gang , SHIEH, Chan-Long , WANG, Guangming , FOONG, Fatt
IPC分类号： H01L21/70 , H01L27/32 , H01L51/52
CPC分类号： H01L27/3244 , H01L27/1259 , H01L27/322 , H01L29/78603 , H01L51/003 , H01L51/0097 , H01L51/5246 , H01L51/56 , H01L2227/323 , H01L2251/5338
摘要： A process of fabricating a flexible TFT back-panel on a glass support includes a step of providing a flat glass support member sufficiently thick to prevent bending during the processing. A layer of etch stop material is positioned on the upper surface of the glass support member and an insulating buffer layer is positioned on the layer of etch stop material. A TFT back-panel is positioned on the insulating buffer layer and a flexible plastic carrier is affixed to the TFT back-panel. The glass support member is etched away, whereby a flexible TFT back-panel is provided. The TFT back-panel can include a matrix of either OLED cells or LCD cells.
摘要翻译：在玻璃支架上制造柔性TFT背板的工艺包括提供足够厚的平板玻璃支撑件以防止加工过程中弯曲的步骤。一层蚀刻停止材料定位在玻璃支撑构件的上表面上，并且绝缘缓冲层位于蚀刻停止材料层上。 TFT背板位于绝缘缓冲层上，柔性塑料载体固定在TFT后面板上。蚀刻玻璃支撑构件，由此提供柔性TFT背面板。 TFT背面板可以包括OLED单元或LCD单元的矩阵。

9. 发明申请

WO2015069710A1 SELF-ALIGNED METAL OXIDE TFT 审中-公开
标题翻译：自对准金属氧化物膜
公开(公告)号：WO2015069710A1
公开(公告)日：2015-05-14
申请号：PCT/US2014/064045
申请日：2014-11-05
申请人： CBRITE INC.
发明人： SHIEH, Chan-Long , YU, Gang , FOONG, Fatt
IPC分类号： H01L29/786 , H01L27/32 , H01L21/027
CPC分类号： H01L29/78696 , H01L21/02554 , H01L21/02565 , H01L21/707 , H01L27/1225 , H01L27/124 , H01L27/1288 , H01L29/66969 , H01L29/78606 , H01L29/7869
摘要： A method of fabricating MO TFTs includes positioning opaque gate metal on a transparent substrate to define a gate area. Depositing gate dielectric material overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material thereon. Depositing etch stop material on the semiconductor material. Positioning photoresist defining an isolation area in the semiconductor material, the etch stop material and the photoresist being selectively removable. Exposing the photoresist from the rear surface of the substrate and removing exposed portions to leave the etch stop material uncovered except for a portion overlying and aligned with the gate metal. Etching uncovered portions of the semiconductor material to isolate the TFT. Using the photoresist, selectively etching the etch stop layer to leave a portion overlying and aligned with the gate metal and defining a channel area in the semiconductor material. Depositing and patterning conductive material to form source and drain areas.
摘要翻译：制造MO TFT的方法包括将不透明栅极金属定位在透明基板上以限定栅极区域。覆盖栅极金属和周围区域的沉积栅介质材料，以及在其上沉积金属氧化物半导体材料。在半导体材料上沉积蚀刻停止材料。在半导体材料中定义隔离区域的定位光刻胶，蚀刻停止材料和光致抗蚀剂被选择性地移除。从基板的后表面露出光致抗蚀剂，除去暴露的部分以使蚀刻停止材料除外覆盖并与栅极金属对准的部分。蚀刻半导体材料的未覆盖部分以隔离TFT。使用光致抗蚀剂，选择性地蚀刻蚀刻停止层以留下覆盖并与栅极金属对准的部分并且限定半导体材料中的沟道区域。沉积和图案化导电材料以形成源极和漏极区域。

10. 发明申请

WO2013181166A1 MASK LEVEL REDUCTION FOR MOFET 审中-公开
标题翻译：屏蔽层减少MOFET
公开(公告)号：WO2013181166A1
公开(公告)日：2013-12-05
申请号：PCT/US2013/042926
申请日：2013-05-28
申请人： CBRITE INC.
发明人： SHIEH, Chan-long , YU, Gang , FOONG, Fatt , LEE, Liu-chung
IPC分类号： G02F1/1343
CPC分类号： G02F1/134363 , G02F1/13439 , G02F1/1368 , G02F2001/134372 , G02F2001/136231 , G02F2001/136236 , H01L27/1225 , H01L27/1288
摘要： A method of fabricating a TFT and IPS with reduced masking operations includes a substrate, a gate, a layer of gate dielectric on the gate and surrounding substrate surface and a semiconducting metal oxide on the gate dielectric. A channel protection layer overlies the gate to define a channel area in the semiconducting metal oxide. A S/D metal layer is patterned on the channel protection layer and a portion of the exposed semiconducting metal oxide to define an IPS area. An organic dielectric material is patterned on the S/D terminals and at an opposed side of the IPS area. The S/D metal is etched to expose the semiconducting metal oxide defining a first IPS electrode. A passivation layer covers the first electrode and a layer of transparent conductive material is patterned on the passivation layer to define a second IPS electrode overlying the first electrode.
摘要翻译：制造具有减小的掩模操作的TFT和IPS的方法包括在栅极和周围的衬底表面上的衬底，栅极，栅极电介质层和栅极电介质上的半导体金属氧化物。沟道保护层覆盖栅极以限定半导体金属氧化物中的沟道区。在沟道保护层和暴露的半导体金属氧化物的一部分上形成S / D金属层以限定IPS区域。在S / D端子和IPS区域的相对侧上构图有机电介质材料。蚀刻S / D金属以暴露限定第一IPS电极的半导体金属氧化物。钝化层覆盖第一电极，并且在钝化层上图案化透明导电材料层，以限定覆盖第一电极的第二IPS电极。

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