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1. 发明申请

WO2011080770A1 USE OF DECREASING VERIFY CURRENTS IN A SET PROGRAMMING CYCLE OF A PHASE CHANGE MEMORY 审中-公开
标题翻译：在相位变化记忆的集合编程周期中使用验证电流的使用
公开(公告)号：WO2011080770A1
公开(公告)日：2011-07-07
申请号：PCT/IT2009/000584
申请日：2009-12-29
申请人： BEDESCHI, Ferdinando
发明人： BEDESCHI, Ferdinando
IPC分类号： G11C16/02
CPC分类号： G11C13/0064 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2013/0092
摘要： Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory, with the use of verify reference current values which decreas in step with the individual bias pulses used to set the phase charge memory to a low resistane state.
摘要翻译：本文公开的主题涉及存储器件，更具体地说，涉及使用验证参考电流值来写入相变存储器的性能，所述验证参考电流值与用于将相位电荷存储器设置为低电阻率的各个偏置脉冲相反地减小州。

2. 发明申请

WO2011080784A1 METHODS FOR A PHASE-CHANGE MEMORY ARRAY 审中-公开
标题翻译：相变记忆阵列的方法
公开(公告)号：WO2011080784A1
公开(公告)日：2011-07-07
申请号：PCT/IT2009/000603
申请日：2009-12-31
申请人： BEDESCHI, Ferdinando , RESTA, Claudio , FERRARO, Marco
发明人： BEDESCHI, Ferdinando , RESTA, Claudio , FERRARO, Marco
IPC分类号： G11C13/02 , G11C16/02
CPC分类号： G06F3/0622 , G06F3/0643 , G06F3/0679 , G11C13/0004 , G11C13/004 , G11C13/0059 , G11C13/0069 , G11C13/0097 , G11C13/02 , H01L45/04 , H01L45/06
摘要： Methods of operating phase-change memory arrays are described. A method includes determining a pattern to be written to a phase-change memory array and executing, according to the pattern, two or more proper reset sequences on the phase-change memory array to write the pattern to the phase-change memory array. Another method includes executing a set sequence on a phase-change memory array and performing a proper read of the phase-change memory array to obtain a pattern derived from executing the set sequence.
摘要翻译：描述了操作相变存储器阵列的方法。一种方法包括确定要写入相变存储器阵列的图案，并根据该图案，在相变存储器阵列上执行两个或更多个适当的复位序列，以将该图案写入相变存储器阵列。另一种方法包括在相变存储器阵列上执行设置序列并执行相变存储器阵列的适当读取以获得从执行所述设置序列导出的模式。

3. 发明申请

WO2008012342A1 PHASE CHANGE MEMORY DEVICE 审中-公开
标题翻译：相变存储器件
公开(公告)号：WO2008012342A1
公开(公告)日：2008-01-31
申请号：PCT/EP2007/057706
申请日：2007-07-26
申请人： STMICROELECTRONICS S.R.L. , PELLIZZER, Fabio , BEZ, Roberto , BEDESCHI, Ferdinando , GASTALDI, Roberto
发明人： PELLIZZER, Fabio , BEZ, Roberto , BEDESCHI, Ferdinando , GASTALDI, Roberto
IPC分类号： H01L27/24 , G11C16/02
CPC分类号： G11C13/0004 , G11C11/56 , G11C11/5678 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2213/79 , H01L27/2427 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144
摘要： A phase change memory device with memory cells (2) formed by a phase change memory element (3) and a selection switch (4). A reference cell (2a) formed by an own phase change memory element (3) and an own selection switch (4) is associated to a group (7) of memory cells to be read. An electrical quantity of the group of memory cells is compared with an analogous electrical quantity of the reference cell, thereby compensating any drift in the properties of the memory cells.
摘要翻译：一种具有由相变存储元件（3）和选择开关（4）形成的存储单元（2）的相变存储器件。由自己的相变存储元件（3）和自己的选择开关（4）形成的参考单元（2a）与待读取的存储单元组（7）相关联。将该组存储器单元的电量与参考单元的类似电量进行比较，由此补偿存储单元的特性中的任何漂移。

4. 发明申请

WO2011080769A1 MIXED MODE PROGRAMMING FOR PHASE CHANGE MEMORY 审中-公开
标题翻译：用于相变存储器的混合模式编程
公开(公告)号：WO2011080769A1
公开(公告)日：2011-07-07
申请号：PCT/IT2009/000583
申请日：2009-12-29
申请人： BEDESCHI, Ferdinando
发明人： BEDESCHI, Ferdinando
IPC分类号： G11C16/02
CPC分类号： G11C13/0064 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2013/009 , G11C2013/0092 , G11C2213/72
摘要： Subject matter disclosed herein relates to a write method of a phase change memory that applies a voltage-regulated bias signal to a memory cell during initial programming steps, and then after verify, if necessary, subsequently shifts to applying a current-regulated bias signal to the memory cell.
摘要翻译：本文公开的主题涉及在初始编程步骤期间将电压调节偏置信号施加到存储单元的相变存储器的写入方法，然后在验证之后，如果需要，随后转移到施加电流调节偏置信号存储单元。

5. 发明申请

WO2010076834A1 RELIABLE SET OPERATION FOR PHASE-CHANGE MEMORY CELL 审中-公开
标题翻译：相变存储单元的可靠设置操作
公开(公告)号：WO2010076834A1
公开(公告)日：2010-07-08
申请号：PCT/IT2008/000823
申请日：2008-12-31
申请人： BEDESCHI, Ferdinando
发明人： BEDESCHI, Ferdinando
IPC分类号： G11C16/02
CPC分类号： G11C13/0009 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , G11C2013/0092
摘要： A Phase-Change Memory (PCM) device and a method of writing data to the PCM device are described. The PCM device includes a multi-phase data storage cell having at least a Set state and a Reset state that may be established using a heater configured to heat the data storage cell. A memory interface may be coupled with the heater configured to write data to the data storage cell, the data being represented by the Set or the Reset states. Iterative write Reset pulses are used to place the data storage cell in the Reset state corresponding to a read value that is less than a read threshold. A write Set pulse that is a predetermined function of the final write Reset pulse that led to reset verification is used to place the data storage cell in the Set state. The PCM device may include additional intermediate states that enable each data storage cell to store two or more bits of information. Other embodiments may be described and claimed.
摘要翻译：描述了相变存储器（PCM）装置和将数据写入PCM装置的方法。 PCM装置包括具有至少设置状态和复位状态的多相数据存储单元，该状态可以使用配置为加热数据存储单元的加热器来建立。存储器接口可以与被配置为将数据写入数据存储单元的加热器耦合，该数据由Set或Reset状态表示。迭代写复位脉冲用于将数据存储单元置于与读取值小于读取阈值的读取值对应的复位状态。作为导致复位验证的最终写入复位脉冲的预定功能的写入设置脉冲用于将数据存储单元置于置位状态。 PCM设备可以包括允许每个数据存储单元存储两个或更多个位的信息的附加中间状态。可以描述和要求保护其他实施例。

6. 发明申请

WO2011070599A1 APPARATUS AND METHOD FOR READING A PHASE-CHANGE MEMORY CELL 审中-公开
标题翻译：用于读取相变存储器单元的装置和方法
公开(公告)号：WO2011070599A1
公开(公告)日：2011-06-16
申请号：PCT/IT2009/000557
申请日：2009-12-10
申请人： BEDESCHI, Ferdinando
发明人： BEDESCHI, Ferdinando
IPC分类号： G11C16/02 , G11C13/02
CPC分类号： G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0054 , G11C2213/72
摘要： An apparatus and a method for reading a phase-change memory cell are described. A circuit includes a current ramp circuit. A current forcing module is coupled with the current ramp circuit. A Veb emulation circuit is coupled with the current forcing module by a voltage adder, the voltage adder to sum an output from the Veb emulation circuit and a high impedance voltage source. A method includes forcing a current ramp into both a bitline and a dummy bitline, the dummy bitline having a voltage. The method also includes tripping a comparator when the current ramp provides a storage voltage with a predefined value, the storage voltage associated with the phase-change memory cell, and the predefined value independent from a resistance value of the phase-change memory cell and added in series to the voltage of the dummy bitline.
摘要翻译：描述用于读取相变存储单元的装置和方法。电路包括电流斜坡电路。电流强制模块与电流斜坡电路耦合。 Veb仿真电路通过电压加法器与电流强制模块耦合，电压加法器将来自Veb仿真电路的输出和高阻抗电压源相加。一种方法包括将电流斜坡强制施加到位线和伪位线中，虚拟位线具有电压。该方法还包括当电流斜坡提供具有预定义值的存储电压时，跳闸比较器，与相变存储器单元相关联的存储电压以及独立于相变存储器单元的电阻值的预定值并且被添加与虚拟位线的电压串联。

7. 发明申请

WO2011067795A1 REFRESH ARCHITECTURE AND ALGORITHM FOR NON-VOLATILE MEMORIES 审中-公开
标题翻译：非易失性存储器的刷新架构和算法
公开(公告)号：WO2011067795A1
公开(公告)日：2011-06-09
申请号：PCT/IT2009/000541
申请日：2009-12-02
申请人： BEDESCHI, Ferdinando , GASTALDI Roberto
发明人： BEDESCHI, Ferdinando , GASTALDI Roberto
IPC分类号： G11C16/34
CPC分类号： G11C13/0033 , G06F11/1068 , G11C11/5678 , G11C13/0004 , G11C13/0038 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C14/009 , G11C16/3418 , G11C29/52
摘要： Methods and systems to refresh a non-volatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.
摘要翻译：刷新非易失性存储器件的方法和系统，例如相变存储器。在一个实施例中，作为系统状态的函数，存储器设备使用边缘读取参考电平或使用非余量读取参考电平对错误校正的存储器单元的第二刷新来执行存储器单元的第一刷新。

8. 发明申请

WO2011080768A1 MEMORY DEVICES COMPRISING PARTITIONS WITH PARTICULAR ECC ATTRIBUTES 审中-公开
标题翻译：包含具有特殊ECC特征的分段的存储器件
公开(公告)号：WO2011080768A1
公开(公告)日：2011-07-07
申请号：PCT/IT2009/000582
申请日：2009-12-29
申请人： BEDESCHI, Ferdinando
发明人： BEDESCHI, Ferdinando
IPC分类号： G11C8/12 , G06F12/02
CPC分类号： G06F11/1016 , G06F3/0604 , G06F3/0644 , G06F3/0673 , G06F11/1068 , G06F12/0223 , G11C8/12 , G11C29/42
摘要： Subject matter disclosed herein relates to memory management, and more particularly to partitioning a memory based on memory attributes.
摘要翻译：本文公开的主题涉及存储器管理，更具体地涉及基于存储器属性来划分存储器。

9. 发明申请

WO2008150693A1 BIASING A PHASE CHANGE MEMORY DEVICE 审中-公开
标题翻译：偏移相变存储器件
公开(公告)号：WO2008150693A1
公开(公告)日：2008-12-11
申请号：PCT/US2008/064197
申请日：2008-05-20
申请人： INTEL CORPORATION , BEDESCHI, Ferdinando , FACKENTHAL, Richard, E. , FANTINI, Andrea
发明人： BEDESCHI, Ferdinando , FACKENTHAL, Richard, E. , FANTINI, Andrea
IPC分类号： G11C13/00 , G11C11/4094
CPC分类号： G11C13/004 , G11C7/04 , G11C13/0004 , G11C13/0033 , G11C2013/0054 , G11C2213/79
摘要： A phase change memory device includes a plurality of cells connected to bitlines and including respective phase change memory elements and cell select devices and an addressing circuit for selectively addressing at least one bitline and one cell connected thereto. A reading column bias circuit supplies a bitline voltage to the addressed bitline and cell. The bitline voltage includes the sum of a safe voltage and a reference select device voltage, wherein the reference voltage is equal to a select device voltage on the select device when a cell current flowing through the phase change memory element and the cell select device is equal to a safe current. The safe voltage and the safe current are such that phase transition of the phase change memory element is prevented in any bias condition including a cell voltage lower than the safe voltage and in any bias condition including the cell current lower than the safe current.
摘要翻译：相变存储器件包括连接到位线并包括各自的相变存储器元件和单元选择器件的多个单元以及用于选择性地寻址至少一个位线和连接到其上的一个单元的寻址电路。读取列偏置电路向寻址的位线和单元提供位线电压。位线电压包括安全电压和参考选择器件电压的总和，其中当流过相变存储器元件和电池选择器件的电池电流相等时，参考电压等于选择器件上的选择器件电压到一个安全的电流。安全电压和安全电流使得在包括电池电压低于安全电压的任何偏压条件下以及包括电池电流低于安全电流的任何偏置条件下，防止相变存储元件的相变。

10. 发明申请

WO2008118757A1 PHASE CHANGE MEMORY WITH PROGRAM/VERIFY FUNCTION 审中-公开
标题翻译：具有程序/验证功能的相变存储器
公开(公告)号：WO2008118757A1
公开(公告)日：2008-10-02
申请号：PCT/US2008/057726
申请日：2008-03-20
申请人： INTEL CORPORATION , BEDESCHI, Ferdinando , FACKENTHAL, Richard E. , ZHANG, Ruili
发明人： BEDESCHI, Ferdinando , FACKENTHAL, Richard E. , ZHANG, Ruili
IPC分类号： G11C13/00 , H01L27/105
CPC分类号： G11C13/0064 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0054
摘要： A phase change memory includes a plurality of cells for storing data in the form of respective resistance levels, addressing circuits for addressing cells to be programmed, and the resistance levels are determined from comparison of cell currents of addressed cells with a reference current. A reference generator provides the sense amplifier with the reference current. The reference generator is provided with a reference select circuit to select the reference current from a plurality of verify currents based on program data to be stored in the cell.
摘要翻译：相变存储器包括用于存储各自电阻电平形式的数据的多个单元，用于寻址待编程单元的寻址电路，并且通过将寻址的单元与参考电流的单元电流进行比较来确定电阻水平。参考发生器为读出放大器提供参考电流。参考发生器具有参考选择电路，以根据要存储在单元中的程序数据从多个验证电流中选择参考电流。

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