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1. 发明申请

WO2006078744A3 METHOD AND SYSTEM FOR MANAGING A SUSPEND REQUEST IN A FLASH MEMORY 审中-公开
标题翻译：用于管理闪存中的暂停请求的方法和系统
公开(公告)号：WO2006078744A3
公开(公告)日：2009-04-16
申请号：PCT/US2006001776
申请日：2006-01-19
申请人： ATMEL CORP , SURICO STEFANO , BARTOLI SIMONE , MARZIANI MONICA , FIGINI LUCA
发明人： SURICO STEFANO , BARTOLI SIMONE , MARZIANI MONICA , FIGINI LUCA
IPC分类号： G06F12/00
CPC分类号： G06F9/30003 , G11C2216/22
摘要： The system includes a microcontroller (12) performing a modify operation on a flash memory array (16), a memory (14) coupled to the microcontroller (12) and storing suspend sequence code for causing a suspension of the modify operation when executed by the microcontroller (12), and suspend circuitry (30) that receives a suspend request (22) from a user to suspend the modify operation and starts the execution of the suspend sequence code.
摘要翻译：该系统包括对闪速存储器阵列（16）执行修改操作的微控制器（12），耦合到微控制器（12）的存储器（14），并且存储暂停序列代码，用于当由微控制器（12）和挂起电路（30），其从用户接收暂停请求（22）以暂停修改操作并开始执行挂起序列码。

2. 发明申请

WO2006041730A3 METHOD AND SYSTEM FOR A PROGRAMMING APPROACH FOR A NONVOLATILE ELECTRONIC DEVICE 审中-公开
标题翻译：用于非易失性电子器件编程方法的方法和系统
公开(公告)号：WO2006041730A3
公开(公告)日：2006-08-17
申请号：PCT/US2005035296
申请日：2005-09-30
申请人： ATMEL CORP , SURICO STEFANO , BARTOLI SIMONE , TASSAN CASER FABIO , MARZIANI MONICA
发明人： SURICO STEFANO , BARTOLI SIMONE , TASSAN CASER FABIO , MARZIANI MONICA
IPC分类号： G11C16/06
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/12 , G11C16/3454 , G11C2211/5621 , G11C2211/5634
摘要： Aspects for programming a nonvolatile electronic device include performing an initial verify step of a programming algorithm with an initial type of reference voltage value, and performing one or more subsequent verify steps in the programming algorithm with a second type of reference voltage value. Further included is utilizing a read reference voltage for the initial verify step, wherein desired programming is ensured for a cell that falls out of ideal distribution.
摘要翻译：用于编程非易失性电子设备的方面包括利用初始类型的参考电压值执行编程算法的初始验证步骤，并且利用第二类型的参考电压值在编程算法中执行一个或多个后续验证步骤。进一步包括利用读取参考电压进行初始验证步骤，其中对于落在理想分布之外的单元确保期望的编程。

3. 发明申请

WO2008076546A3 METHOD AND DEVICE FOR MANAGING A POWER SUPPLY POWER-ON SEQUENCE 审中-公开
标题翻译：用于管理电源上电序列的方法和设备
公开(公告)号：WO2008076546A3
公开(公告)日：2008-08-14
申请号：PCT/US2007084166
申请日：2007-11-08
申请人： ATMEL CORP , FRULIO MASSIMILIANO , SURICO STEFANO , BETTINI ANDREA , MARZIANI MONICA
发明人： FRULIO MASSIMILIANO , SURICO STEFANO , BETTINI ANDREA , MARZIANI MONICA
IPC分类号： H03K19/0175
CPC分类号： G11C5/147 , G11C5/143
摘要： Many circuits require a minimum voltage supply level before proper operation may be initiated. Power-on control circuits have typically used a voltage supply level detector and have compared that level with an internal reference. The internal reference typically has a dependence on device threshold, accuracy of tracking electrical characteristics in the device, as well as temperature and processing variation. The present invention (400) incorporates a typical supply voltage detector (410) to trigger a reference voltage generator (420). The reference voltage generator (420) is a temperature and process independent supply capable of operating at low power supply levels. An output voltage level from the reference voltage generator (420) is compared with the ramping-up supply voltage. When the ramping-up supply voltage is greater than the reference voltage generator output voltage level an enable signal is produced. The enable signal signifies to system circuitry that a supply voltage level great enough to support nominal operations is present.
摘要翻译：许多电路在启动正常操作之前需要最小电压电平。上电控制电路通常使用电压电平检测器，并将其与内部参考电平进行比较。内部参考通常取决于器件阈值，跟踪器件电气特性的准确性，以及温度和工艺变化。本发明（400）包含典型电源电压检测器（410）以触发参考电压发生器（420）。参考电压发生器（420）是能够在低电源电平下工作的温度和工艺独立电源。将来自参考电压发生器（420）的输出电压电平与斜升电源电压进行比较。当斜升电源电压大于参考电压发生器输出电压电平时，产生使能信号。使能信号表示系统电路存在足够大以支持标称操作的电源电压水平。

4. 发明申请

WO2006119327A3 METHOD AND SYSTEM FOR PROGRAM PULSE GENERATION DURING PROGRAMMING OF NONVOLATILE ELECTRONIC DEVICES 审中-公开
标题翻译：非线性电子设备编程过程中的程序脉冲发生方法与系统
公开(公告)号：WO2006119327A3
公开(公告)日：2007-12-13
申请号：PCT/US2006016902
申请日：2006-05-03
申请人： ATMEL CORP , SURICO STEFANO , MARSELLA MIRELLA , MARZIANI MONICA , CHINOSI MAURO
发明人： SURICO STEFANO , MARSELLA MIRELLA , MARZIANI MONICA , CHINOSI MAURO
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/3468
摘要： Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.
摘要翻译：在非易失性电子设备的编程期间，用于编程脉冲产生的方面包括提供可配置的电压序列发生器，用于在非易失性电子设备的编程算法的修改操作期间根据需要管理验证脉冲和脉冲验证切换，其中产生更有效的修改操作。以这种方式，可以容易地由微控制器管理的高度灵活的位序列生成，导致更短的代码长度，更快的执行时间以及在不同器件中的重用性。更具体地，引入完全兼容的电压序列生成，其可以应用于正被修改的闪存单元的端子，并且允许对脉冲验证和验证脉冲切换的有效且省时的管理。

5. 发明申请

WO2006119404A3 METHOD AND SYSTEM FOR CONFIGURING PARAMETERS FOR A FLASH MEMORY 审中-公开
标题翻译：用于配置闪速存储器参数的方法和系统
公开(公告)号：WO2006119404A3
公开(公告)日：2007-04-05
申请号：PCT/US2006017096
申请日：2006-05-03
申请人： ATMEL CORP , SURICO STEFANO , BARTOLI SIMONE , MARSELLA MIRELLA , BOSISIO GIORGIO
发明人： SURICO STEFANO , BARTOLI SIMONE , MARSELLA MIRELLA , BOSISIO GIORGIO
IPC分类号： G06F12/00
CPC分类号： G11C16/20 , G11C16/04 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/4402
摘要： Method and system for configuring parameters used in flash memory devices. A load instruction and associated address are retrieved from a read-only memory, and the address is used to select a configuration register storing a configuration value. The configuration value is loaded to an associated dedicated register to configure a parameter of the flash memory in a flash memory operation. In another aspect, one or more selected configuration values not stored in a ROM are changed if a tested flash memory operation is not within desired specifications.
摘要翻译：用于配置闪存设备中使用的参数的方法和系统。从只读存储器检索加载指令和相关联的地址，并且该地址用于选择存储配置值的配置寄存器。配置值加载到相关联的专用寄存器，以在闪存操作中配置闪存的参数。在另一方面，如果测试的闪速存储器操作不在期望的规范内，则不存储在ROM中的一个或多个选择的配置值被改变。

6. 发明申请

WO2008076553A3 COLUMN REDUNDANCY FOR A FLASH MEMORY WITH A HIGH WRITE PARALLELISM 审中-公开
标题翻译：具有高写并发性的闪存存储器的冗余冗余
公开(公告)号：WO2008076553A3
公开(公告)日：2009-01-22
申请号：PCT/US2007084460
申请日：2007-11-12
申请人： ATMEL CORP , BARTOLI SIMONE , SURICO STEFANO , SACCO ANDREA , MOSTOLA MARIA
发明人： BARTOLI SIMONE , SURICO STEFANO , SACCO ANDREA , MOSTOLA MARIA
IPC分类号： G06F11/00
CPC分类号： G11C29/82 , G11C29/806 , G11C29/846
摘要： A redundant memory array (300) has r columns of redundant memory cells (306), r redundant senses (312), and a redundant column decoder (308). Redundant address registers (332) store addresses of defective regular memory cells. Redundant latches (338) are provided in n groups of r latches. Redundancy comparison logic (330) compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal (333) to disable the regular senses (310) for one of the n groups of m columns, an ENABLE_LATCH signal (334) to one of the n groups of m columns to disable corresponding regular senses, and one of r REDO signals (336) to a respective one of the r redundant latches (338) in one of the n groups that is disabled. The selected one of the redundant latches (338) activates one of the r redundant senses (312) to access a redundant column.
摘要翻译：冗余存储器阵列（300）具有r列的冗余存储器单元（306），r冗余感测（312）和冗余列解码器（308）。冗余地址寄存器（332）存储有缺陷的常规存储单元的地址。冗余锁存器（338）设置在n组r个锁存器中。冗余比较逻辑（330）将缺陷规则存储器单元的地址与外部输入地址进行比较。如果比较是真实的，则提供的是：禁用n列m列中的一个的常规感测（310）的DISABLE_LOAD信号（333），到m列的n组之一的ENABLE_LATCH信号（334）禁用相应的常规感测，并且将r个REDO信号中的一个（336）禁止到被禁用的n个组中的一个中的r个冗余锁存器（338）中的相应一个。所选择的冗余锁存器（338）中的一个激活r个冗余感测（312）中的一个以访问冗余列。

7. 发明申请

WO2006044190A3 MANAGING ADDRESS BITS DURING BUFFERED PROGRAM OPERATIONS 审中-公开
标题翻译：在缓存程序运行期间管理地址
公开(公告)号：WO2006044190A3
公开(公告)日：2007-03-15
申请号：PCT/US2005035658
申请日：2005-10-04
申请人： ATMEL CORP , BARTOLI SIMONE , SURICO STEFANO , MANFRE DAVIDE , FERRARIO DONATO
发明人： BARTOLI SIMONE , SURICO STEFANO , MANFRE DAVIDE , FERRARIO DONATO
IPC分类号： G06F12/00
CPC分类号： G06F12/04 , G11C16/10 , G11C2216/14
摘要： A method and system for managing a buffered program operation for plurality of words is described. In one aspect the method and system include providing an internal buffer including a plurality of locations and at least one bit location for the plurality of locations. Each of the words is stored in a location of the plurality of locations (204). The words are associated with internal address bits for the locations. At least one of the internal address bits is at least one group address bit that corresponds to all of the words (206). A remaining portion of the internal address bits is associated at least one of the words. The at least one bit location stores the at least one group address bit for the words. Thus, in one aspect, the method and system include storing each of the words one of the buffer locations. The method and system also include associating the at least one group address bit with the buffer location for each of the words (202).
摘要翻译：描述用于管理用于多个单词的缓冲程序操作的方法和系统。在一个方面，该方法和系统包括提供包括多个位置的内部缓冲器和用于多个位置的至少一个位位置。每个字被存储在多个位置的位置（204）中。这些单词与位置的内部地址位相关联。内部地址位中的至少一个是与所有字对应的至少一个组地址位（206）。内部地址位的剩余部分与至少一个字相关联。所述至少一个位位置存储所述字的至少一个组地址位。因此，在一个方面，该方法和系统包括存储缓冲器位置之一中的每一个字。方法和系统还包括将至少一个组地址位与每个字（202）的缓冲器位置相关联。

8. 发明申请

WO2008055183A2 ADAPTIVE GATE VOLTAGE REGULATION 审中-公开
标题翻译：自适应门电压调节
公开(公告)号：WO2008055183A2
公开(公告)日：2008-05-08
申请号：PCT/US2007083062
申请日：2007-10-30
申请人： ATMEL CORP , SIVERO STEFANO , SURICO STEFANO , CASER FABIO TASSAN , CHINOSI MAURO
发明人： SIVERO STEFANO , SURICO STEFANO , CASER FABIO TASSAN , CHINOSI MAURO
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483
摘要： A memory device generates a select voltage and an unselect voltage on bit lines and generates a bit line select voltage having a magnitude less than the unselect voltage so that the application of the bit line select voltage to a gate of a transistor receiving the select voltage causes the transistor to conduct, and the application of the bit line select voltage to a gate of a transistor receiving the unselect voltage biases the transistor off.
摘要翻译：存储器件在位线上产生选择电压和取消选择电压，并产生具有小于未选择电压的幅度的位线选择电压，从而将位线选择电压施加到接收选择电压的晶体管的栅极导致晶体管导通，并且将位线选择电压施加到接收去选择电压的晶体管的栅极偏置晶体管。

9. 发明申请

WO2008057835A3 LOW VOLTAGE COLUMN DECODER SHARING A MEMORY ARRAY P-WELL 审中-公开
标题翻译：低电压柱解码器共享存储阵列P-WELL
公开(公告)号：WO2008057835A3
公开(公告)日：2009-03-12
申请号：PCT/US2007082875
申请日：2007-10-29
申请人： ATMEL CORP , FRULIO MASSIMILIANO , SURICO STEFANO , SACCO ANDREA , MANFRE DAVIDE
发明人： FRULIO MASSIMILIANO , SURICO STEFANO , SACCO ANDREA , MANFRE DAVIDE
IPC分类号： G11C8/00
CPC分类号： G11C16/08
摘要： A plurality of memory sub-arrays (302A - 302X) are formed in a p-well region (304). Each of the memory sub-arrays (302A - 302X) has at least one first-level column decoder (306A - 306X) that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder (316) is formed outside of the p-well region (304) and includes high-voltage MOS transistors to provide an output signal to one of an array of sense amplifiers (320). During a memory erase mode of operation, a high voltage is provided to bias the p-well region (304) and a plurality of high-voltage switches (326A - 326X) are activated to provide a high voltage to gate terminals of the selector transistor in the first-level column decoders (306 A 306X).
摘要翻译：多个存储器子阵列（302A-302X）形成在p阱区域（304）中。每个存储子阵列（302A-302X）具有至少一个第一级解码器（306A-306X），其包括也形成在p阱内的多个低压MOS选择晶体管。最后一级解码器（316）形成在p阱区域（304）的外部，并且包括高压MOS晶体管，以向读出放大器（320）阵列之一提供输出信号。在存储器擦除操作模式期间，提供高电压以偏置p阱区域（304），并且激活多个高压开关（326A-326X）以向选择器晶体管的栅极端提供高电压在第一级列解码器（306A 306X）中。

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