专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2006119327A3 METHOD AND SYSTEM FOR PROGRAM PULSE GENERATION DURING PROGRAMMING OF NONVOLATILE ELECTRONIC DEVICES 审中-公开
标题翻译：非线性电子设备编程过程中的程序脉冲发生方法与系统
公开(公告)号：WO2006119327A3
公开(公告)日：2007-12-13
申请号：PCT/US2006016902
申请日：2006-05-03
申请人： ATMEL CORP , SURICO STEFANO , MARSELLA MIRELLA , MARZIANI MONICA , CHINOSI MAURO
发明人： SURICO STEFANO , MARSELLA MIRELLA , MARZIANI MONICA , CHINOSI MAURO
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/3468
摘要： Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.
摘要翻译：在非易失性电子设备的编程期间，用于编程脉冲产生的方面包括提供可配置的电压序列发生器，用于在非易失性电子设备的编程算法的修改操作期间根据需要管理验证脉冲和脉冲验证切换，其中产生更有效的修改操作。以这种方式，可以容易地由微控制器管理的高度灵活的位序列生成，导致更短的代码长度，更快的执行时间以及在不同器件中的重用性。更具体地，引入完全兼容的电压序列生成，其可以应用于正被修改的闪存单元的端子，并且允许对脉冲验证和验证脉冲切换的有效且省时的管理。

2. 发明申请

WO2008055184A3 PROGRAMMING PULSE GENERATOR FOR NONVOLATILE NAND-MEMORY 审中-公开
标题翻译：用于非易失性NAND存储器的编程脉冲发生器
公开(公告)号：WO2008055184A3
公开(公告)日：2008-06-19
申请号：PCT/US2007083063
申请日：2007-10-30
申请人： ATMEL CORP , SIVERO STEFANO , MARSELLA MIRELLA , CHINOSI MAURO , BOSISIO GIORGIO
发明人： SIVERO STEFANO , MARSELLA MIRELLA , CHINOSI MAURO , BOSISIO GIORGIO
IPC分类号： G11C16/12
CPC分类号： G11C16/12
摘要： A signal generator circuit is configured to generate program signals for a memory array. The program signals are applied to word lines in the memory array, and have a transient state based on a coupling characteristic of the word lines and selector gates. The transient state is configured to minimize coupling between the word lines and the gates of the selectors so that a state of each selector remains unchanged during the transient state.
摘要翻译：信号发生器电路被配置为产生用于存储器阵列的程序信号。程序信号被施加到存储器阵列中的字线，并且基于字线和选择器门的耦合特性具有瞬态状态。瞬态状态被配置为最小化字线和选择器的栅极之间的耦合，使得每个选择器的状态在过渡状态期间保持不变。

3. 发明申请

WO2008055183A2 ADAPTIVE GATE VOLTAGE REGULATION 审中-公开
标题翻译：自适应门电压调节
公开(公告)号：WO2008055183A2
公开(公告)日：2008-05-08
申请号：PCT/US2007083062
申请日：2007-10-30
申请人： ATMEL CORP , SIVERO STEFANO , SURICO STEFANO , CASER FABIO TASSAN , CHINOSI MAURO
发明人： SIVERO STEFANO , SURICO STEFANO , CASER FABIO TASSAN , CHINOSI MAURO
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/0483
摘要： A memory device generates a select voltage and an unselect voltage on bit lines and generates a bit line select voltage having a magnitude less than the unselect voltage so that the application of the bit line select voltage to a gate of a transistor receiving the select voltage causes the transistor to conduct, and the application of the bit line select voltage to a gate of a transistor receiving the unselect voltage biases the transistor off.
摘要翻译：存储器件在位线上产生选择电压和取消选择电压，并产生具有小于未选择电压的幅度的位线选择电压，从而将位线选择电压施加到接收选择电压的晶体管的栅极导致晶体管导通，并且将位线选择电压施加到接收去选择电压的晶体管的栅极偏置晶体管。

4. 发明申请

WO2006044942A2 METHOD AND SYSTEM FOR PROVIDING SENSING CIRCUITRY IN A MULTI-BANK MEMORY DEVICE 审中-公开
标题翻译：在多银行存储器件中提供感应电路的方法和系统
公开(公告)号：WO2006044942A2
公开(公告)日：2006-04-27
申请号：PCT/US2005037546
申请日：2005-10-18
申请人： ATMEL CORP , FRULIO MASSIMILIANO , SIVERO STEFANO , CASER FABIO TASSAN , CHINOSI MAURO
发明人： FRULIO MASSIMILIANO , SIVERO STEFANO , CASER FABIO TASSAN , CHINOSI MAURO
IPC分类号： G11C8/00
CPC分类号： G11C7/18 , G11C7/06 , G11C2207/002 , G11C2207/005
摘要： A method and system for providing a multi-bank memory is described. The method and system include providing a plurality of banks. Each of the plurality of banks includes at least one array including a plurality of memory cells and analog sensing circuitry. The method and system further include providing common digital sensing circuitry coupled with the plurality of banks.
摘要翻译：描述了一种用于提供多存储体存储器的方法和系统。该方法和系统包括提供多个银行。多个组中的每一个包括至少一个包括多个存储单元和模拟感测电路的阵列。该方法和系统还包括提供与多个存储体耦合的公共数字感测电路。

5. 发明申请

WO2008089158A3 COMPENSATED CURRENT OFFSET IN A SENSING CIRCUIT 审中-公开
标题翻译：传感电路中的补偿电流偏移
公开(公告)号：WO2008089158A3
公开(公告)日：2009-12-30
申请号：PCT/US2008051024
申请日：2008-01-14
申请人： ATMEL CORP , BEDARIDA LORENZO , PELLI GABRIELE , BARTOLI SIMONE , CHINOSI MAURO
发明人： BEDARIDA LORENZO , PELLI GABRIELE , BARTOLI SIMONE , CHINOSI MAURO
IPC分类号： G11C7/08
CPC分类号： G11C7/062 , G11C7/02 , G11C7/067 , G11C16/26 , G11C2207/063
摘要： A sensing circuit with current offset functionality. In one embodiment, the sensing circuit includes a memory circuit having a first offset circuit operative to offset a first current. The sensing circuit also includes a reference circuit coupled to the memory circuit, where the reference circuit includes a second offset circuit operative to offset a second current. The sensing circuit also includes a compare circuit coupled to the memory circuit and the reference circuit, where the compare circuit determines the state of a memory cell based on first current and the second current. According to the system disclosed herein, the first and second offset circuits optimize the performance of the sensing circuit and prevent errors when determining the state of the memory cell.
摘要翻译：具有电流偏移功能的感测电路。在一个实施例中，感测电路包括存储器电路，该存储器电路具有可操作以偏移第一电流的第一偏移电路。感测电路还包括耦合到存储器电路的参考电路，其中参考电路包括可操作以偏移第二电流的第二偏移电路。感测电路还包括耦合到存储器电路和参考电路的比较电路，其中比较电路基于第一电流和第二电流确定存储器单元的状态。根据本文公开的系统，第一和第二偏移电路优化感测电路的性能并且在确定存储器单元的状态时防止错误。

6. 发明申请

WO2004025390A3 TEMPERATURE-COMPENSATED CURRENT REFERENCE CIRCUIT 审中-公开
标题翻译：温度补偿电流参考电路
公开(公告)号：WO2004025390A3
公开(公告)日：2005-06-16
申请号：PCT/US0328835
申请日：2003-09-12
申请人： ATMEL CORP
发明人： ODDONE GIORGIO , BEDARIDA LORENZO , CHINOSI MAURO
IPC分类号： G05F3/26 , G05F1/10 , G05F3/02 , G05F3/16 , G05F3/24
CPC分类号： G05F3/245
摘要： A current-reference circuit comprises a CMOS differential amplifier having first output node comprising a drain of a first n-channel MOS transistor and a second output node comprising a drain of a second n-channel MOS transistor. A first p-channel MOS transistor has a source coupled to a supply potential, a gate coupled to the second output node, and a drain. A first PNP bipolar transistor has an emitter coupled to the drain of the first p-channel MOS transistor through a first resistor and to a gate of the second n-channel MOS transistor, and a collector and a base both coupled to ground. A second PNP bipolar transistor has an emitter coupled to the drain of the first p-channel MOS transistor through a second resistor in series with a third resistor, and a collector and a base both coupled to ground. The gate of the first n-channel MOS transistor is coupled to a common node between the second and third resistors. A third n-channel MOS transistor has a drain coupled to the drain of the first p-channel MOS transistor, a source coupled to ground through a fourth resistor, and a gate coupled to either a reference potential or to the common node between the second and third resistors.
摘要翻译：电流参考电路包括具有第一输出节点的CMOS差分放大器，该第一输出节点包括第一n沟道MOS晶体管的漏极和包括第二n沟道MOS晶体管的漏极的第二输出节点。第一p沟道MOS晶体管具有耦合到电源电位的源极，耦合到第二输出节点的栅极和漏极。第一PNP双极晶体管具有通过第一电阻器和第二n沟道MOS晶体管的栅极耦合到第一p沟道MOS晶体管的漏极的发射极，以及耦合到地的集电极和基极。第二PNP双极晶体管具有通过与第三电阻器串联的第二电阻器以及耦合到地的集电极和基极耦合到第一p沟道MOS晶体管的漏极的发射极。第一n沟道MOS晶体管的栅极耦合到第二和第三电阻之间的公共节点。第三n沟道MOS晶体管具有耦合到第一p沟道MOS晶体管的漏极的漏极，通过第四电阻器耦合到地的源极，以及耦合到参考电位或者在第二p沟道MOS晶体管的公共节点之间的栅极和第三电阻。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式