专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2008057835A3 LOW VOLTAGE COLUMN DECODER SHARING A MEMORY ARRAY P-WELL 审中-公开
标题翻译：低电压柱解码器共享存储阵列P-WELL
公开(公告)号：WO2008057835A3
公开(公告)日：2009-03-12
申请号：PCT/US2007082875
申请日：2007-10-29
申请人： ATMEL CORP , FRULIO MASSIMILIANO , SURICO STEFANO , SACCO ANDREA , MANFRE DAVIDE
发明人： FRULIO MASSIMILIANO , SURICO STEFANO , SACCO ANDREA , MANFRE DAVIDE
IPC分类号： G11C8/00
CPC分类号： G11C16/08
摘要： A plurality of memory sub-arrays (302A - 302X) are formed in a p-well region (304). Each of the memory sub-arrays (302A - 302X) has at least one first-level column decoder (306A - 306X) that includes a plurality of low-voltage MOS selector transistors that are also formed within the p-well. A last-level decoder (316) is formed outside of the p-well region (304) and includes high-voltage MOS transistors to provide an output signal to one of an array of sense amplifiers (320). During a memory erase mode of operation, a high voltage is provided to bias the p-well region (304) and a plurality of high-voltage switches (326A - 326X) are activated to provide a high voltage to gate terminals of the selector transistor in the first-level column decoders (306 A 306X).
摘要翻译：多个存储器子阵列（302A-302X）形成在p阱区域（304）中。每个存储子阵列（302A-302X）具有至少一个第一级解码器（306A-306X），其包括也形成在p阱内的多个低压MOS选择晶体管。最后一级解码器（316）形成在p阱区域（304）的外部，并且包括高压MOS晶体管，以向读出放大器（320）阵列之一提供输出信号。在存储器擦除操作模式期间，提供高电压以偏置p阱区域（304），并且激活多个高压开关（326A-326X）以向选择器晶体管的栅极端提供高电压在第一级列解码器（306A 306X）中。

2. 发明申请

WO2008089159A3 SENSE AMPLIFIER WITH STAGES TO REDUCE CAPACITANCE MISMATCH IN CURRENT MIRROR LOAD 审中-公开
标题翻译：具有降低电流误差的步骤的感应放大器
公开(公告)号：WO2008089159A3
公开(公告)日：2009-12-30
申请号：PCT/US2008051025
申请日：2008-01-15
申请人： ATMEL CORP , PELLI GABRIELE , BEDARIDA LORENZO , FRULIO MASSIMILIANO , MANFRE DAVIDE
发明人： PELLI GABRIELE , BEDARIDA LORENZO , FRULIO MASSIMILIANO , MANFRE DAVIDE
IPC分类号： G11C7/06
CPC分类号： G11C7/062 , G11C7/067 , G11C16/28 , G11C2207/063
摘要： A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages provided by the first stage and the second stage, where the state indicated by the comparator is substantially unaffected by capacitive current components provided by transient behavior of the first and second stages.
摘要翻译：一种用于读取存储器单元状态的读出放大器电路。在本发明的一个方面，读出放大器电路包括接收从存储单元导出的单元电流的第一级和从参考单元导出的参考电流，以及接收单元电流和参考电流的第二级。耦合到第一级和第二级的比较器基于由第一级和第二级提供的电压的差提供指示存储器单元的状态的输出，其中由比较器指示的状态基本上不受由第一和第二级的瞬态特性提供的电容电流分量的影响。

3. 发明申请

WO2006044190A3 MANAGING ADDRESS BITS DURING BUFFERED PROGRAM OPERATIONS 审中-公开
标题翻译：在缓存程序运行期间管理地址
公开(公告)号：WO2006044190A3
公开(公告)日：2007-03-15
申请号：PCT/US2005035658
申请日：2005-10-04
申请人： ATMEL CORP , BARTOLI SIMONE , SURICO STEFANO , MANFRE DAVIDE , FERRARIO DONATO
发明人： BARTOLI SIMONE , SURICO STEFANO , MANFRE DAVIDE , FERRARIO DONATO
IPC分类号： G06F12/00
CPC分类号： G06F12/04 , G11C16/10 , G11C2216/14
摘要： A method and system for managing a buffered program operation for plurality of words is described. In one aspect the method and system include providing an internal buffer including a plurality of locations and at least one bit location for the plurality of locations. Each of the words is stored in a location of the plurality of locations (204). The words are associated with internal address bits for the locations. At least one of the internal address bits is at least one group address bit that corresponds to all of the words (206). A remaining portion of the internal address bits is associated at least one of the words. The at least one bit location stores the at least one group address bit for the words. Thus, in one aspect, the method and system include storing each of the words one of the buffer locations. The method and system also include associating the at least one group address bit with the buffer location for each of the words (202).
摘要翻译：描述用于管理用于多个单词的缓冲程序操作的方法和系统。在一个方面，该方法和系统包括提供包括多个位置的内部缓冲器和用于多个位置的至少一个位位置。每个字被存储在多个位置的位置（204）中。这些单词与位置的内部地址位相关联。内部地址位中的至少一个是与所有字对应的至少一个组地址位（206）。内部地址位的剩余部分与至少一个字相关联。所述至少一个位位置存储所述字的至少一个组地址位。因此，在一个方面，该方法和系统包括存储缓冲器位置之一中的每一个字。方法和系统还包括将至少一个组地址位与每个字（202）的缓冲器位置相关联。

4. 发明申请

WO2008089157A2 COLUMN LEAKAGE COMPENSATION IN A SENSING CIRCUIT 审中-公开
标题翻译：感应电路中的柱泄漏补偿
公开(公告)号：WO2008089157A2
公开(公告)日：2008-07-24
申请号：PCT/US2008051023
申请日：2008-01-14
申请人： ATMEL CORP , BEDARIDA LORENZO , MOSTOLA MARIA , MANFRE DAVIDE , FERRARIO DONATO
发明人： BEDARIDA LORENZO , MOSTOLA MARIA , MANFRE DAVIDE , FERRARIO DONATO
IPC分类号： G11C16/28 , G11C7/06 , G11C29/00
CPC分类号： G11C29/12 , G11C7/062 , G11C7/12 , G11C16/04 , G11C16/26
摘要： A sensing circuit. In one embodiment, the sensing circuit includes a memory circuit including a first bitline that sinks a first leakage current, a compensation device coupled to the memory circuit, and a compensation circuit coupled to the compensation device. The compensation circuit includes a second bitline that sinks a second leakage current that matches the first leakage current. The compensation device is operative to compensate the first leakage current through a current based on the second leakage current. According to the system and method disclosed herein, the compensation device and compensation circuit prevents errors when determining the state of the memory cell.
摘要翻译：感测电路。在一个实施例中，感测电路包括存储电路，其包括吸收第一泄漏电流的第一位线，耦合到存储器电路的补偿装置和耦合到补偿装置的补偿电路。补偿电路包括吸收与第一泄漏电流匹配的第二漏电流的第二位线。补偿装置用于基于第二泄漏电流补偿通过电流的第一泄漏电流。根据本文公开的系统和方法，在确定存储单元的状态时，补偿装置和补偿电路可以防止错误。

5. 发明申请

WO2006033832A3 NEW COMPENSATED METHOD TO IMPLEMENT A HIGH VOLTAGE DISCHARGE PHASE AFTER ERASE PULSE IN A FLASH MEMORY DEVICE 审中-公开
标题翻译：用于在闪速存储器件中擦除脉冲之后实现高电压放电相的新补偿方法
公开(公告)号：WO2006033832A3
公开(公告)日：2007-02-15
申请号：PCT/US2005031830
申请日：2005-09-07
申请人： ATMEL CORP , BEDARIDA LORENZO , BARTOLI SIMONE , ODDONE GIORGIO , MANFRE DAVIDE
发明人： BEDARIDA LORENZO , BARTOLI SIMONE , ODDONE GIORGIO , MANFRE DAVIDE
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/10 , G11C16/22
摘要： A method for discharge in a flash memory device includes: initiating a discharge of a memory cell after an erase operation; coupling a first discharge circuit to a first plate of a gate-bulk capacitor, and a second discharge circuit to a second plate of the gate-bulk capacitor, where the first plate represents the common gate node of the memory cell and the second plate represents the bulk-source node of the memory cell; and coupling the common gate node and the bulk-source node to ground to provide for a complete discharge. The current injected into the first plate approximately equals the current extracted from the second plate. In this manner, dangerous oscillations of the gate and bulk-source voltages as they go to ground are eliminated without complicated designs or voltage limitators, and without sacrificing the fast discharge after the erase operation. The reliability of the discharge operation is thus significantly improved.
摘要翻译：一种闪速存储装置中的放电方法包括：在擦除操作之后启动存储单元的放电; 将第一放电电路耦合到栅极体积电容器的第一板，以及第二放电电路连接到栅极 - 体积电容器的第二板，其中第一板表示存储单元的公共栅极节点，第二板表示存储器单元的体源节点; 并将公共栅极节点和体源极节点耦合到地，以提供完全放电。注入第一板的电流大约等于从第二板提取的电流。以这种方式，在没有复杂的设计或电压限制器的情况下，栅极和体源电压的危险振荡消除，而不会在擦除操作之后不牺牲快速放电。因此，放电操作的可靠性显着提高。

6. 发明申请

WO2004027777A2 A FAST CONTROLLED OUTPUT BUFFER 审中-公开
标题翻译：快速控制的输出缓冲器
公开(公告)号：WO2004027777A2
公开(公告)日：2004-04-01
申请号：PCT/US0329307
申请日：2003-09-16
申请人： ATMEL CORP
发明人： BEDARIDA LORENZO , SIVERO STEFANO , MANFRE DAVIDE
IPC分类号： H03K19/0175 , H03K17/16 , H03K19/003 , G11C
CPC分类号： H03K17/166 , H03K17/165 , H03K19/00361
摘要： An output buffer switch-on control circuit includes several transistors and a discharge current control circuit. A first transistor has a first terminal connected to an internal voltage line and is controlled by an output data source. A second transistor has a first terminal connected to the internal voltage line and is controlled by a second terminal of the first transistor. The second transistor also has a second terminal connected to a first terminal of an output capacitor. A third transistor is controlled by the output data source and has a first terminal connected to a common voltage. A fourth transistor is digitally controlled and has a first terminal connected to the second terminal of the second transistor. The fourth transistor also has a second terminal connected to the common voltage. The discharge current control circuit is preferably actively-controlled and is connected between a second terminal of the first transistor and a second terminal of the third transistor. The discharge current control circuit preferably includes a discharge resistor and a mirrored current transistor feedback controlled by an output capacitor.
摘要翻译：输出缓冲器接通控制电路包括多个晶体管和放电电流控制电路。第一晶体管具有连接到内部电压线并由输出数据源控制的第一端子。第二晶体管具有连接到内部电压线的第一端子，并由第一晶体管的第二端子控制。第二晶体管还具有连接到输出电容器的第一端子的第二端子。第三晶体管由输出数据源控制，并具有连接到公共电压的第一端子。数字控制第四晶体管，并且具有连接到第二晶体管的第二端子的第一端子。第四晶体管还具有连接到公共电压的第二端子。放电电流控制电路优选地被主动地控制并且连接在第一晶体管的第二端子和第三晶体管的第二端子之间。放电电流控制电路优选地包括放电电阻器和由输出电容器控制的镜像电流晶体管反馈。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式