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1. 发明申请

WO2011025655A2 SILICON-SELECTIVE DRY ETCH FOR CARBON-CONTAINING FILMS 审中-公开
标题翻译：用于含碳膜的硅选择性干法蚀刻
公开(公告)号：WO2011025655A2
公开(公告)日：2011-03-03
申请号：PCT/US2010/045056
申请日：2010-08-10
申请人： APPLIED MATERIALS, INC. , SAPRE, Kedar , TANG, Jing , WANG, Linlin , MALLICK, Abhijit Basu , INGLE, Nitin
发明人： SAPRE, Kedar , TANG, Jing , WANG, Linlin , MALLICK, Abhijit Basu , INGLE, Nitin
IPC分类号： H01L21/3065 , G03F7/42 , B44C1/22
CPC分类号： H01L21/3065 , H01L21/31116
摘要： A method of etching silicon-and-carbon-containing material is described and includes a SiConi TM etch in combination with a flow of reactive oxygen. The reactive oxygen may be introduced before the SiConi TM etch reducing the carbon content in the near surface region and allowing the SiConi TM etch to proceed more rapidly. Alternatively, reactive oxygen may be introduced during the SiConi TM etch further improving the effective etch rate.
摘要翻译：描述了一种蚀刻含硅和碳材料的方法，其包括SiConi TM蚀刻与活性氧流的组合。在SiConi TM蚀刻降低近表面区域中的碳含量并允许SiConi TM蚀刻更快进行之前可引入活性氧。或者，可以在SiConi TM蚀刻期间引入活性氧，从而进一步提高有效蚀刻速率。

2. 发明申请

WO2013049173A2 IMPROVED INTRENCH PROFILE 审中-公开
标题翻译：改进的内容简档
公开(公告)号：WO2013049173A2
公开(公告)日：2013-04-04
申请号：PCT/US2012/057294
申请日：2012-09-26
申请人： APPLIED MATERIALS, INC. , SAPRE, Kedar , INGLE, Nitin K. , TANG, Jing
发明人： SAPRE, Kedar , INGLE, Nitin K. , TANG, Jing
CPC分类号： H01L21/3065 , H01L21/3081 , H01L21/76224
摘要： A method of etching a recess in a semiconductor substrate is described. The method may include forming a dielectric liner layer in a trench of the substrate where the liner layer has a first density. The method may also include depositing a second dielectric layer at least partially in the trench on the liner layer. The second dielectric layer may initially be flowable following the deposition, and have a second density that is less than the first density of the liner. The method may further include exposing the substrate to a dry etchant, where the etchant removes a portion of the first liner layer and the second dielectric layer to form a recess, where the dry etchant includes a fluorine-containing compound and molecular hydrogen, and where the etch rate ratio for removing the first dielectric liner layer to removing the second dielectric layer is about 1:1.2 to about 1:1.
摘要翻译：描述了蚀刻半导体衬底中的凹部的方法。该方法可以包括在衬底的沟槽中形成介质衬垫层，其中衬层具有第一密度。该方法还可以包括至少部分地在衬垫层上的沟槽中沉积第二电介质层。第二电介质层可以首先在沉积之后流动，并且具有小于衬垫的第一密度的第二密度。该方法可以进一步包括将衬底暴露于干蚀刻剂，其中蚀刻剂去除第一衬里层和第二介电层的一部分以形成凹陷，其中干燥蚀刻剂包括含氟化合物和分子氢，并且其中用于去除第一介电衬垫层以去除第二介电层的蚀刻速率比为约1:1.2至约1:1。

3. 发明申请

WO2013032873A1 DOUBLE PATTERNING ETCHING PROCESS 审中-公开
标题翻译：双重图案蚀刻过程
公开(公告)号：WO2013032873A1
公开(公告)日：2013-03-07
申请号：PCT/US2012/052171
申请日：2012-08-23
申请人： APPLIED MATERIALS, INC. , SAPRE, Kedar , TANG, Jing , BHATNAGAR, Ajay , INGLE, Nitin , VENKATARAMAN, Shankar
发明人： SAPRE, Kedar , TANG, Jing , BHATNAGAR, Ajay , INGLE, Nitin , VENKATARAMAN, Shankar
IPC分类号： H01L21/027
CPC分类号： H01L21/31144 , H01J37/32357 , H01J2237/334 , H01L21/0274 , H01L21/0337 , H01L21/3086 , H01L21/31116
摘要： A method of etching a substrate comprises forming on the substrate, a plurality of double patterning features composed of silicon oxide, silicon nitride, or silicon oxynitride. The substrate having the double patterning features is provided to a process zone. An etching gas comprising nitrogen tri-fluoride, ammonia and hydrogen is energized in a remote chamber. The energized etching gas is introduced into the process zone to etch the double patterning features to form a solid residue on the substrate. The solid residue is sublimated by heating the substrate to a temperature of at least about 100 C.
摘要翻译：蚀刻衬底的方法包括在衬底上形成由氧化硅，氮化硅或氮氧化硅组成的多个双重构图特征。具有双重图案化特征的基板被提供到处理区域。包括三氟化氮，氨和氢的蚀刻气体在远程室中通电。通电的蚀刻气体被引入到工艺区中以蚀刻双重图案化特征以在衬底上形成固体残余物。固体残余物通过将基底加热至至少约100℃的温度升华。

4. 发明申请

WO2007140424A2 CHEMICAL VAPOR DEPOSITION OF HIGH QUALITY FLOW-LIKE SILICON DIOXIDE USING A SILICON CONTAINING PRECURSOR AND ATOMIC OXYGEN 审中-公开
标题翻译：使用含硅前体和原子氧的高品质流动二氧化硅的化学气相沉积
公开(公告)号：WO2007140424A2
公开(公告)日：2007-12-06
申请号：PCT/US2007/069999
申请日：2007-05-30
申请人： APPLIED MATERIALS, INC. , INGLE, Nitin, K. , YUAN, Zheng , GEE, Paul , SAPRE, Kedar
发明人： INGLE, Nitin, K. , YUAN, Zheng , GEE, Paul , SAPRE, Kedar
IPC分类号： H01L21/31
CPC分类号： H01L21/3105 , C23C16/402 , C23C16/452 , C23C16/56 , H01L21/02126 , H01L21/02164 , H01L21/02216 , H01L21/02274 , H01L21/02315 , H01L21/02337 , H01L21/31633
摘要： Methods of depositing a silicon oxide layer on a substrate are described. The methods may include the steps of providing a substrate to a deposition chamber, generating an atomic oxygen precursor outside the deposition chamber, and introducing the atomic oxygen precursor into the chamber. The methods may also include introducing a silicon precursor to the deposition chamber, where the silicon precursor and the atomic oxygen precursor are first mixed in the chamber. The silicon precursor and the atomic oxygen precursor react to form the silicon oxide layer on the substrate, and the deposited silicon oxide layer may be annealed. Systems to deposit a silicon oxide layer on a substrate are also described.
摘要翻译：描述了在衬底上沉积氧化硅层的方法。该方法可以包括以下步骤：向沉积室提供衬底，在沉积室外产生原子氧前体，并将原子氧前体引入室中。所述方法还可以包括将硅前体引入沉积室，其中硅前体和原子氧前体首先在室中混合。硅前体和原子氧前体反应以在衬底上形成氧化硅层，并且沉积的氧化硅层可以退火。还描述了在衬底上沉积氧化硅层的系统。

5. 发明申请

WO2008157068A2 OXYGEN SACVD TO FORM SACRIFICIAL OXIDE LINERS IN SUBSTRATE GAPS 审中-公开
标题翻译：氧气SACVD在基板中形成氧化亚锡衬里
公开(公告)号：WO2008157068A2
公开(公告)日：2008-12-24
申请号：PCT/US2008/065971
申请日：2008-06-05
申请人： APPLIED MATERIALS, INC. , ZHENG, Yi , KWESKIN, Sasha, J. , SAPRE, Kedar , INGLE, Nitin, K. , YUAN, Zheng
发明人： ZHENG, Yi , KWESKIN, Sasha, J. , SAPRE, Kedar , INGLE, Nitin, K. , YUAN, Zheng
IPC分类号： H01L21/311
CPC分类号： H01L21/02126 , H01L21/02211 , H01L21/02216 , H01L21/02271 , H01L21/28132 , H01L21/3086 , H01L21/3088 , H01L21/3146 , H01L21/31604
摘要： A method of forming and removing a sacrificial oxide layer is described. The method includes forming a step on a substrate, where the step has a top and sidewalls. The method may also include forming the sacrificial oxide layer around the step by chemical vapor deposition of molecular oxygen and TEOS, where the oxide layer is formed on the top and sidewalls of the step. The method may also include removing a top portion of the oxide layer and the step; removing a portion of the substrate exposed by the removal of the step to form a etched substrate; and removing the entire sacrificial oxide layer from the etched substrate.
摘要翻译：描述了形成和去除牺牲氧化物层的方法。该方法包括在衬底上形成台阶，其中台阶具有顶部和侧壁。该方法还可以包括通过分子氧和TEOS的化学气相沉积在步骤周围形成牺牲氧化物层，其中氧化物层形成在台阶的顶部和侧壁上。该方法还可以包括去除氧化物层的顶部和步骤; 通过去除步骤去除暴露的基板的一部分以形成蚀刻的基板; 并从蚀刻的衬底去除整个牺牲氧化物层。

6. 发明申请

WO2013049223A2 INSENSITIVE DRY REMOVAL PROCESS FOR SEMICONDUCTOR INTEGRATION 审中-公开
标题翻译：半导体集成的不敏感干法去除过程
公开(公告)号：WO2013049223A2
公开(公告)日：2013-04-04
申请号：PCT/US2012/057358
申请日：2012-09-26
申请人： APPLIED MATERIALS, INC. , SAPRE, Kedar , MININNI, Rossella , TANG, Jing
发明人： SAPRE, Kedar , MININNI, Rossella , TANG, Jing
CPC分类号： H01L29/401 , H01L21/31116 , H01L29/66545
摘要： Methods of depositing and etching dielectric layers from a surface of a semiconductor substrate are disclosed. The methods may include depositing a first dielectric layer having a first wet etch rate in aqueous HF. The methods also may include depositing a second dielectric layer that may be initially flowable following deposition, and the second dielectric layer may have a second wet etch rate in aqueous HF that is higher than the first wet etch rate. The methods may further include etching the first and second dielectric layers with an etchant gas mixture, where the first and second dielectric layers have a ratio of etch rates that is closer to one than the ratio of the second wet etch rate to the first wet etch rate in aqueous HF.
摘要翻译：公开了从半导体衬底的表面沉积和蚀刻电介质层的方法。该方法可以包括在HF水溶液中沉积具有第一湿蚀刻速率的第一介电层。该方法还可以包括沉积在沉积之后可以初始可流动的第二介电层，并且第二介电层可以在HF水溶液中具有高于第一湿法蚀刻速率的第二湿法蚀刻速率。该方法可以进一步包括用蚀刻剂气体混合物蚀刻第一和第二介电层，其中第一和第二介电层具有比第二湿法蚀刻率与第一湿法蚀刻率的比值更接近于1的蚀刻率在HF水溶液中的速率。

7. 发明申请

WO2011112518A3 METHODS FOR FORMING LOW MOISTURE DIELECTRIC FILMS 审中-公开
公开(公告)号：WO2011112518A3
公开(公告)日：2011-09-15
申请号：PCT/US2011/027422
申请日：2011-03-07
申请人： APPLIED MATERIALS, INC. , HUA, Zhong Qiang , LUO, Lei , HERNANDEZ, Manuel A. , CAO, Zhitao , SAPRE, Kedar , BHATNAGAR, Ajay
发明人： HUA, Zhong Qiang , LUO, Lei , HERNANDEZ, Manuel A. , CAO, Zhitao , SAPRE, Kedar , BHATNAGAR, Ajay
IPC分类号： H01L21/205
摘要： A method for forming a pre-metal dielectric (PMD) layer or an inter-metal dielectric (IMD) layer over a substrate includes placing the substrate in a chemical vapor deposition (CVD) process chamber and forming a first oxide layer over the substrate in the CVD process chamber. The first oxide layer is formed using a thermal CVD process at a temperature of about 450°C or less and a sub-atmospheric pressure. The method also includes forming a second oxide layer over the first oxide layer in the CVD process chamber. The second oxide layer is formed using a plasma enhanced chemical vapor deposition (PECVD) process at a temperature of about 450°C or less and a sub-atmospheric pressure. The substrate remains in the CVD process chamber during formation of the first oxide layer and the second oxide layer.

8. 发明申请

WO2011112330A3 REDUCED PATTERN LOADING USING BIS(DIETHYLAMINO)SILANE (C8H22N2Si) AS SILICON PRECURSOR 审中-公开
公开(公告)号：WO2011112330A3
公开(公告)日：2011-09-15
申请号：PCT/US2011/025050
申请日：2011-02-16
申请人： APPLIED MATERIALS, INC. , KWESKIN, Sasha , GEE, Paul, Edward , VENKATARAMAN, Shankar , SAPRE, Kedar
发明人： KWESKIN, Sasha , GEE, Paul, Edward , VENKATARAMAN, Shankar , SAPRE, Kedar
IPC分类号： H01L21/205
摘要： Aspects of the disclosure pertain to methods of depositing dielectric layers on patterned substrates. In embodiments, dielectric layers are deposited by flowing BIS(DIETHYLAMINO)SILANE (BDEAS), ozone and molecular oxygen into a processing chamber such that a relatively uniform dielectric growth rate is achieved across the patterned substrate surface. The deposition of dielectric layers grown according to embodiments may have a reduced dependence on pattern density while still being suitable for non-sacrificial applications.

9. 发明申请

WO2013048872A1 PRETREATMENT AND IMPROVED DIELECTRIC COVERAGE 审中-公开
标题翻译：预处理和改进的电介质覆盖
公开(公告)号：WO2013048872A1
公开(公告)日：2013-04-04
申请号：PCT/US2012/056332
申请日：2012-09-20
申请人： Applied Materials, Inc. , LUO, Lei , VENKATARAMAN, Shanka , HERNANDEZ, Manuel A. , SAPRE, Kedar , HUA, Zhong Qiang
发明人： LUO, Lei , VENKATARAMAN, Shanka , HERNANDEZ, Manuel A. , SAPRE, Kedar , HUA, Zhong Qiang
IPC分类号： H01L21/31 , H01L21/768
CPC分类号： H01L21/0226 , H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/02315 , H01L21/02362 , H01L21/76831 , H01L21/76898
摘要： Methods of conformally depositing silicon oxide layers on patterned substrates are described. The patterned substrates are plasma treated such that subsequently deposited silicon oxide layers may deposit uniformly on walls of deep closed trenches. The technique is particularly useful for through-substrate vias (TSVs) which require especially deep trenches. The trenches may be closed at the bottom and deep to enable through-substrate vias (TSVs) by later removing a portion of the backside substrate (near to the closed end of the trench). The conformal silicon oxide layer thickness on the sidewalls near the bottom of a trench is greater than or about 70% of the conformal silicon oxide layer thickness near the top of the trench in embodiments of the invention. The improved uniformity of the silicon oxide layer enables a subsequently deposited conducting plug to be thicker and offer less electrical resistance.
摘要翻译：描述了在图案化衬底上共形沉积氧化硅层的方法。图案化的衬底被等离子体处理，使得随后沉积的氧化硅层可以均匀地沉积在深闭合的沟槽的壁上。该技术对于需要特别深的沟槽的贯通衬底通孔（TSV）特别有用。沟槽可以在底部和深处封闭，以通过稍后去除背面基板的一部分（靠近沟槽的封闭端）来实现贯穿衬底通孔（TSV）。在本发明的实施方案中，靠近沟槽底部的侧壁上的共形氧化硅层厚度大于或接近沟槽顶部的共形氧化硅层厚度的约70％。氧化硅层的改进的均匀性使得随后沉积的导电插头更厚并且提供更少的电阻。

10. 发明申请

WO2011129957A2 PREFERENTIAL DIELECTRIC GAPFILL 审中-公开
标题翻译：优选电介质
公开(公告)号：WO2011129957A2
公开(公告)日：2011-10-20
申请号：PCT/US2011/029428
申请日：2011-03-22
申请人： APPLIED MATERIALS, INC. , KWESKIN, Sasha , HAMANA, Hiroshi , GEE, Paul Edward , VENKATARAMAN, Shankar , SAPRE, Kedar
发明人： KWESKIN, Sasha , HAMANA, Hiroshi , GEE, Paul Edward , VENKATARAMAN, Shankar , SAPRE, Kedar
IPC分类号： H01L21/316 , H01L21/31
CPC分类号： H01L21/76229 , H01L21/67017
摘要： Aspects of the disclosure pertain to methods of preferentially filling narrow trenches with silicon oxide while not completely filling wider trenches and/or open areas. In embodiments, dielectric layers are deposited by flowing a silicon-containing precursor and ozone into a processing chamber such that a relatively dense first portion of a silicon oxide layer followed by a more porous (and more rapidly etched) second portion of the silicon oxide layer. Narrow trenches are filled with dense material whereas open areas are covered with a layer of dense material and more porous material. Dielectric material in wider trenches may be removed at this point with a wet etch while the dense material in narrow trenches is retained.
摘要翻译：本公开的方面涉及优先用氧化硅填充窄沟槽而不完全填充较宽的沟槽和/或开放区域的方法。在实施例中，通过使含硅前体和臭氧流入处理室来沉积电介质层，使得氧化硅层的相对致密的第一部分，随后是氧化硅层的更多孔（并且更快蚀刻）的第二部分。狭窄的沟槽用致密材料填充，而开放区域被一层致密材料和更多孔的材料覆盖。此时可以通过湿蚀刻在较宽的沟槽中去除介电材料，同时保留窄沟槽中的致密材料。

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