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1. 发明申请

WO2013090030A1 MEMORY ARCHITECTURE FOR READ-MODIFY-WRITE OPERATIONS 审中-公开
标题翻译：用于读取修改操作的存储器架构
公开(公告)号：WO2013090030A1
公开(公告)日：2013-06-20
申请号：PCT/US2012/067400
申请日：2012-11-30
申请人： ADVANCED MICRO DEVICES, INC. , LOH, Gabriel H. , O'CONNOR, James M. , IGNATOWSKI, Michael , JAYASENA, Nuwan S. , BECKMANN, Bradford M.
发明人： LOH, Gabriel H. , O'CONNOR, James M. , IGNATOWSKI, Michael , JAYASENA, Nuwan S. , BECKMANN, Bradford M.
IPC分类号： G06F11/10 , G06F12/08
CPC分类号： G11C5/02 , G06F11/1048
摘要： According to one embodiment, a memory architecture implemented method is provided, where the memory architecture includes a logic chip and one or more memory chips on a single die, and where the method comprises: reading values of data from the one or more memory chips to the logic chip, where the one or more memory chips and the logic chip are on a single die; modifying, via the logic chip on the single die, the values of data; and writing, from the logic chip to the one or more memory chips, the modified values of data.
摘要翻译：根据一个实施例，提供了一种存储器架构实现的方法，其中存储器架构包括逻辑芯片和单个管芯上的一个或多个存储器芯片，并且其中该方法包括：从一个或多个存储器芯片读取数据的值逻辑芯片，其中一个或多个存储器芯片和逻辑芯片在单个芯片上; 通过单个芯片上的逻辑芯片修改数据的值; 并从逻辑芯片向一个或多个存储器芯片写入修改的数据值。

2. 发明申请

WO2015156937A1 MULTI-LEVEL MEMORY HIERARCHY 审中-公开
标题翻译：多级记忆分级
公开(公告)号：WO2015156937A1
公开(公告)日：2015-10-15
申请号：PCT/US2015/019400
申请日：2015-03-09
申请人： ADVANCED MICRO DEVICES, INC.
发明人： HSU, Lisa , O'CONNOR, James M. , SRIDHARAN, Vilas K. , LOH, Gabriel H. , JAYASENA, Nuwan S. , BECKMANN, Bradford M.
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/1009 , G06F2212/283 , G06F2212/651
摘要： Described is a system and method for a multi-level memory hierarchy. Each level is based on different attributes including, for example, power, capacity, bandwidth, reliability, and volatility. In some embodiments, the different levels of the memory hierarchy may use an on-chip stacked dynamic random access memory, (providing fast, high-bandwidth, low-energy access to data) and an off-chip non-volatile random access memory, (providing low-power, high-capacity storage), in order to provide higher-capacity, lower power, and higher-bandwidth performance. The multi-level memory may present a unified interface to a processor so that specific memory hardware and software implementation details are hidden. The multi-level memory enables the illusion of a single-level memory that satisfies multiple conflicting constraints. A comparator receives a memory address from the processor, processes the address and reads from or writes to the appropriate memory level. In some embodiments, the memory architecture is visible to the software stack to optimize memory utilization.
摘要翻译：描述了用于多级存储器层次结构的系统和方法。每个级别都是基于不同的属性，包括功率，容量，带宽，可靠性和波动性。在一些实施例中，存储器层级的不同级别可以使用片上堆叠的动态随机存取存储器（提供对数据的快速，高带宽，低能量访问）和片外非易失性随机存取存储器，（提供低功耗，大容量存储），以提供更高容量，更低功耗和更高带宽的性能。多级存储器可以向处理器呈现统一的接口，从而隐藏特定的存储器硬件和软件实现细节。多级存储器能够实现满足多个冲突约束的单级存储器的错觉。比较器从处理器接收存储器地址，处理地址并读取或写入适当的存储器级别。在一些实施例中，存储器架构对于软件堆栈是可见的以优化存储器利用。

3. 发明申请

WO2018075131A1 MECHANISMS TO IMPROVE DATA LOCALITY FOR DISTRIBUTED GPUS 审中-公开
标题翻译：提高分布式GPUS数据本地化的机制
公开(公告)号：WO2018075131A1
公开(公告)日：2018-04-26
申请号：PCT/US2017/047807
申请日：2017-08-21
申请人： ADVANCED MICRO DEVICES, INC.
发明人： ECKERT, Yasuko , KAYIRAN, Onur , JAYASENA, Nuwan S. , LOH, Gabriel H. , ZHANG, Dong Ping
IPC分类号： G06F9/50
CPC分类号： H04L47/70 , G06F9/5066 , H04L47/50 , H04L67/10 , H04L67/2842 , Y02D10/22 , Y02D10/36
摘要： Systems, apparatuses, and methods for implementing mechanisms to improve data locality for distributed processing units are disclosed. A system includes a plurality of distributed processing units (e.g., GPUs) and memory devices. Each processing unit is coupled to one or more local memory devices. The system determines how to partition a workload into a plurality of workgroups based on maximizing data locality and data sharing. The system determines which subset of the plurality of workgroups to dispatch to each processing unit of the plurality of processing units based on maximizing local memory accesses and minimizing remote memory accesses. The system also determines how to partition data buffer(s) based on data sharing patterns of the workgroups. The system maps to each processing unit a separate portion of the data buffer(s) so as to maximize local memory accesses and minimize remote memory accesses.
摘要翻译：公开了用于实现改善分布式处理单元的数据局部性的机制的系统，设备和方法。系统包括多个分布式处理单元（例如，GPU）和存储器设备。每个处理单元被耦合到一个或多个本地存储器设备。该系统基于最大化数据局部性和数据共享来确定如何将工作负载划分为多个工作组。系统基于最大化本地存储器访问和最小化远程存储器访问来确定要分派给多个处理单元中的每个处理单元的多个工作组中的哪个子集。系统还会根据工作组的数据共享模式确定如何分区数据缓冲区。系统将每个处理单元映射到一个或多个数据缓冲区的单独部分，以最大化本地存储器访问并最小化远程存储器访问。

4. 发明申请

WO2017123284A1 INTERPOSER HAVING A PATTERN OF SITES FOR MOUNTING CHIPLETS 审中-公开
标题翻译：具有用于安装芯片的模式的插入器
公开(公告)号：WO2017123284A1
公开(公告)日：2017-07-20
申请号：PCT/US2016/052769
申请日：2016-09-21
申请人： ADVANCED MICRO DEVICES, INC.
发明人： JAYASENA, Nuwan S. , ROBERTS, David A.
IPC分类号： H01L23/00 , H01L25/065 , H01L23/12
CPC分类号： H01L23/49838 , H01L21/4853 , H01L23/145 , H01L23/147 , H01L23/15 , H01L25/0652 , H01L25/0655 , H01L25/50 , H01L2224/16145 , H01L2224/16227 , H01L2224/81139 , H01L2224/8114 , H01L2225/06513 , H01L2225/06531 , H01L2225/06534 , H01L2225/06589 , H01L2225/06593 , H01L2924/1431 , H01L2924/1432 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/1579 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105
摘要： The described embodiments include an interposer with signal routes located therein. The interposer includes a set of sites arranged in a pattern, each site including a set of connection points. Each connection point in each site is coupled to a corresponding one of the signal routes. Integrated circuit chiplets may be mounted on the sites and signal connectors for mounted integrated circuit chiplets may coupled to some or all of the connection points for corresponding sites, thereby coupling the chiplets to corresponding signal routes. The chiplets may then send and receive signals via the connection points and signal routes. In some embodiments, the set of connection points in each of the sites is the same, i.e., has a same physical layout. In other embodiments, the set of connection points for each site is arranged in one of two or more physical layouts.
摘要翻译：所描述的实施例包括具有位于其中的信号路由的中介层。插入器包括按照图案排列的一组站点，每个站点包括一组连接点。每个站点中的每个连接点都耦合到相应的一个信号路由。集成电路小芯片可以安装在位置上，并且用于安装的集成电路小芯片的信号连接器可以耦合到对应位置的一些或全部连接点，从而将小芯片耦合到对应的信号路由。小芯片然后可以经由连接点和信号路线发送和接收信号。在一些实施例中，每个站点中的一组连接点是相同的，即具有相同的物理布局。在其他实施例中，每个站点的连接点集合被布置在两个或更多个物理布局中的一个中。

5. 发明申请

WO2014025678A1 STACKED MEMORY DEVICE WITH HELPER PROCESSOR 审中-公开
标题翻译：具有帮助处理器的堆叠存储器件
公开(公告)号：WO2014025678A1
公开(公告)日：2014-02-13
申请号：PCT/US2013/053599
申请日：2013-08-05
申请人： ADVANCED MICRO DEVICES, INC.
发明人： WATANABE, Yasuko , LOH, Gabriel H. , O'CONNOR, James Michael , IGNATOWSKI, Michael , JAYASENA, Nuwan S.
IPC分类号： G06F13/16 , G06F13/42
CPC分类号： G06F13/1668 , G06F13/4234 , Y02D10/14 , Y02D10/151
摘要： A processing system (100) comprises one or more processor devices (102) and other system components coupled to a stacked memory device (104) having a set of stacked memory layers (120) and a set of one or more logic layers (122). The set of logic layers implements a helper processor (134) that executes instructions to perform tasks in response to a task request from the processor devices or otherwise on behalf of the other processor devices. The set of logic layers also includes a memory interface (130) coupled to memory cell circuitry (126) implemented in the set of stacked memory layers and coupleable to the processor devices. The memory interface operates to perform memory accesses for the processor devices and for the helper processor. By virtue of the helper processor's tight integration with the stacked memory layers, the helper processor may perform certain memory-intensive operations more efficiently than could be performed by the external processor devices.
摘要翻译：处理系统（100）包括耦合到具有一组堆叠存储器层（120）和一组一个或多个逻辑层（122）的堆叠存储器件（104）的一个或多个处理器设备（102）和其它系统组件，。所述逻辑层集合实现辅助处理器（134），所述辅助处理器执行指令以响应来自所述处理器设备的任务请求或以其他方式代表所述其他处理器设备来执行任务。逻辑层集合还包括耦合到在堆叠存储器层组中实现并可耦合到处理器设备的存储器单元电路（126）的存储器接口（130）。存储器接口操作以对处理器设备和辅助处理器执行存储器访问。由于辅助处理器与堆叠的存储器层的紧密集成，辅助处理器可以比由外部处理器设备执行的更有效地执行某些存储器密集型操作。

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