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1. 发明申请

WO2020123173A1 LOSSY SIGNIFICANCE COMPRESSION WITH LOSSY RESTORATION 审中-公开
公开(公告)号：WO2020123173A1
公开(公告)日：2020-06-18
申请号：PCT/US2019/063981
申请日：2019-12-02
申请人： ADVANCED MICRO DEVICES, INC.
发明人： LOH, Gabriel H.
IPC分类号： G06N20/00 , G06N3/08 , H03M7/30 , H04N19/00
摘要： Described are systems and methods for lossy compression and restoration of data. The raw data is first truncated. Then the truncated data is compressed. The compressed truncated data can then be efficiently stored and/or transmitted using fewer bits. To restore the data, the compressed data is then decompressed and restoration bits are concatenated. The restoration bits are selected to compensate for statistical biasing introduced by the truncation.

2. 发明申请

WO2016028561A1 SYSTEM AND METHOD FOR REVERSE INCLUSION IN MULTILEVEL CACHE HIERARCHY 审中-公开
标题翻译：用于反向包含在多媒体高速缓存中的系统和方法
公开(公告)号：WO2016028561A1
公开(公告)日：2016-02-25
申请号：PCT/US2015/044776
申请日：2015-08-12
申请人： ADVANCED MICRO DEVICES, INC.
发明人： LOH, Gabriel H.
IPC分类号： G06F12/08
CPC分类号： G06F12/128 , G06F12/126 , Y02D10/13
摘要： A processing system (100) having multilevel cache employs techniques for identifying and selecting valid candidate cache lines for eviction from a lower level cache (108) of an inclusive cache hierarchy (102), so as to reduce invalidations resulting from an eviction of a cache line in a lower level cache (110) that also resides in a higher level cache (108). In response to an eviction trigger for a lower level cache, a cache controller (122) identifies candidate cache lines (307) for eviction from the cache lines residing in the lower level cache based on the replacement policy. The cache controller uses residency metadata (310) to identify the candidate cache line as a valid candidate if it does not also reside in the higher cache and as an invalid candidate if it does reside in the higher cache. The cache controller prevents eviction of invalid candidates, so as to avoid unnecessary invalidations in the higher cache while maintaining inclusiveness.
摘要翻译：具有多级高速缓存的处理系统（100）采用用于从包含高速缓存层级（102）的较低级高速缓存（108）识别和选择用于逐出的有效候选高速缓存行的技术，以便减少由高速缓存驱逐引起的无效在较低级别的高速缓存（110）中的线路也驻留在较高级别的高速缓存（108）中。响应于较低级别缓存的逐出触发器，缓存控制器（122）基于替换策略来识别候选高速缓存行（307），以从驻留在较低级别高速缓存中的高速缓存行驱逐。高速缓存控制器使用驻留元数据（310）来将候选高速缓存行识别为有效候选，如果它也不驻留在较高的高速缓存中，并且如果它驻留在较高的高速缓存中则为无效候选。高速缓存控制器防止驱逐无效候选，以避免在高速缓存中不必要的无效，同时保持包容性。

3. 发明申请

WO2014025676A1 STACKED MEMORY DEVICE WITH METADATA MANAGEMENT 审中-公开
标题翻译：具有元数据管理的堆叠存储器件
公开(公告)号：WO2014025676A1
公开(公告)日：2014-02-13
申请号：PCT/US2013/053596
申请日：2013-08-05
申请人： ADVANCED MICRO DEVICES, INC.
发明人： LOH, Gabriel H. , O'CONNOR, James Michael , BECKMANN, Bradford M. , IGNATOWSKI, Michael
IPC分类号： G06F13/16 , G06F11/10
CPC分类号： G06F13/1668 , G06F11/1004 , Y02D10/14
摘要： A processing system (100) comprises one or more processor devices (104) and other system components coupled to a stacked memory device (102) having a set of stacked memory layers (120) and a set of one or more logic layers (122). The set of logic layers implements a metadata manager (134) that offloads metadata management from the other system components. The set of logic layers also includes a memory interface (130) coupled to memory cell circuitry (126) implemented in the set of stacked memory layers and coupleable to the devices external to the stacked memory device. The memory interface operates to perform memory accesses for the external devices and for the metadata manager. By virtue of the metadata manager's tight integration with the stacked memory layers, the metadata manager may perform certain memory-intensive metadata management operations more efficiently than could be performed by the external devices.
摘要翻译：处理系统（100）包括耦合到具有一组堆叠存储器层（120）和一组一个或多个逻辑层（122）的堆叠存储器件（102）的一个或多个处理器设备（104）和其他系统组件，。逻辑层集合实现了从其他系统组件卸载元数据管理的元数据管理器（134）。逻辑层集合还包括耦合到在堆叠存储器层组中实现的存储单元电路（126）的存储器接口（130），并且可耦合到堆叠存储器件外部的器件。存储器接口用于对外部设备和元数据管理器执行存储器访问。由于元数据管理器与堆叠的存储器层的紧密集成，元数据管理器可以比由外部设备执行的更有效地执行某些存储密集型元数据管理操作。

4. 发明申请

WO2015156937A1 MULTI-LEVEL MEMORY HIERARCHY 审中-公开
标题翻译：多级记忆分级
公开(公告)号：WO2015156937A1
公开(公告)日：2015-10-15
申请号：PCT/US2015/019400
申请日：2015-03-09
申请人： ADVANCED MICRO DEVICES, INC.
发明人： HSU, Lisa , O'CONNOR, James M. , SRIDHARAN, Vilas K. , LOH, Gabriel H. , JAYASENA, Nuwan S. , BECKMANN, Bradford M.
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/1009 , G06F2212/283 , G06F2212/651
摘要： Described is a system and method for a multi-level memory hierarchy. Each level is based on different attributes including, for example, power, capacity, bandwidth, reliability, and volatility. In some embodiments, the different levels of the memory hierarchy may use an on-chip stacked dynamic random access memory, (providing fast, high-bandwidth, low-energy access to data) and an off-chip non-volatile random access memory, (providing low-power, high-capacity storage), in order to provide higher-capacity, lower power, and higher-bandwidth performance. The multi-level memory may present a unified interface to a processor so that specific memory hardware and software implementation details are hidden. The multi-level memory enables the illusion of a single-level memory that satisfies multiple conflicting constraints. A comparator receives a memory address from the processor, processes the address and reads from or writes to the appropriate memory level. In some embodiments, the memory architecture is visible to the software stack to optimize memory utilization.
摘要翻译：描述了用于多级存储器层次结构的系统和方法。每个级别都是基于不同的属性，包括功率，容量，带宽，可靠性和波动性。在一些实施例中，存储器层级的不同级别可以使用片上堆叠的动态随机存取存储器（提供对数据的快速，高带宽，低能量访问）和片外非易失性随机存取存储器，（提供低功耗，大容量存储），以提供更高容量，更低功耗和更高带宽的性能。多级存储器可以向处理器呈现统一的接口，从而隐藏特定的存储器硬件和软件实现细节。多级存储器能够实现满足多个冲突约束的单级存储器的错觉。比较器从处理器接收存储器地址，处理地址并读取或写入适当的存储器级别。在一些实施例中，存储器架构对于软件堆栈是可见的以优化存储器利用。

5. 发明申请

WO2014078285A1 TRACKING MEMORY BANK UTILITY AND COST FOR INTELLIGENT POWER UP DECISIONS 审中-公开
标题翻译：跟踪记忆银行的实用性和智能上电决策的成本
公开(公告)号：WO2014078285A1
公开(公告)日：2014-05-22
申请号：PCT/US2013/069607
申请日：2013-11-12
申请人： ADVANCED MICRO DEVICES, INC.
发明人： BRETERNITZ, Mauricio , O'CONNOR, James M. , LOH, Gabriel H. , ECKERT, Yasuko , THOTTETHODI, Mithuna , MANNE, Srilatha , BECKMANN, Bradford M.
IPC分类号： G06F1/26 , G06F12/08
CPC分类号： G06F1/3275 , Y02D10/14 , Y02D50/20
摘要： A device receives an indication that a memory bank is to be powered up, and determines, based on receiving the indication, power scores corresponding to powered down memory banks. Each power score corresponds to a power metric associated with powering up a powered down memory bank. The device powers up a selected memory bank based on the plurality of power scores.
摘要翻译：设备接收到存储器组将被加电的指示，并且基于接收到指示，确定对应于掉电存储器组的功率分数。每个功率分数对应于与断电存储器组的加电相关联的功率度量。设备基于多个功率得分来加电所选择的存储体。

6. 发明申请

WO2013081932A1 A DRAM CACHE WITH TAGS AND DATA JOINTLY STORED IN PHYSICAL ROWS 审中-公开
标题翻译：具有标签和数据的DRAM高速缓存存储在物理路径中
公开(公告)号：WO2013081932A1
公开(公告)日：2013-06-06
申请号：PCT/US2012/066217
申请日：2012-11-21
申请人： ADVANCED MICRO DEVICES, INC.
发明人： LOH, Gabriel H. , HILL, Mark D.
IPC分类号： G06F12/08 , G06F12/12 , G11C7/10
CPC分类号： G06F12/0893 , G06F12/0831 , G06F12/0864 , G06F12/0879 , G06F12/123 , Y02D10/13
摘要： A system and method for efficient cache data access in a large row-based memory of a computing system. A computing system includes a processing unit and an integrated three- dimensional (3D) dynamic random access memory (DRAM). The processing unit uses the 3D DRAM as a cache. Each row of the multiple rows in the memory array banks of the 3D DRAM stores at least multiple cache tags and multiple corresponding cache lines indicated by the multiple cache tags. In response to receiving a memory request from the processing unit, the 3D DRAM performs a memory access according to the received memory request on a given cache line indicated by a cache tag within the received memory request. Rather than utilizing multiple DRAM transactions, a single, complex DRAM transaction may be used to reduce latency and power consumption.
摘要翻译：一种用于在计算系统的大型基于行的存储器中高效缓存数据访问的系统和方法。计算系统包括处理单元和集成三维（3D）动态随机存取存储器（DRAM）。处理单元使用3D DRAM作为高速缓存。 3D DRAM的存储器阵列组中的多行的每一行存储由多个高速缓存标签指示的至少多个高速缓存标签和多个对应的高速缓存行。响应于从处理单元接收到存储器请求，3D DRAM根据在所接收的存储器请求中由高速缓存标签指示的给定高速缓存线上的接收到的存储器请求执行存储器访问。可以使用单个复杂DRAM事务来减少等待时间和功耗，而不是利用多个DRAM事务。

7. 发明申请

WO2020154166A1 CACHE REPLACEMENT BASED ON TRANSLATION LOOKASIDE BUFFER EVICTIONS 审中-公开
公开(公告)号：WO2020154166A1
公开(公告)日：2020-07-30
申请号：PCT/US2020/013856
申请日：2020-01-16
申请人： ADVANCED MICRO DEVICES, INC.
发明人： LOH, Gabriel H. , MOYER, Paul
IPC分类号： G06F12/1027 , G06F12/0895 , G06F12/1009 , G06F12/121
摘要： A processing system adjusts a cache replacement priority of cache lines at a cache based on evictions of entries mapping virtual-to-physical address translations from a translation lookaside buffer (TLB). Upon eviction of a TLB entry, the processing system identifies cache lines corresponding to the physical addresses of the evicted TLB entry and evicts the cache lines or adjusts the cache replacement priority of the cache lines so that their eviction from the cache will be accelerated.

8. 发明申请

WO2019182943A1 STOCHASTIC ROUNDING LOGIC 审中-公开
公开(公告)号：WO2019182943A1
公开(公告)日：2019-09-26
申请号：PCT/US2019/022685
申请日：2019-03-18
申请人： ADVANCED MICRO DEVICES, INC.
发明人： LOH, Gabriel H.
IPC分类号： G06F7/499
摘要： Techniques and circuits are provided for stochastic rounding. In an embodiment, a circuit includes carry-save adder (CSA) logic having three or more CSA inputs, a CSA sum output, and a CSA carry output. One of the three or more CSA inputs is presented with a random number value, while other CSA inputs are presented with input values to be summed. The circuit further includes adder logic having adder inputs and a sum output. The CSA carry output of the CSA logic is coupled with one of the adder inputs of the adder logic, and the CSA sum output of the CSA logic is coupled with another input of the adder inputs of the adder logic. A particular number of most significant bits of the sum output of the adder logic represent a stochastically rounded sum of the input values.

9. 发明申请

WO2019112657A1 ACTIVATION FUNCTION FUNCTIONAL BLOCK FOR ELECTRONIC DEVICES 审中-公开
公开(公告)号：WO2019112657A1
公开(公告)日：2019-06-13
申请号：PCT/US2018/048059
申请日：2018-08-27
申请人： ADVANCED MICRO DEVICES, INC.
发明人： LOH, Gabriel H.
IPC分类号： G06N3/063 , G06N3/04
摘要： An electronic device has an activation function functional block that implements an activation function. During operation, the activation function functional block receives an input including a plurality of bits representing a numerical value. The activation function functional block then determines a range from among a plurality of ranges into which the input falls, each range including a separate portion of possible numerical values of the input. The activation function functional block next generates a result of a linear function associated with the range. Generating the result includes using a separate linear function that is associated with each range in the plurality of ranges to approximate results of the activation function within that range.

10. 发明申请

WO2014100090A1 DIE-STACKED DEVICE WITH PARTITIONED MULTI-HOP NETWORK 审中-公开
标题翻译：具有分层多路网络的DIE堆叠设备
公开(公告)号：WO2014100090A1
公开(公告)日：2014-06-26
申请号：PCT/US2013/075956
申请日：2013-12-18
申请人： ADVANCED MICRO DEVICES, INC.
发明人： THOTTETHODI, Mithuna S. , LOH, Gabriel H.
IPC分类号： H01L23/12
CPC分类号： H04L45/021 , G06F17/5068 , H01L23/481 , H01L23/49838 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L25/0652 , H01L25/18 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2924/1461 , H01L2924/15192 , H04L45/00 , H01L2924/00
摘要： An electronic assembly (100) includes horizontally-stacked die (104, 105, 106, 107) disposed at an interposer (102), and may also include vertically-stacked die (107, 111, 112, 113). The stacked die are interconnected via a multi-hop communication network (101) that is partitioned into a link partition and a router partition. The link partition is at least partially implemented in the metal layers of the interposer for horizontally-stacked die. The link partition may also be implemented in part by the intra-die interconnects (334, 335) in a single die and by the inter-die interconnects (222) connecting vertically-stacked sets of die. The router partition is implemented at some or all of the die disposed at the interposer and comprises the logic (402, 404, 406, 408) that supports the functions that route packets among the components of the processing system (100) via the interconnects of the link partition. The router partition may implement fixed routing, or alternatively may be configurable using programmable routing tables (406) or configurable logic blocks.
摘要翻译：电子组件（100）包括设置在插入器（102）处的水平堆叠的管芯（104,105,106,107），并且还可以包括垂直堆叠的管芯（107,111,112,113）。堆叠的管芯通过分为链路分区和路由器分区的多跳通信网络（101）互连。连接分隔件至少部分地实现在用于水平堆叠的模具的插入件的金属层中。链路分区还可以部分地由单个管芯中的管芯内互连（334,335）以及连接垂直堆叠的管芯组的管芯间互连（222）来实现。路由器分区在设置在插入器处的芯片的部分或全部处被实现，并且包括逻辑（402,404,406,408），其逻辑（402,404,406,408）支持在处理系统（100）的组件之间经由互连链接分区。路由器分区可以实现固定路由，或者可以使用可编程路由表（406）或可配置逻辑块来配置。

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