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1. 发明申请

WO2011032812A1 CONDUCTIVE STRUCTURE FOR NARROW INTERCONNECT OPENINGS 审中-公开
标题翻译：导电结构用于连接开口
公开(公告)号：WO2011032812A1
公开(公告)日：2011-03-24
申请号：PCT/EP2010/062407
申请日：2010-08-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , ROSSNAGEL, Stephen , YANG, Chih-Chao , EDELSTEIN, Daniel , NOGAMI, Takeshi
发明人： ROSSNAGEL, Stephen , YANG, Chih-Chao , EDELSTEIN, Daniel , NOGAMI, Takeshi
IPC分类号： H01L21/768
CPC分类号： H01L21/76871 , H01L21/76846 , H01L21/76868 , H01L21/76883
摘要： An interconnect structure having reduced electrical resistance and a method of forming such an interconnect structure are provided. The interconnect structure includes a dielectric material (24) including at least one opening therein. The at least one opening is filled with an optional barrier diffusion layer (30), a grain growth promotion layer (32), an agglomerated plating seed layer (34'), an optional second plating seed layer a conductive structure (38). The conductive structure which includes a metal-containing conductive material, typically Cu, has a bamboo microstructure and an average grain size of larger than 0.05 microns. In some embodiments, the conductive structure includes conductive grains that have a (111) crystal orientation.
摘要翻译：提供具有降低的电阻的互连结构和形成这种互连结构的方法。互连结构包括其中包括至少一个开口的电介质材料（24）。所述至少一个开口填充有可选的阻挡扩散层（30），晶粒生长促进层（32），聚集的电镀种子层（34'），任选的第二电镀种子层，导电结构（38）。包含含金属的导电材料（通常为Cu）的导电结构具有竹结构，平均晶粒尺寸大于0.05微米。在一些实施例中，导电结构包括具有（111）晶体取向的导电晶粒。

2. 发明申请

WO2010076074A1 INTERCONNECT STRUCTURE WITH IMPROVED DIELECTRIC LINE TO VIA ELECTROMIGRATION RESISTANT INTERFACIAL LAYER AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：具有改进的介电线的互连结构通过电阻接触层及其制造方法
公开(公告)号：WO2010076074A1
公开(公告)日：2010-07-08
申请号：PCT/EP2009/064974
申请日：2009-11-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , BASKER, Veeraraghavan , TONTI, William, Robert , WONG, Keith, Kwong Hon , YANG, Chih-Chao
发明人： BASKER, Veeraraghavan , TONTI, William, Robert , WONG, Keith, Kwong Hon , YANG, Chih-Chao
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/76843 , H01L21/76814 , H01L21/76849 , H01L21/7685 , H01L21/76886 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) (66) that is present at the bottom of a via opening. The via opening is located within a second dielectric material (52') that is located atop a first dielectric material (52) that includes a first conductive material (56) embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.
摘要翻译：提供具有改善的电迁移阻力的互连结构，其包括存在于通孔开口底部的金属界面层（或金属合金层）（66）。通孔开口位于第二介电材料（52'）内，第二电介质材料（52'）位于包括嵌入其中的第一导电材料（56）的第一介电材料（52）的顶部。存在于通孔开口底部的金属界面层（或金属合金层）位于埋在第一电介质内的下面的第一导电材料和嵌入在第二电介质材料内的第二导电材料之间。还提供了制造改进的电迁移电阻互连结构的方法。

3. 发明申请

WO2009098151A1 INTERCONNECT STRUCTURE AND METHOD FOR CU/ULTRA LOW K INTEGRATION 审中-公开
标题翻译：用于CU /超低K积分的互连结构和方法
公开(公告)号：WO2009098151A1
公开(公告)日：2009-08-13
申请号：PCT/EP2009/050918
申请日：2009-01-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , MURRAY, Conal, Eugene , YANG, Chih-Chao
发明人： MURRAY, Conal, Eugene , YANG, Chih-Chao
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L21/76808 , H01L21/76805 , H01L21/76814 , H01L21/76835 , H01L21/76843
摘要： A semiconductor structure is provided that includes a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein; a dielectric capping layer located on the first dielectric material and some, but not all, portions of the at least one conductive feature; and an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein, wherein the conductively filled via is in contact with an exposed surface of the at least one conductive feature of the first interconnect level by an anchoring area. Moreover, the conductively filled via and conductively filled line of the inventive structure are separated from the second dielectric material by a single continuous diffusion barrier layer. As such, the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line. A method of forming such an interconnect structure is also provided.
摘要翻译：提供了一种半导体结构，其包括下互连级，其包括具有嵌入其中的至少一个导电特征的第一介电材料; 位于所述第一电介质材料上的电介质覆盖层以及所述至少一个导电特征的一些但不是全部的部分; 以及包括具有至少一个导电填充通孔的第二介电材料和布置在其中的上覆导电填充线的上部互连水平，其中所述导电填充的通孔与所述第一互连水平的所述至少一个导电特征的暴露表面接触通过锚定区域。此外，本发明结构的导电填充通孔和导电填充线通过单个连续扩散阻挡层与第二介电材料分离。因此，第二电介质材料在与导电填充线相邻的区域中不包括受损区域。还提供了一种形成这种互连结构的方法。

4. 发明申请

WO2007051718A2 STRUCTURE AND METHOD FOR MONITORING STRESS-INDUCED DEGRADATION OF CONDUCTIVE INTERCONNECTS 审中-公开
标题翻译：用于监测导电互连的应力诱导降解的结构和方法
公开(公告)号：WO2007051718A2
公开(公告)日：2007-05-10
申请号：PCT/EP2006/067590
申请日：2006-10-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , CHANDA, Kaushik , NGUYEN, Du, Binh , MCLAUGHLIN, Paul, Stephen , FILIPPI, Ronald , RATHORE, Hazara, Singh , CLEVENGER, Lawrence , YANG, Chih-Chao , COWLEY, Andrew , GILL, Jason, Paul , LI, Baozhen , LEE, Tom , AGARWALA, Birendra , SULLIVAN, Timothy, Dooling
发明人： CHANDA, Kaushik , NGUYEN, Du, Binh , MCLAUGHLIN, Paul, Stephen , FILIPPI, Ronald , RATHORE, Hazara, Singh , CLEVENGER, Lawrence , YANG, Chih-Chao , COWLEY, Andrew , GILL, Jason, Paul , LI, Baozhen , LEE, Tom , AGARWALA, Birendra , SULLIVAN, Timothy, Dooling
IPC分类号： G01R31/28 , H01L23/544
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (µm).
摘要翻译：提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。至少一些导电互连件包括金属板，金属连接线和上金属通孔。所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。上金属通孔在与一个外围边缘水平位移至少约3微米（μm）的位置处具有与金属连接线接触的底端。

5. 发明申请

WO2009106520A1 BILAYER METAL CAPPING LAYER FOR INTERCONNECT APPLICATIONS 审中-公开
标题翻译：双层金属覆盖层用于互连应用
公开(公告)号：WO2009106520A1
公开(公告)日：2009-09-03
申请号：PCT/EP2009/052160
申请日：2009-02-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , NITTA, Satyanarayana, Venkata , YANG, Chih-Chao
发明人： NITTA, Satyanarayana, Venkata , YANG, Chih-Chao
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/76849 , H01L21/76805 , H01L21/76814 , H01L21/76843 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The invention provides semiconductor interconnect structures that have improved reliability and technology extendibility. In the present invention, a second metallic capping layer (76) is located on a surface of a first metallic cap layer (60) which is, in turn, located on a surface of the conductive feature (58) embedded within a first dielectric material (54). Both the first and second metallic capping layers are located beneath an opening, e.g., a via opening, which is present within an overlying second dielectric material (68). The second metallic capping layer protects the first dielectric capping layer from being removed (either completely or partially) during subsequent processing steps. Interconnect structures including via gouging features as well as non-via gouging features are disclosed. The present invention provides methods of fabricating such semiconductor interconnect structures.
摘要翻译：本发明提供了具有改进的可靠性和技术可扩展性的半导体互连结构。在本发明中，第二金属覆盖层（76）位于第一金属覆盖层（60）的表面上，第一金属覆盖层（60）又位于导电特征（58）的嵌入第一介电材料（54）。第一和第二金属覆盖层都位于开口下方，例如存在于覆盖的第二介电材料（68）内的通孔开口。第二金属覆盖层保护第一介电覆盖层在随后的处理步骤期间被去除（完全或部分地）。公开了包括通过气刨特征以及非通孔气刨功能的互连结构。本发明提供制造这种半导体互连结构的方法。

6. 发明申请

WO2007137969A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES HAVING HIGH-Q WAFER BACK-SIDE CAPACITORS 审中-公开
标题翻译：具有高Q波形背面电容器的半导体集成电路器件
公开(公告)号：WO2007137969A1
公开(公告)日：2007-12-06
申请号：PCT/EP2007/054941
申请日：2007-05-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , CLEVENGER, Lawrence , DALTON, Timothy, Joseph , HSU, Louis, Lu-Chen , RADENS, Carl, John , RAMACHANDRAN, Vidhya , WONG, Keith, Kwong Hon , YANG, Chih-Chao
发明人： CLEVENGER, Lawrence , DALTON, Timothy, Joseph , HSU, Louis, Lu-Chen , RADENS, Carl, John , RAMACHANDRAN, Vidhya , WONG, Keith, Kwong Hon , YANG, Chih-Chao
IPC分类号： H01L21/8242 , H01L27/12
CPC分类号： H01L21/84 , H01L21/76898 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L2924/0002 , Y10S438/957 , H01L2924/00
摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semico nductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.
摘要翻译：提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。

7. 发明申请

WO2012045509A1 3D VIA CAPACITOR WITH A FLOATING CONDUCTIVE PLATE FOR IMPROVED RELIABILITY 审中-公开
标题翻译：具有改进可靠性的浮动导电板的3D VIA电容器
公开(公告)号：WO2012045509A1
公开(公告)日：2012-04-12
申请号：PCT/EP2011/064079
申请日：2011-08-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , CHEN, Fen , YANG, Chih-Chao , LI, Baozhen
发明人： CHEN, Fen , YANG, Chih-Chao , LI, Baozhen
IPC分类号： H01L21/02 , H01L23/522 , H01L21/768
CPC分类号： H01L23/5223 , H01L21/76805 , H01L25/0657 , H01L28/91 , H01L2225/06513 , H01L2225/06544 , H01L2225/06565 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer (110) on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode (118a, b) overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer (120) overlies the first electrode. A first conductive plate (122) is over the first high-k dielectric material layer. A second high-k dielectric material layer (126) overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode (128) is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided.
摘要翻译：本发明提供一种3D通孔电容器及其形成方法。电容器包括在衬底上的绝缘层（110）。绝缘层具有通孔，其具有侧壁和底部。第一电极（118a，b）覆盖通孔的侧壁和底部的至少一部分。第一高k电介质材料层（120）覆盖在第一电极上。第一导电板（122）在第一高k电介质材料层之上。第二高k介电材料层（126）覆盖在第一导电板上并留下未填充的通孔的剩余部分。在通孔的剩余部分中形成第二电极（128）。第一导电板基本上平行于第一电极并且不与第一和第二电极接触。还提供了这种3D通孔电容器的阵列。

8. 发明申请

WO2012010479A1 METHOD AND STRUCTURE TO IMPROVE THE CONDUCTIVITY OF NARROW COPPER FILLED VIAS 审中-公开
标题翻译：提高纳米铜填充电导率的方法与结构
公开(公告)号：WO2012010479A1
公开(公告)日：2012-01-26
申请号：PCT/EP2011/061959
申请日：2011-07-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , MCFEELY, Fenton, Read , YANG, Chih-Chao
发明人： MCFEELY, Fenton, Read , YANG, Chih-Chao
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H05K1/09 , H01L21/76846 , H01L21/76864 , H01L21/76873 , H01L21/76883 , H01L23/53238 , H01L2221/1089 , H01L2924/0002 , Y10T29/49126 , Y10T29/49165 , H01L2924/00
摘要： Techniques for improving the conductivity of copper (Cu)-filled vias are provided. In one aspect, a method of fabricating a Cu-filled via is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A thin seed Cu layer is deposited on the Ru layer. A first anneal is performed to increase a grain size of the seed Cu layer. The via is filled with additional Cu. A second anneal is performed to increase the grain size of the additional Cu.
摘要翻译：提供了提高铜（Cu）填充通孔电导率的技术。一方面，提供了制造填充铜的通孔的方法。该方法包括以下步骤。在电介质中蚀刻通孔。通孔内有一个扩散屏障。薄的钌（Ru）层共形沉积到扩散阻挡层上。在Ru层上沉积薄的种子Cu层。进行第一退火以增加种子Cu层的晶粒尺寸。通孔填充有额外的铜。进行第二次退火以增加附加Cu的晶粒尺寸。

9. 发明申请

WO2009019063A1 ELECTROMIGRATION RESISTANT INTERCONNECT STRUCTURE 审中-公开
标题翻译：电阻互连结构
公开(公告)号：WO2009019063A1
公开(公告)日：2009-02-12
申请号：PCT/EP2008/057591
申请日：2008-06-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , YANG, Haining , YANG, Chih-Chao , WONG, Keith, Kwong Hon
发明人： YANG, Haining , YANG, Chih-Chao , WONG, Keith, Kwong Hon
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/76834 , H01L21/76849 , H01L21/76883
摘要： A line trench is formed in a dielectric layer that may contain an interlayer dielectric material. A metal liner is formed on the sidewalls a nd the bottom surface of the line trench. A conductive metal is deposited within a remaining portion of the line trench at least up to a top surface of the dielectric layer and planarized to form a metal line in the line trench. The metal line is recessed by a recess etch below the top surface of the dielectric layer. A dielectric line cap or a metallic line cap is form ed by deposition of a diel ectric cap layer or a metallic cap layer, followed by planarization of the dielectric or metallic cap layer. The dielectric line cap or the metallic line cap applies a highly compressive stress on the underlying metal line, which increases electro migration resistance of the metal line.
摘要翻译：在可以包含层间绝缘材料的电介质层中形成线沟槽。金属衬垫形成在线沟槽的侧壁和底表面上。导电金属沉积在至少直到电介质层的顶表面的线沟槽的剩余部分内，并平坦化以在线沟槽中形成金属线。金属线通过在电介质层的顶表面下方的凹陷蚀刻凹陷。介质线帽或金属线帽通过沉积二层帽层或金属帽层形成，随后平坦化电介质或金属帽层。介质线帽或金属线帽在下面的金属线上施加高度压缩应力，这增加了金属线的电迁移电阻。

10. 发明申请

WO2008064963A1 DUAL LINER CAPPING LAYER INTERCONNECT STRUCTURE 审中-公开
标题翻译：双层封装层互连结构
公开(公告)号：WO2008064963A1
公开(公告)日：2008-06-05
申请号：PCT/EP2007/061481
申请日：2007-10-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , WONG, Keith, Kwong Hon , YANG, Chih-Chao , YANG, Haining
发明人： WONG, Keith, Kwong Hon , YANG, Chih-Chao , YANG, Haining
IPC分类号： H01L21/768
CPC分类号： H01L21/76829 , H01L21/76834 , Y10S438/927
摘要： A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms (5 nm) in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.
摘要翻译： Cu互连上的高拉伸应力覆盖层，以减少Cu /介电界面处的铜迁移和原子排空。高拉伸电介质膜通过沉积多层薄的电介质材料而形成，每层的厚度约为50埃（5纳米）。每个电介质层在沉积每个后续介电层之前进行等离子体处理，使得电介质盖具有内部拉伸应力。

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