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1. 发明申请

WO2006124525A1 SELECTIVE APPLICATION OF PROGRAM INHIBIT SCHEMES IN NON-VOLATILE MEMORY 审中-公开
标题翻译：在非易失性存储器中选择性应用程序抑制方案
公开(公告)号：WO2006124525A1
公开(公告)日：2006-11-23
申请号：PCT/US2006/018278
申请日：2006-05-11
申请人： SANDISK CORPORATION , WAN, Jun , LUTZE, Jeffrey , HIGASHITANI, Masaaki , HEMINK, Gerrit, Jan , OOWADA, Ken , CHEN, Jian , GONGWER, Geoffrey, S.
发明人： WAN, Jun , LUTZE, Jeffrey , HIGASHITANI, Masaaki , HEMINK, Gerrit, Jan , OOWADA, Ken , CHEN, Jian , GONGWER, Geoffrey, S.
IPC分类号： G11C16/34 , G11C11/56
CPC分类号： G11C16/3418
摘要： A non-volatile memory system is programmed so as to reduce or avoid program disturb. In accordance with one embodiment, multiple program inhibit schemes are employed for a single non-volatile memory system. Program inhibit schemes are selected based on the word line being programmed. Certain program inhibit schemes have been discovered to better minimize or eliminate program disturb at select word lines. In one embodiment, selecting a program inhibit scheme includes selecting a program voltage pulse ramp rate. Different ramp rates have been discovered to better minimize program disturb when applied to select word lines. In another embodiment, the temperature of a memory system is detected before or during a program operation. A program inhibit scheme can be selected based on the temperature of the system.
摘要翻译：编程非易失性存储器系统以减少或避免编程干扰。根据一个实施例，单个非易失性存储器系统采用多个程序禁止方案。基于正在编程的字线选择编程抑制方案。已经发现某些程序禁止方案能够更好地最小化或消除选择字线上的程序干扰。在一个实施例中，选择编程禁止方案包括选择编程电压脉冲斜率。在应用于选择字线时，已经发现了不同的斜率以更好地最小化程序干扰。在另一个实施例中，在程序操作之前或期间检测存储器系统的温度。可以基于系统的温度来选择程序禁止方案。

2. 发明申请

WO2007076492A2 METHODS AND SYSTEMS FOR WRITING NON-VOLATILE MEMORIES FOR INCREASED ENDURANCE 审中-公开
标题翻译：用于写入非易失性存储器以增加耐久性的方法和系统
公开(公告)号：WO2007076492A2
公开(公告)日：2007-07-05
申请号：PCT/US2006/062579
申请日：2006-12-22
申请人： SANDISK CORPORATION , PINTO, Yosi , GONGWER, Geoffrey S. , HONEN, Oren
发明人： PINTO, Yosi , GONGWER, Geoffrey S. , HONEN, Oren
CPC分类号： G11C16/349 , G11C16/3495 , H03K21/403
摘要： A memory system that incorporates methods of amplifying the lifetime of a counter made up of memory elements, such as EEPROM cells, having finite endurance. A relatively small memory made up of a number of individually accessible write segments, where, depending on the embodiment, each write segment is made up of a single memory cell or a small number of cells (e.g., a byte). A count is encoded so that it is distributed across a number of fields, each associated with one of the write segments, such that as the count is incremented only a single field (or, in the single bit embodiments, occasionally more than one field) is changed and that these changes are evenly distributed across the fields. The changed field is then written to the corresponding segment, while the other write segments are unchanged. Consequently, the number of rewrites to a given write segment is decreased, and the lifetime correspondingly increased, by a factor corresponding to the number of write segments used.
摘要翻译：一种存储系统，其包含放大由具有有限耐久性的诸如EEPROM单元之类的存储元件组成的计数器的寿命的方法。由多个单独访问的写入段构成的相对小的存储器，其中根据实施例，每个写入段由单个存储器单元或少量单元（例如，一个字节）组成。计数被编码，使得其分布在多个字段中，每个字段与写入段之一相关联，使得当计数仅增加一个字段（或者在单个实施例中，偶尔地多于一个字段）时，改变了这些变化是均匀地分布在各个领域。然后将更改的字段写入相应的段，而其他写段不变。因此，给定写入段的重写次数减少，并且寿命相应地增加了与所使用的写入段数相对应的因子。

3. 发明申请

WO2004021576A1 SYMBOL FREQUENCY LEVELING IN A DATA STORAGE SYSTEM 审中-公开
标题翻译：数据存储系统中的符号频率调整
公开(公告)号：WO2004021576A1
公开(公告)日：2004-03-11
申请号：PCT/US2003/027322
申请日：2003-08-29
申请人： SANDISK CORPORATION , GONGWER, Geoffrey, S. , GROSS, Stephen, J.
发明人： GONGWER, Geoffrey, S. , GROSS, Stephen, J.
IPC分类号： H03M7/00
CPC分类号： H03M5/00 , H03M7/40
摘要： Methods and apparatus for transforming data into a format which may be efficiently stored in a non-volatile memory are disclosed. According to one aspect of the present invention, a method for storing information of a first data format in a memory system includes generating statistics associated with the first data format, and transforming the information from the first data format to a second data format using the statistics. Once the information is transformed into the second data format, the information is stored into a memory. Storing the information in the second data format in the memory includes storing an identifier that identifies a transformation used to transform the information to the second data format. In one embodiment, costs associated with storing the information in the second data format are less than or equal to costs associated with storing the information in the first data format.
摘要翻译：公开了将数据转换成可以有效地存储在非易失性存储器中的格式的方法和装置。根据本发明的一个方面，一种用于将第一数据格式的信息存储在存储器系统中的方法包括生成与第一数据格式相关联的统计信息，以及使用统计信息将信息从第一数据格式转换为第二数据格式。一旦信息被转换成第二数据格式，信息被存储到存储器中。以第二数据格式存储在存储器中的信息包括存储识别用于将信息变换为第二数据格式的变换的标识符。在一个实施例中，与以第二数据格式存储信息相关联的成本小于或等于与以第一数据格式存储信息相关联的成本。

4. 发明申请

WO2004114313A2 TRACKING CELLS FOR A MEMORY SYSTEM 审中-公开
标题翻译：跟踪记忆系统的细胞
公开(公告)号：WO2004114313A2
公开(公告)日：2004-12-29
申请号：PCT/US2004/018172
申请日：2004-06-07
申请人： SANDISK CORPORATION , GUTERMAN, Daniel, C. , GROSS, Stephen, J. , KHALID, Shahzad , GONGWER, Geoffrey, S.
发明人： GUTERMAN, Daniel, C. , GROSS, Stephen, J. , KHALID, Shahzad , GONGWER, Geoffrey, S.
IPC分类号： G11C11/00
CPC分类号： G11C16/26 , G11C11/5621 , G11C16/349
摘要： Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells 5 provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading.

5. 发明申请

WO2003041083A1 ERROR MANAGEMENT FOR WRITABLE TRACKING STORAGE UNITS STORING REFERENCE VALUES 审中-公开
标题翻译：可写跟踪存储单元的错误管理存储参考值
公开(公告)号：WO2003041083A1
公开(公告)日：2003-05-15
申请号：PCT/US2002/034942
申请日：2002-10-30
申请人： SANDISK CORPORATION , GONGWER, Geoffrey, S. , KHALID, Shahzad, B. , GUTERMAN, Daniel, C.
发明人： GONGWER, Geoffrey, S. , KHALID, Shahzad, B. , GUTERMAN, Daniel, C.
IPC分类号： G11C7/14
CPC分类号： G11C16/349 , G11C11/5621 , G11C11/5642 , G11C16/28 , G11C29/00
摘要： A memory system (e.g., memory card) having error management for stored levels (e.g., reference levels) used in discrimination of logic levels for data storage units providing data storage is disclosed. The stored levels can be stored in predetermined storage units (e.g., writable tracking storage units) in the memory system. The memory system is typically a non-volatile memory product or device that provides binary or multi-state data storage.
摘要翻译：公开了一种对提供数据存储的数据存储单元的逻辑电平进行辨别的存储电平（例如参考电平）的错误管理的存储器系统（例如，存储卡）。存储的电平可以存储在存储器系统中的预定存储单元（例如，可写跟踪存储单元）中。存储器系统通常是提供二进制或多状态数据存储的非易失性存储器产品或设备。

6. 发明申请

WO2007076492A3 METHODS AND SYSTEMS FOR WRITING NON-VOLATILE MEMORIES FOR INCREASED ENDURANCE 审中-公开
标题翻译：用于增加耐力的非易失性记忆的方法和系统
公开(公告)号：WO2007076492A3
公开(公告)日：2007-11-29
申请号：PCT/US2006062579
申请日：2006-12-22
申请人： SANDISK CORP , PINTO YOSI , GONGWER GEOFFREY S , HONEN OREN
发明人： PINTO YOSI , GONGWER GEOFFREY S , HONEN OREN
IPC分类号： G11C16/34 , H03K21/40
CPC分类号： G11C16/349 , G11C16/3495 , H03K21/403
摘要： A memory system that incorporates methods of amplifying the lifetime of a counter made up of memory elements, such as EEPROM cells, having finite endurance. A relatively small memory made up of a number of individually accessible write segments, where, depending on the embodiment, each write segment is made up of a single memory cell or a small number of cells (e.g., a byte). A count is encoded so that it is distributed across a number of fields, each associated with one of the write segments, such that as the count is incremented only a single field (or, in the single bit embodiments, occasionally more than one field) is changed and that these changes are evenly distributed across the fields. The changed field is then written to the corresponding segment, while the other write segments are unchanged. Consequently, the number of rewrites to a given write segment is decreased, and the lifetime correspondingly increased, by a factor corresponding to the number of write segments used.
摘要翻译：一种内存系统，结合了放大由有限寿命的存储器元件组成的计数器的寿命的方法，例如EEPROM单元。由许多单独可访问的写段组成的相对较小的存储器，其中取决于实施例，每个写段由单个存储器单元或少量单元（例如，字节）组成。计数被编码以便它分布在多个字段中，每个字段与其中一个写入段相关联，使得随着计数仅递增一个字段（或者在单个位实施例中，偶尔多于一个字段）已更改，并且这些更改均匀分布在各个字段中。然后将更改的字段写入相应的段，而其他写段不变。因此，对给定写段的重写次数减少了，并且寿命相应地增加了与所使用的写段数对应的因子。

7. 发明申请

WO2004114313A3 TRACKING CELLS FOR A MEMORY SYSTEM 审中-公开
公开(公告)号：WO2004114313A3
公开(公告)日：2004-12-29
申请号：PCT/US2004/018172
申请日：2004-06-07
申请人： SANDISK CORPORATION , GUTERMAN, Daniel, C. , GROSS, Stephen, J. , KHALID, Shahzad , GONGWER, Geoffrey, S.
发明人： GUTERMAN, Daniel, C. , GROSS, Stephen, J. , KHALID, Shahzad , GONGWER, Geoffrey, S.
IPC分类号： G11C11/56
摘要： Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells 5 provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading.

8. 发明申请

WO2003100787A1 EFFICIENT READ, WRITE METHOD FOR PIPELINE MEMORY 审中-公开
标题翻译：有效读取，管道存储器的写入方法
公开(公告)号：WO2003100787A1
公开(公告)日：2003-12-04
申请号：PCT/US2003/005214
申请日：2003-02-20
申请人： SANDISK CORPORATION , GONGWER, Geoffrey, S.
发明人： GONGWER, Geoffrey, S.
IPC分类号： G11C7/10
CPC分类号： G11C7/1039
摘要： Methods and apparatus for efficiently writing data to and reading data from multi-state memory cells. According to one aspect of the present invention, a memory system includes a first storage element, a data source, a first element, a second element, and a ripple clock. The data source provides a plurality of bits to be stored in the first storage element, and the first element receives a first bit from the data source, and also clocks the first bit into the second element. The first element then receives a second bit of the plurality of bits from the data source substantially while the first bit is being stored into the first storage element. The ripple clock enables access to the first element and the second element such that the first bit and the second bit may be pipelined.
摘要翻译：用于有效地将数据写入并从多状态存储器单元读取数据的方法和装置。根据本发明的一个方面，存储系统包括第一存储元件，数据源，第一元件，第二元件和纹波时钟。数据源提供要存储在第一存储元件中的多个比特，并且第一元素从数据源接收第一比特，并且还将第一比特计时到第二个元素。然后，第一元素从数据源接收多个比特的第二比特，同时第一比特被存储到第一个存储元素中。纹波时钟允许访问第一元件和第二元件，使得第一位和第二位可以被流水线化。

9. 发明申请

WO1995019646A1 INPUT/OUTPUT TRANSISTORS WITH OPTIMIZED ESD PROTECTION 审中-公开
标题翻译：具有优化的ESD保护的输入/输出晶体管
公开(公告)号：WO1995019646A1
公开(公告)日：1995-07-20
申请号：PCT/US1995000580
申请日：1995-01-12
申请人： ATMEL CORPORATION , RANDAZZO, Todd, A. , LARSEN, Bradley, J. , GONGWER, Geoffrey, S.
发明人： ATMEL CORPORATION
IPC分类号： H01L27/01
CPC分类号： H01L29/78 , H01L27/0266 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： An apparatus providing electrostatic discharge (ESD) protection in an input/output transistor. Disposed near the gate (35) and the surface of the substrate (25) is a lightly doped region (105). A sidewall oxide layer (45) is selectively etched to extend laterally from a gate a significant amount. A heavily doped source (70) and drain (75) are implanted in the substrate where the drain, and possibly the source are separated from the gate by the significant extent of the sidewall oxide.
摘要翻译：一种在输入/输出晶体管中提供静电放电（ESD）保护的装置。设在栅极（35）附近并且衬底（25）的表面是轻掺杂区域（105）。选择性地蚀刻侧壁氧化物层（45）以从栅极横向延伸大量。重掺杂源（70）和漏极（75）注入到衬底中，其中漏极和可能的源极与栅极分离出大量的侧壁氧化物。

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