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1. 发明申请

WO2005125130A2 COMMUNICATION CHANNEL CALIBRATION USING FEEDBACK 审中-公开
标题翻译：使用反馈通信通道校准
公开(公告)号：WO2005125130A2
公开(公告)日：2005-12-29
申请号：PCT/US2005/020208
申请日：2005-06-08
申请人： RAMBUS, INC. , KIM, Jun , RICHARDSON, Wayne, S. , CHIU, Glenn
发明人： KIM, Jun , RICHARDSON, Wayne, S. , CHIU, Glenn
IPC分类号： H04L12/56
CPC分类号： H04B17/11 , H04L5/1438 , H04L25/03343 , H04L2025/03802
摘要： A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.
摘要翻译：用于校准耦合第一和第二组件的通信信道的方法包括在第二组件上传输数据信号从第一分量到通信信道上的第二分量，以及感测数据信号的相位等特性。关于感测到的特性的信息使用辅助信道反馈到第一分量。响应于该信息，在第一组件上调整用于发射机的可调参数，例如相位。而且，感测从第二组件上的发射机接收到的数据信号的特性，并用于调整第一组件上的接收机的可调参数。

2. 发明申请

WO2010017015A1 REQUEST-COMMAND ENCODING FOR REDUCED-DATA-RATE TESTING 审中-公开
标题翻译：要求减少数据速率测试的请求命令编码
公开(公告)号：WO2010017015A1
公开(公告)日：2010-02-11
申请号：PCT/US2009/051081
申请日：2009-07-17
申请人： RAMBUS INC. , KASAMSETTY, Kishore, Ven , RICHARDSON, Wayne, S. , KNORPP, Kurt , WARE, Frederick, A.
发明人： KASAMSETTY, Kishore, Ven , RICHARDSON, Wayne, S. , KNORPP, Kurt , WARE, Frederick, A.
IPC分类号： G11C29/16 , G11C29/18
CPC分类号： G11C29/16 , G11C29/028 , G11C29/12015 , G11C29/18 , G11C29/56012
摘要： Embodiments of a memory device are described. This memory device includes a signal connector which is electrically coupled to a command/address (CA) link, and an interface circuit, which is electrically coupled to the signal connector, and which receives CA packets via the CA link. A given CA packet includes an address field having address information corresponding to one or more storage locations in the memory device. Moreover, the memory device includes control logic having two operating modes, where, during a first operating mode, the control logic decodes address information in the CA packets using full-field sampling, and, during the second operating mode, the control logic decodes a portion of the address information in the CA packets using sub-field sampling.
摘要翻译：描述存储器件的实施例。该存储装置包括电连接到命令/地址（CA）链路的信号连接器和电耦合到信号连接器并且经由CA链路接收CA分组的接口电路。给定的CA分组包括具有与存储设备中的一个或多个存储位置相对应的地址信息的地址字段。此外，存储器件包括具有两种操作模式的控制逻辑，其中在第一操作模式期间，控制逻辑使用全场采样来解码CA分组中的地址信息，并且在第二操作模式期间，控制逻辑解码 CA分组中的部分地址信息使用子场采样。

3. 发明申请

WO2006058200A3 MICRO-THREADED MEMORY 审中-公开
公开(公告)号：WO2006058200A3
公开(公告)日：2006-06-01
申请号：PCT/US2005/042722
申请日：2005-11-23
申请人： RAMBUS INC. , WARE, Frederick, A. , HAMPEL, Craig, E. , RICHARDSON, Wayne, S. , BELLOWS, Chad, A. , LAI, Lawrence
发明人： WARE, Frederick, A. , HAMPEL, Craig, E. , RICHARDSON, Wayne, S. , BELLOWS, Chad, A. , LAI, Lawrence
IPC分类号： G11C7/22
摘要： A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

4. 发明申请

WO2006039106A1 MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTERGRATED CIRCUIT MEMORY DEVICE 审中-公开
标题翻译：包括集成电路存储器件的多字段寻址模式存储器系统
公开(公告)号：WO2006039106A1
公开(公告)日：2006-04-13
申请号：PCT/US2005/032770
申请日：2005-09-12
申请人： RAMBUS INC. , WARE, Frederick, A. , LAI, Lawrence , BELLOWS, Chad, A. , RICHARDSON, Wayne, S.
发明人： WARE, Frederick, A. , LAI, Lawrence , BELLOWS, Chad, A. , RICHARDSON, Wayne, S.
IPC分类号： G11C8/12 , G11C8/16
CPC分类号： G11C8/10 , G11C8/12 , G11C8/16
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. During a third mode of operation, a first plurality of storage cells in a first row of storage cells in a first memory bank is accessible in response to a first column address. A second plurality of storage cells in a second row of storage cells in a second bank is accessible in response to a second column address. A third plurality of storage cells in the first row of storage cells is accessible in response to a third column address and a fourth plurality of storage cells in the second row of storage cells is accessible in response to a fourth column address. The first and second column addresses are in a first request packet and the third and fourth column addresses are in a second request packet provided by the master device.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。集成电路存储器件包括一个接口和列解码器，以访问存储单元行或存储体中的页面。在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。在第三操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元中的第一多个存储单元。响应于第二列地址，可访问第二存储体中第二行存储单元中的第二多个存储单元。第一行存储单元中的第三多个存储单元响应于第三列地址而可访问，并且第二行存储单元中的第四多个存储单元响应于第四列地址而可访问。第一列地址和第二列地址在第一请求分组中，并且第三和第四列地址在由主设备提供的第二请求分组中。

5. 发明申请

WO2006023391A1 MEMORY DEVICE HAVING STAGGERED MEMORY OPERATIONS 审中-公开
标题翻译：具有存储器存储器操作的存储器件
公开(公告)号：WO2006023391A1
公开(公告)日：2006-03-02
申请号：PCT/US2005/028728
申请日：2005-08-11
申请人： RAMBUS INC. , LAI, Lawrence , RICHARDSON, Wayne, S. , BELLOWS, Chad, A.
发明人： LAI, Lawrence , RICHARDSON, Wayne, S. , BELLOWS, Chad, A.
IPC分类号： G11C7/10 , G11C7/22 , G11C8/12
CPC分类号： G11C7/1042 , G11C7/22 , G11C8/12 , G11C2207/2227
摘要： A memory system includes logical banks divided into sub-banks or collections of sub-banks. The memory system responds to memory-access requests (e.g., read and write) directed to a given logical bank by sequentially accessing sub-banks or collections of sub-banks. Sequential access reduces the impact of power-supply spikes induced by memory operations, and thus facilitates improved system performance. Some embodiments of the memory system combine sequential sub-bank access with other performance-enhancing features, such as wider power buses or increased bypass capacitance, to further enhance performance.
摘要翻译：记忆系统包括分为子银行或子银行集合的逻辑银行。存储器系统通过顺序地访问子银行或子银行集合来响应指向给定逻辑银行的存储器访问请求（例如，读取和写入）。顺序访问减少了由存储器操作引起的电源尖峰的影响，从而有助于提高系统性能。存储器系统的一些实施例将顺序的子银行访问与诸如更宽的电源总线或增加的旁路电容的其他性能增强特征相结合，以进一步提高性能。

6. 发明申请

WO2013085695A1 EVENT-DRIVEN CLOCK DUTY CYCLE CONTROL 审中-公开
标题翻译：事件驱动时钟周期控制
公开(公告)号：WO2013085695A1
公开(公告)日：2013-06-13
申请号：PCT/US2012/065445
申请日：2012-11-16
申请人： RAMBUS INC.
发明人： CHAU, Pak, Shing , RICHARDSON, Wayne, S. , KIM, Jun
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K3/012 , H03K3/017
摘要： Duty cycle error vectors that indicate both the magnitude and direction of the duty cycle error relative to a desired duty cycle are generated within a duty cycle measurement circuit, enabling threshold-based determination of whether duty cycle adjustment is necessary, refraining from power-consuming adjustment and follow-up measurement in those cases where the duty cycle is within a target range. When duty cycle adjustment is deemed necessary, the magnitude of the duty cycle error indicated by the duty cycle error vector may be applied to effect proportional rather than incremental duty cycle adjustment, quickly returning the clock duty cycle to a target range.
摘要翻译：在占空比测量电路内产生指示相对于期望占空比的占空比误差的大小和方向的占空比误差矢量，使得能够基于阈值确定是否需要占空比调整，避免功耗调节在占空比在目标范围内的情况下进行跟踪测量。当认为有必要进行占空比调整时，由占空比误差矢量表示的占空比误差的大小可以用于实现比例而不是增量占空比调整，从而快速地将时钟占空比返回到目标范围。

7. 发明申请

WO1998028747A1 MEMORY AND METHOD FOR SENSING SUB-GROUPS OF MEMORY ELEMENTS 审中-公开
标题翻译：用于感测存储元件子组的记忆和方法
公开(公告)号：WO1998028747A1
公开(公告)日：1998-07-02
申请号：PCT/US1997023076
申请日：1997-12-15
申请人： RAMBUS, INC.
发明人： RAMBUS, INC. , BARTH, Richard, M. , STARK, Donald, C. , LAI, Lawrence , RICHARDSON, Wayne, S.
IPC分类号： G11C08/00
CPC分类号： G11C7/06 , G11C8/14 , G11C11/4085 , G11C11/4091
摘要： A memory and method of operation is described. In one embodiment, the memory includes a group of memory cells divided into a plurality of sub-groups. Sub word-lines are selectively coupled to main word lines, each sub-word line corresponding to a sub-group and is coupled to the memory cells in the row of the corresponding sub-group: Sense amplifier circuitry is coupled to the group of memory cells. The sense amplifier circuitry is divided into a plurality of sub-sensing circuits, each of the plurality of sub-sensing circuits selectively coupled to a corresponding one of the plurality of sub-groups. The memory includes a control mechanism to control the word lines and sub-sensing circuit(s) that are activated at any one time such that only those sub-word lines and sub-sensing circuits needed to perform memory operations are operated and consume power. In an alternate embodiment, the control mechanism controls the sub-word lines and sub-sensing circuits to enable substantially concurrent access to different sub-groups of memory cells from different rows of the memory.
摘要翻译：描述了存储器和操作方法。在一个实施例中，存储器包括分成多个子组的一组存储器单元。子字线选择性地耦合到主字线，每个子字线对应于一个子组，并且被耦合到相应子组的行中的存储器单元：感测放大器电路耦合到该组存储器细胞。感测放大器电路被分成多个子感测电路，多个子感测电路中的每一个选择性地耦合到多个子组中的相应一个子组。存储器包括控制机构，用于控制在任何一个时间被激活的字线和子感测电路，使得只需要执行存储器操作所需的那些子字线和子感测电路并消耗功率。在替代实施例中，控制机构控制子字线和子感测电路以使得能够从存储器的不同行实质上并发地访问存储器单元的不同子组。

8. 发明申请

WO1996038031A2 CHIP SOCKET ASSEMBLY AND CHIP FILE ASSEMBLY FOR SEMICONDUCTOR CHIPS 审中-公开
标题翻译：用于半导体芯片的芯片插座组件和芯片文件组件
公开(公告)号：WO1996038031A2
公开(公告)日：1996-11-28
申请号：PCT/US1996007369
申请日：1996-05-21
申请人： RAMBUS, INC.
发明人： RAMBUS, INC. , PERINO, Donald, V. , RICHARDSON, Wayne, S. , DILLON, John, B.
IPC分类号： H05K07/10
CPC分类号： H05K7/1431 , H01R12/7005 , H05K3/325
摘要： A chip socket assembly provides for the mechanical and electrical coupling of edge-mountable chips to a bus of a circuit board with relative ease. An edge-mountable chip may be placed in a slot defined by a base. A clip may be attached to the base to retain the chip in the base. Alternatively, the base and the package of the chip may be configured such that the chip mates with the base in retaining the chip in the base. With the chip socket assembly, users may add, remove, or replace single chips and therefore expand the functionality of a system with the granularity of a single chip in a relatively easy manner. A chip file assembly may also be used to provide for the mechanical and electrical coupling of a plurality of edge-mountable chips to a bus of a circuit board with relative ease. Assemblies for securing horizontal chip packages are also described.
摘要翻译：芯片插座组件相对容易地将可边缘安装的芯片机械和电耦合到电路板的总线。可边缘安装的芯片可以放置在由基座限定的槽中。夹子可以附接到基座以将芯片保持在基座中。或者，芯片的基座和封装可以被配置成使得芯片将芯片保持在基座中与基座配合。使用芯片插座组件，用户可以以相对容易的方式添加，移除或替换单个芯片，并因此以单个芯片的粒度来扩展系统的功能。芯片文件组件也可用于相对容易地将多个可边缘安装的芯片机械和电耦合到电路板的总线。还描述了用于固定水平芯片封装的组件。

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