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    • 1. 发明申请
    • THIN-BOX METAL BACKGATE EXTREMELY THIN SOI DEVICE
    • 薄金属背板极薄的SOI器件
    • WO2011115773A3
    • 2011-12-29
    • PCT/US2011027461
    • 2011-03-08
    • IBMCHAN KEVIN KREN ZHIBINWANG XINHUI
    • CHAN KEVIN KREN ZHIBINWANG XINHUI
    • H01L29/78H01L21/336
    • H01L29/7827H01L21/7624H01L29/66628H01L29/66772H01L29/78603H01L29/78645H01L29/78648H01L29/78696
    • Silicon-on-insulator (SOI) structures with silicon layers less than 20 nm thick are used to form extremely thin silicon-on-insulator (ETSOI) semiconductor devices. ETSOI devices are manufactured using a thin tungsten backgate 101 encapsulated by thin nitride layers 100, 102 to prevent metal oxidation, the tungsten backgate 103 being characterized by its low resistivity. The structure further includes at least one FET having a gate stack 131, 132, 133 formed by a high-K metal gate 132 and a tungsten region 133 superimposed thereon, the footprint of the gate stack utilizing the thin SOI layer 100 as a channel. The SOI structure thus formed controls Vt variations from the thin SOI thickness and dopants therein. The ETSOI high-K metal backgate fully depleted device in conjunction with the thin BOX provides an excellent short channel control and significantly lowers the drain induced bias and sub-threshold swings. The present structure supports the evidence of the stability of the wafer having a tungsten film during thermal processing, and especially during STI and contact formation.
    • 使用具有小于20nm厚的硅层的绝缘体上硅(SOI)结构来形成极薄的绝缘体上硅(ETSOI)半导体器件。 ETSOI器件使用由薄氮化物层100,102包封的薄钨背板101制造以防止金属氧化,钨背板103的特征在于其低电阻率。 该结构还包括至少一个FET,其具有由高K金属栅极132和叠加在其上的钨区域133形成的栅极堆叠131,132,133,栅极堆叠的占用面积利用薄SOI层100作为沟道。 如此形成的SOI结构控制了来自薄SOI厚度和其中掺杂剂的Vt变化。 ETSOI高K金属背栅完全耗尽器件与薄型BOX一起提供出色的短通道控制,并显着降低漏极引起的偏置和亚阈值波动。 本结构支持在热处理期间具有钨膜的晶片稳定性的证据,并且特别是在STI和接触形成期间。
    • 2. 发明申请
    • ASYMMETRIC EPITAXY AND APPLICATION THEREOF
    • 不对称外延及其应用
    • WO2011056336A3
    • 2011-07-28
    • PCT/US2010051383
    • 2010-10-05
    • IBMYIN HAIZHOUWANG XINHUICHAN KEVIN KREN ZHIBIN
    • YIN HAIZHOUWANG XINHUICHAN KEVIN KREN ZHIBIN
    • H01L21/336H01L29/78
    • H01L21/26586H01L29/66628H01L29/66636H01L29/66659H01L29/7835
    • The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation. A source region formed to the second side of the gate structure by the epitaxial growth has a height higher than a drain region formed to the first side of the gate structure by the epitaxial growth. A semiconductor structure formed thereby is also provided.
    • 本发明提供了形成非对称场效应晶体管的方法。 所述方法包括在半导体衬底的顶部上形成栅极结构,所述栅极结构包括栅极叠层和邻近所述栅极堆叠的侧壁的间隔物,并且具有与所述第一侧相对的第一侧和第二侧; 从衬底中的栅极结构的第一侧进行成角度的离子注入,从而形成与第一侧相邻的离子注入区域,其中栅极结构防止成角度的离子注入到达邻近第二侧的衬底 门结构; 以及在栅极结构的第一和第二侧在衬底上进行外延生长。 结果,在离子注入区域上的外延生长比经历无离子注入的区域慢得多。 通过外延生长形成到栅极结构的第二侧的源极区域的高度高于通过外延生长形成于栅极结构的第一侧的漏极区域的高度。 还提供了由此形成的半导体结构。