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1. 发明申请

WO2011115773A3 THIN-BOX METAL BACKGATE EXTREMELY THIN SOI DEVICE 审中-公开
标题翻译：薄金属背板极薄的SOI器件
公开(公告)号：WO2011115773A3
公开(公告)日：2011-12-29
申请号：PCT/US2011027461
申请日：2011-03-08
申请人： IBM , CHAN KEVIN K , REN ZHIBIN , WANG XINHUI
发明人： CHAN KEVIN K , REN ZHIBIN , WANG XINHUI
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7827 , H01L21/7624 , H01L29/66628 , H01L29/66772 , H01L29/78603 , H01L29/78645 , H01L29/78648 , H01L29/78696
摘要： Silicon-on-insulator (SOI) structures with silicon layers less than 20 nm thick are used to form extremely thin silicon-on-insulator (ETSOI) semiconductor devices. ETSOI devices are manufactured using a thin tungsten backgate 101 encapsulated by thin nitride layers 100, 102 to prevent metal oxidation, the tungsten backgate 103 being characterized by its low resistivity. The structure further includes at least one FET having a gate stack 131, 132, 133 formed by a high-K metal gate 132 and a tungsten region 133 superimposed thereon, the footprint of the gate stack utilizing the thin SOI layer 100 as a channel. The SOI structure thus formed controls Vt variations from the thin SOI thickness and dopants therein. The ETSOI high-K metal backgate fully depleted device in conjunction with the thin BOX provides an excellent short channel control and significantly lowers the drain induced bias and sub-threshold swings. The present structure supports the evidence of the stability of the wafer having a tungsten film during thermal processing, and especially during STI and contact formation.
摘要翻译：使用具有小于20nm厚的硅层的绝缘体上硅（SOI）结构来形成极薄的绝缘体上硅（ETSOI）半导体器件。 ETSOI器件使用由薄氮化物层100,102包封的薄钨背板101制造以防止金属氧化，钨背板103的特征在于其低电阻率。该结构还包括至少一个FET，其具有由高K金属栅极132和叠加在其上的钨区域133形成的栅极堆叠131,132,133，栅极堆叠的占用面积利用薄SOI层100作为沟道。如此形成的SOI结构控制了来自薄SOI厚度和其中掺杂剂的Vt变化。 ETSOI高K金属背栅完全耗尽器件与薄型BOX一起提供出色的短通道控制，并显着降低漏极引起的偏置和亚阈值波动。本结构支持在热处理期间具有钨膜的晶片稳定性的证据，并且特别是在STI和接触形成期间。

2. 发明申请

WO2011056336A3 ASYMMETRIC EPITAXY AND APPLICATION THEREOF 审中-公开
标题翻译：不对称外延及其应用
公开(公告)号：WO2011056336A3
公开(公告)日：2011-07-28
申请号：PCT/US2010051383
申请日：2010-10-05
申请人： IBM , YIN HAIZHOU , WANG XINHUI , CHAN KEVIN K , REN ZHIBIN
发明人： YIN HAIZHOU , WANG XINHUI , CHAN KEVIN K , REN ZHIBIN
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/26586 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation. A source region formed to the second side of the gate structure by the epitaxial growth has a height higher than a drain region formed to the first side of the gate structure by the epitaxial growth. A semiconductor structure formed thereby is also provided.
摘要翻译：本发明提供了形成非对称场效应晶体管的方法。所述方法包括在半导体衬底的顶部上形成栅极结构，所述栅极结构包括栅极叠层和邻近所述栅极堆叠的侧壁的间隔物，并且具有与所述第一侧相对的第一侧和第二侧; 从衬底中的栅极结构的第一侧进行成角度的离子注入，从而形成与第一侧相邻的离子注入区域，其中栅极结构防止成角度的离子注入到达邻近第二侧的衬底门结构; 以及在栅极结构的第一和第二侧在衬底上进行外延生长。结果，在离子注入区域上的外延生长比经历无离子注入的区域慢得多。通过外延生长形成到栅极结构的第二侧的源极区域的高度高于通过外延生长形成于栅极结构的第一侧的漏极区域的高度。还提供了由此形成的半导体结构。

3. 发明申请

WO2005041252B1 SPLIT POLY-SiGe/POLY-Si ALLOY GATE STACK 审中-公开
公开(公告)号：WO2005041252B1
公开(公告)日：2005-09-09
申请号：PCT/US2004020907
申请日：2004-06-30
申请人： IBM , CHEN JIA , CHAN KEVIN K , HUANG SHIH-FEN , NOWAK EDWARD J
发明人： CHEN JIA , CHAN KEVIN K , HUANG SHIH-FEN , NOWAK EDWARD J
IPC分类号： H01L20060101 , H01L21/335 , H01L21/336 , H01L21/8238 , H01L29/24 , H01L29/49 , H01L29/76 , H01L31/072 , H01L31/119
CPC分类号： H01L21/2807 , H01L21/28052 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L29/4916 , H01L29/4925 , H01L29/665
摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer (41) on the gate dielectric (43). The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe (45) with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer (47), (3) to 4A thick. The thin SiO2 or SixGeyOZ interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of a subsequently deposited layer of cobalt. This gate electrode stack structure is used for both nFETs.and pFETs.

4. 发明申请

WO2011133339A3 MONOLAYER DOPANT EMBEDDED STRESSOR FOR ADVANCED CMOS 审中-公开
标题翻译：用于高级CMOS的单层掺杂嵌入式压电器
公开(公告)号：WO2011133339A3
公开(公告)日：2012-03-08
申请号：PCT/US2011031693
申请日：2011-04-08
申请人： IBM , CHAN KEVIN K , DUBE ABHISHEK , HOLT JUDSON R , LI JINGHONG , NEWBURY JOSEPH S , ONTALUS VIOREL , PARK DAE-GYU , ZHU ZHENGMAO
发明人： CHAN KEVIN K , DUBE ABHISHEK , HOLT JUDSON R , LI JINGHONG , NEWBURY JOSEPH S , ONTALUS VIOREL , PARK DAE-GYU , ZHU ZHENGMAO
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8228 , H01L27/092
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/7834
摘要： Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include an FET gate stack 18 located on an upper surface of a semiconductor substrate 12. The FET gate stack includes source and drain extension regions 28 located within the semiconductor substrate at a footprint of the FET gate stack. A device channel 40 is also present between the source and drain extension regions and beneath the gate stack. The structure further includes embedded stressor elements 34 located on opposite sides of the FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy 36 doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy 38 doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes a monolayer of dopant located within the upper layer of each of the embedded stressor elements. The monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.
摘要翻译：公开了在其中具有嵌入的应力元件的半导体结构。所公开的结构包括位于半导体衬底12的上表面上的FET栅极堆叠18. FET栅极堆叠包括在FET栅极堆叠的覆盖区处位于半导体衬底内的源极和漏极延伸区域28。器件沟道40也存在于源极延伸区域和漏极延伸区域之间以及栅极堆叠层下方。该结构还包括位于FET栅极堆叠的相对侧并且位于半导体衬底内的嵌入式应力元件34。每个嵌入的应力元件包括第一外延36掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，并且第二外延的上层 38掺杂的半导体材料位于下层的顶部。与第二外延掺杂半导体材料的上层相比，第一外延掺杂半导体材料的下层具有较低的掺杂剂含量。该结构还包括位于每个嵌入的应力元件的上层内的掺杂剂单层。掺杂剂的单层与源极延伸区域或漏极延伸区域的边缘直接接触。

5. 发明申请

WO2011162977A3 DELTA MONOLAYER DOPANTS EPITAXY FOR EMBEDDED SOURCE/DRAIN SILICIDE 审中-公开
标题翻译： DELTA MONOLAYER DOPANTS嵌入式源/漏极硅胶外观
公开(公告)号：WO2011162977A3
公开(公告)日：2012-03-15
申请号：PCT/US2011039892
申请日：2011-06-10
申请人： IBM , CHAN KEVIN K , DUBE ABHISHEK , HOLT JUDSON R , JOHNSON JEFFREY B , LI JINGHONG , PARK DAE-GYU , ZHU ZHENGMAO
发明人： CHAN KEVIN K , DUBE ABHISHEK , HOLT JUDSON R , JOHNSON JEFFREY B , LI JINGHONG , PARK DAE-GYU , ZHU ZHENGMAO
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7834 , H01L29/7848
摘要： Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack (18) located on an upper surface of a semiconductor substrate (12). The at least one FET gate stack includes source and drain extension regions (28) located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel (40) is also present between the source and drain extension regions (28) and beneath the at least one gate stack (18). The structure further includes embedded stressor elements (33) located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material (35) having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material (36) located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact (45) located directly on an upper surface of the delta monolayer (37).
摘要翻译：公开了在其中具有嵌入的应力元件的半导体结构。所公开的结构包括位于半导体衬底（12）的上表面上的至少一个FET栅叠层（18）。所述至少一个FET栅极堆叠包括位于所述至少一个FET栅极堆叠中的覆盖区内的所述半导体衬底内的源极和漏极延伸区域（28）。器件通道（40）也存在于源极和漏极延伸区域（28）之间并且在至少一个栅极堆叠（18）下方。该结构还包括位于至少一个FET栅极堆叠的相对侧上并且在半导体衬底内的嵌入式应力元件（33）。每个嵌入式应力元件包括从底部到顶部具有不同于半导体衬底的晶格常数的晶格常数的第一外延掺杂半导体材料（35）的第一层，并且在器件沟道中施加应变，位于第一层顶部的第二外延掺杂半导体材料（36）的第二层和位于第二层的上表面上的掺杂剂的Δ单层。该结构还包括直接位于三角单层（37）的上表面上的金属半导体合金接触（45）。

6. 发明申请

WO2006002410A3 COMPRESSIVE SIGE <110> GROWTH MOSFET DEVICES 审中-公开
标题翻译：压缩信号<110>增长型MOSFET器件
公开(公告)号：WO2006002410A3
公开(公告)日：2007-12-06
申请号：PCT/US2005022643
申请日：2005-06-21
申请人： IBM , CHAN KEVIN K , GUARINI KATHRYN W , IEONG MEIKEL , RIM KERN , YANG MIN
发明人： CHAN KEVIN K , GUARINI KATHRYN W , IEONG MEIKEL , RIM KERN , YANG MIN
IPC分类号： H01L29/04 , H01L21/20 , H01L21/205 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L29/06 , H01L29/10 , H01L29/76 , H01L29/94 , H01L31/0328 , H01L31/0336 , H01L31/036 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/045 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/02658 , H01L21/823807 , H01L29/1054
摘要： A structure for conducting carriers and method for forming is described incorporating a single crystal substrate of Si or SiGe having an upper surface in the and a psuedomorphic or epitaxial layer of SiGe having a concentration of Ge different than the substrate whereby the psuedomorphic layer is under strain. A method for forming semiconductor epitaxial layers is described incorporating the step of forming a psuedomorphic or epitaxial layer in a rapid thermal chemical vapor deposition (RTCVD) tool by increasing the temperature in the tool to about 600ºC and introducing both a Si containing gas and a Ge containing gas. A method for chemically preparing a substrate for epitaxial deposition is described comprising the steps of immersing a substrate in a series of baths containing ozone, dilute HF, deionized water, HC1 acid and deionized water, respectively, followed by drying the substrate in an inert atmosphere to obtain a substrate surface free of impurities and with a RMS roughness of less than 0.1 nm.
摘要翻译：描述了用于导电载体的结构和形成方法，其结合了在<110>中具有上表面的Si或SiGe的单晶衬底和SiGe的形貌或外延层，其Ge浓度与衬底的Ge不同，由此使形成层正在紧张。描述了一种用于形成半导体外延层的方法，其包括在快速热化学气相沉积（RTCVD）工具中通过将工具中的温度增加到约600℃并形成含硅气体和锗的Ge形成或外延层的步骤含气。描述了一种用于化学制备用于外延沉积的衬底的方法，其包括以下步骤：将衬底浸入含有臭氧，稀HF，去离子水，HCl酸和去离子水的一系列浴中，然后在惰性气氛中干燥衬底以获得不含杂质且RMS小于0.1nm的衬底表面。

7. 发明申请

WO2005041252A2 SPLIT POLY-SiGe/POLY-Si ALLOY GATE STACK 审中-公开
标题翻译：分散多晶硅/多晶硅合金栅极堆叠
公开(公告)号：WO2005041252A2
公开(公告)日：2005-05-06
申请号：PCT/US2004020907
申请日：2004-06-30
申请人： IBM , CHEN JIA , CHAN KEVIN K , HUANG SHIH-FEN , NOWAK EDWARD J
发明人： CHEN JIA , CHAN KEVIN K , HUANG SHIH-FEN , NOWAK EDWARD J
IPC分类号： H01L20060101 , H01L21/335 , H01L21/336 , H01L21/8238 , H01L29/24 , H01L29/49 , H01L29/76 , H01L31/072 , H01L31/119 , H01L
CPC分类号： H01L21/2807 , H01L21/28052 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L29/4916 , H01L29/4925 , H01L29/665
摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer (41) on the gate dielectric (43). The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe (45) with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer (47), (3) to 4A thick. The thin SiO2 or SixGeyOZ interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of a subsequently deposited layer of cobalt. This gate electrode stack structure is used for both nFETs.and pFETs.
摘要翻译：在栅极电介质（43）上的硅纳米晶种子层（41）上形成场效应晶体管器件的多层栅电极堆叠结构。硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积具有高达至少70％的[Ge]的均匀且连续的多晶硅（45）层。在快速降低的温度下，氧气环境中沉积室的原位吹扫导致薄的SiO 2或SixGeyOz界面层（47），（3）至4A厚。薄的SiO 2或SixGeyOZ界面层是足够薄且不连续的，以提供对栅极电流的很小的阻力，但是具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许随后沉积的钴的硅化物。该栅电极堆叠结构用于nFET和pFET。

8. 发明申请

WO2005067677A2 HIGH PERFORMANCE STRAINED SILICON FINFETS DEVICE AND METHOD FOR FORMING SAME 审中-公开
标题翻译：高性能应变硅熔体装置及其形成方法
公开(公告)号：WO2005067677A2
公开(公告)日：2005-07-28
申请号：PCT/US2005000072
申请日：2005-01-04
申请人： IBM
发明人： BEDELL STEPHEN W , CHAN KEVIN K , CHIDAMBARRAO DURESETI , CHRISTIANSEN SILKE H , CHU JACK O , DOMENICUCCI ANTHONY G , LEE KAM-LEUNG , MOCUTA ANDA C , OTT JOHN A , OUYANG QIQING C
IPC分类号： H01L21/336 , H01L21/84 , H01L27/01 , H01L27/12 , H01L29/786
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.
摘要翻译：应变Fin场效应晶体管（FinFET）（及其形成方法）包括具有侧壁的松弛的第一材料和形成在第一材料的侧壁上的应变的第二材料。松弛的第一材料和应变的第二材料形成FinFET的鳍。

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