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1. 发明申请

WO2008100843A4 CORRECTION OF VOLTAGE OFFSET AND CLOCK OFFSET FOR SAMPLING NEAR ZERO-CROSSING POINT 审中-公开
标题翻译：零点附近取样的电压偏移和时钟偏移的校正
公开(公告)号：WO2008100843A4
公开(公告)日：2009-04-16
申请号：PCT/US2008053552
申请日：2008-02-11
申请人： RAMBUS INC , FULLER ANDREW M , POULTON JOHN
发明人： FULLER ANDREW M , POULTON JOHN
IPC分类号： H04L25/06 , H04L7/033 , H04L7/04
CPC分类号： H04L25/063 , H03F3/45179 , H03F2203/45008 , H03F2203/45306 , H03F2203/45588 , H04L7/046 , H04L25/0278
摘要： Embodiments of a circuit are described. This circuit includes a receiver circuit including a first sampler (312-1) and a second" sampler (312-2). A clock-data-recovery circuit (324) in the receiver circuit adjusts a sample time of the receiver circuit so that the sample time is proximate to a signal crossing point at an edge of an eye pattern associated with received signals. An offset-calibration circuit (326) in the receiver circuit determines and adjusts an offset voltage of a given sampler, which can be the first sampler or the second sampler. This offset-calibration circuit may determine a present offset voltage (412) of the given sampler in a timing region proximate to the signal crossing point (410-2) in which the clock-data-recovery circuit dithers about a present sample time based on the present offset voltage. Additionally, the clock-data-recovery circuit and the offset-calibration circuit may iteratively converge on the signal crossing point and a residual offset voltage of the given sampler.
摘要翻译：描述电路的实施例。该电路包括包含第一采样器（312-1）和第二采样器（312-2）的接收器电路，接收器电路中的时钟数据恢复电路（324）调整接收器电路的采样时间，采样时间接近与接收信号相关联的眼图边缘处的信号交叉点，接收器电路中的偏移校准电路（326）确定并调整给定采样器的偏移电压，该给定采样器可以是第一该偏移校准电路可以确定给定采样器在接近信号交叉点（410-2）的时间区域中的当前偏移电压（412），其中时钟数据恢复电路在其中抖动基于当前偏移电压的当前采样时间另外，时钟数据恢复电路和偏移校准电路可以迭代地收敛在给定采样器的信号交叉点和残余偏移电压上。

2. 发明申请

WO2008100843A2 EDGE-BASED SAMPLER OFFSET CORRECTION 审中-公开
标题翻译：基于边缘采样器偏移校正
公开(公告)号：WO2008100843A2
公开(公告)日：2008-08-21
申请号：PCT/US2008/053552
申请日：2008-02-11
申请人： RAMBUS INC. , FULLER, Andrew, M. , POULTON, John
发明人： FULLER, Andrew, M. , POULTON, John
IPC分类号： H04L25/06
CPC分类号： H04L25/063 , H03F3/45179 , H03F2203/45008 , H03F2203/45306 , H03F2203/45588 , H04L7/046 , H04L25/0278
摘要： A receiver circuit includes a first sampler and a second sampler. A clock-data-recovery circuit in the receiver circuit adjusts a sample time of the receiver circuit so that the sample time is proximate to a signal crossing point at an edge of an eye pattern associated with received signals. An offset-calibration circuit in the receiver circuit determines and adjusts an offset voltage of a given sampler, which can be the first sampler or the second sampler. This offset-calibration circuit may determine a present offset voltage of the given sampler in a timing region proximate to the signal crossing point in which the clock-data-recovery circuit dithers about a present sample time based on the present offset voltage. Additionally, the clock-data-recovery circuit and the offset-calibration circuit may iteratively converge on the signal crossing point and a residual offset voltage of the given sampler.
摘要翻译：接收器电路包括第一采样器和第二采样器。接收机电路中的时钟数据恢复电路调整接收器电路的采样时间，使得采样时间接近与接收信号相关联的眼图的边缘处的信号交叉点。接收器电路中的偏移校准电路确定并调整给定采样器的偏移电压，其可以是第一采样器或第二采样器。该偏移校准电路可以在靠近信号交叉点的定时区域中确定给定采样器的当前偏移电压，其中时钟数据恢复电路基于当前偏移电压来抖动当前采样时间。此外，时钟数据恢复电路和偏移校准电路可以迭代地收敛于给定采样器的信号交叉点和剩余偏移电压。

3. 发明申请

WO2010080173A1 MESOCHRONOUS SIGNALING SYSTEM WITH CLOCK-STOPPED LOW POWER MODE 审中-公开
标题翻译：具有时钟停止低功耗模式的MESOCHRONOUS信号系统
公开(公告)号：WO2010080173A1
公开(公告)日：2010-07-15
申请号：PCT/US2009/050020
申请日：2009-07-09
申请人： RAMBUS INC. , WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W. , FULLER, Andrew, M.
发明人： WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W. , FULLER, Andrew, M.
IPC分类号： G06F1/04 , G06F1/32 , G06F12/00
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop- clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译：在低功率信号系统中，集成电路设备包括开环时钟分配电路和发射电路，其协作以实现不受源同步定时参考而不伴随的信息载体的高速传输。开环时钟分配电路响应于外部提供的时钟信号而产生发送时钟信号，并且发送电路响应于发送时钟信号的转换而将符号序列输出到外部信号线上。每个符号在符号时间的发射电路的输出端是有效的，并且发射时钟信号和外部提供的时钟信号之间的相位偏移允许至少漂移符号时间。

4. 发明申请

WO2008100843A3 CORRECTION OF VOLTAGE OFFSET AND CLOCK OFFSET FOR SAMPLING NEAR ZERO-CROSSING POINT 审中-公开
标题翻译：电压偏移和时钟偏移的校正用于采集零点交点
公开(公告)号：WO2008100843A3
公开(公告)日：2009-02-12
申请号：PCT/US2008053552
申请日：2008-02-11
申请人： RAMBUS INC , FULLER ANDREW M , POULTON JOHN
发明人： FULLER ANDREW M , POULTON JOHN
IPC分类号： H04L25/06 , H04L7/033 , H04L7/04
CPC分类号： H04L25/063 , H03F3/45179 , H03F2203/45008 , H03F2203/45306 , H03F2203/45588 , H04L7/046 , H04L25/0278
摘要： Embodiments of a circuit are described. This circuit includes a receiver circuit including a first sampler (312-1) and a second" sampler (312-2). A clock-data-recovery circuit (324) in the receiver circuit adjusts a sample time of the receiver circuit so that the sample time is proximate to a signal crossing point at an edge of an eye pattern associated with received signals. An offset-calibration circuit (326) in the receiver circuit determines and adjusts an offset voltage of a given sampler, which can be the first sampler or the second sampler. This offset-calibration circuit may determine a present offset voltage (412) of the given sampler in a timing region proximate to the signal crossing point (410-2) in which the clock-data-recovery circuit dithers about a present sample time based on the present offset voltage. Additionally, the clock-data-recovery circuit and the offset-calibration circuit may iteratively converge on the signal crossing point and a residual offset voltage of the given sampler.
摘要翻译：描述电路的实施例。该电路包括包括第一采样器（312-1）和第二采样器（312-2）的接收器电路，接收器电路中的时钟数据恢复电路（324）调整接收器电路的采样时间，使得采样时间接近于与接收信号相关联的眼图的边缘处的信号交叉点，接收机电路中的偏移校准电路（326）确定并调整给定采样器的偏移电压，其可以是第一该偏移校准电路可以在接近信号交叉点（410-2）的定时区域中确定给定采样器的当前偏移电压（412），其中时钟数据恢复电路抖动此时，时钟数据恢复电路和偏移校准电路可以迭代地收敛于信号交叉点和给定采样器的剩余失调电压。

5. 发明申请

WO2008100523A3 LOW-POWER CLOCK GENERATION AND DISTRIBUTION CIRCUITRY 审中-公开
公开(公告)号：WO2008100523A3
公开(公告)日：2008-08-21
申请号：PCT/US2008/001869
申请日：2008-02-12
申请人： RAMBUS INC. , POULTON, John, W. , PALMER, Robert, E. , FULLER, Andrew, M.
发明人： POULTON, John, W. , PALMER, Robert, E. , FULLER, Andrew, M.
IPC分类号： G06F1/10 , G06F1/32
摘要： A communication IC includes a power-efficient clock-distribution system. A control loop monitors and adjusts the peak and trough voltages of a clock signal. The clock signal can be adaptively adjusted to center the peak and trough voltages about the switching threshold voltage of a clock buffer. The voltage swing of the clock signal can thus be made small and, as a consequence, power efficient. The control loop can monitor and control more than one clock signal.

6. 发明申请

WO2010080174A1 MESOCHRONOUS SIGNALING SYSTEM WITH CORE-CLOCK SYNCHRONIZATION 审中-公开
标题翻译：具有核心时钟同步的MESOCHRONOUS信号系统
公开(公告)号：WO2010080174A1
公开(公告)日：2010-07-15
申请号：PCT/US2009/050023
申请日：2009-07-09
申请人： RAMBUS INC. , WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W. , FULLER, Andrew, M.
发明人： WARE, Frederick, A. , PALMER, Robert, E. , POULTON, John, W. , FULLER, Andrew, M.
IPC分类号： G11C11/407 , H03K19/0175
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop- clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译：在低功率信号系统中，集成电路设备包括开环时钟分配电路和发射电路，其协作以使得能够以源同步定时参考不伴随的信息载体的高速传输。开环时钟分配电路响应于外部提供的时钟信号而产生发送时钟信号，并且发送电路响应于发送时钟信号的转换而将符号序列输出到外部信号线上。每个符号在符号时间的发射电路的输出端是有效的，并且发射时钟信号和外部提供的时钟信号之间的相位偏移允许至少漂移符号时间。

7. 发明申请

WO2009076097A1 EDGE-BASED LOSS-OF-SIGNAL DETECTION 审中-公开
标题翻译：基于边缘的信号丢失检测
公开(公告)号：WO2009076097A1
公开(公告)日：2009-06-18
申请号：PCT/US2008/085240
申请日：2008-12-02
申请人： RAMBUS INC. , FULLER, Andrew M. , POULTON, John
发明人： FULLER, Andrew M. , POULTON, John
IPC分类号： H04B1/06 , H04B7/005 , H04W52/02
CPC分类号： H04L25/0262 , H04L1/20 , H04L1/246
摘要： Systems and methods are provided for edge-based loss-of-signal (LOS) detection. In a receiver, a receiver port receives a data signal. A clock and data recovery (CDR) mechanism coupled to the receive port derives one or more clock signals. An LOS signal generation mechanism generates an LOS signal based on edge glitches which occur when the receive port does not receive usable data.
摘要翻译：为基于边缘的信号丢失（LOS）检测提供了系统和方法。在接收机中，接收端口接收数据信号。耦合到接收端口的时钟和数据恢复（CDR）机制导出一个或多个时钟信号。 LOS信号产生机制基于接收端口不接收可用数据时出现的边缘毛刺产生LOS信号。

8. 发明申请

WO2008100523A4 LOW-POWER CLOCK GENERATION AND DISTRIBUTION CIRCUITRY 审中-公开
标题翻译：低功率时钟发生和分配电路
公开(公告)号：WO2008100523A4
公开(公告)日：2009-01-29
申请号：PCT/US2008001869
申请日：2008-02-12
申请人： RAMBUS INC , POULTON JOHN W , PALMER ROBERT E , FULLER ANDREW M
发明人： POULTON JOHN W , PALMER ROBERT E , FULLER ANDREW M
IPC分类号： G06F1/10 , G06F1/32
CPC分类号： H04L25/063 , H03F3/45179 , H03F2203/45008 , H03F2203/45306 , H03F2203/45588 , H04L7/046 , H04L25/0278
摘要： A communication IC includes a power-efficient clock-distribution system. A control loop monitors and adjusts the peak and trough voltages of a clock signal. The clock signal can be adaptively adjusted to center the peak and trough voltages about the switching threshold voltage of a clock buffer. The voltage swing of the clock signal can thus be made small and, as a consequence, power efficient. The control loop can monitor and control more than one clock signal.
摘要翻译：通信IC包括功率高效的时钟分配系统。控制回路监视和调整时钟信号的峰值和谷底电压。可以自适应地调整时钟信号以使峰值和谷值电压围绕时钟缓冲器的开关阈值电压。因此，可以使时钟信号的电压摆幅变小，结果是功率有效。控制回路可以监视和控制多个时钟信号。

9. 发明申请

WO2008100523A2 LOW-POWER CLOCK GENERATION AND DISTRIBUTION CIRCUITRY 审中-公开
标题翻译：低功耗时钟发生和分配电路
公开(公告)号：WO2008100523A2
公开(公告)日：2008-08-21
申请号：PCT/US2008001869
申请日：2008-02-12
申请人： RAMBUS INC , POULTON JOHN W , PALMER ROBERT E , FULLER ANDREW M
发明人： POULTON JOHN W , PALMER ROBERT E , FULLER ANDREW M
IPC分类号： H03K19/00
CPC分类号： H04L25/063 , H03F3/45179 , H03F2203/45008 , H03F2203/45306 , H03F2203/45588 , H04L7/046 , H04L25/0278
摘要： A communication IC includes a power-efficient clock-distribution system. A control loop monitors and adjusts the peak and trough voltages of a clock signal. The clock signal can be adaptively adjusted to center the peak and trough voltages about the switching threshold voltage of a clock buffer. The voltage swing of the clock signal can thus be made small and, as a consequence, power efficient. The control loop can monitor and control more than one clock signal.
摘要翻译：通信IC包括功率高效的时钟分配系统。控制回路监视并调整时钟信号的峰值和谷值电压。时钟信号可以自适应地调整，以使峰值和谷值电压在时钟缓冲器的开关阈值电压附近居中。时钟信号的电压摆幅因此可以做得很小，因此功率效率很高。控制回路可以监视和控制多个时钟信号。

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