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1. 发明申请

WO2013033315A3 WAFER CARRIER WITH THERMAL FEATURES 审中-公开
标题翻译：具有热特性的晶片载体
公开(公告)号：WO2013033315A3
公开(公告)日：2013-05-16
申请号：PCT/US2012053016
申请日：2012-08-30
申请人： VEECO INSTR INC , PARANJPE AJIT , VOLF BORIS , ARMOUR ERIC A , KRISHNAN SANDEEP , WEI GUANGHUA , URBAN LUKAS
发明人： PARANJPE AJIT , VOLF BORIS , ARMOUR ERIC A , KRISHNAN SANDEEP , WEI GUANGHUA , URBAN LUKAS
IPC分类号： H01L21/683 , C23C16/458 , H01L21/205
CPC分类号： H01L21/68764 , C23C16/4584 , C23C16/4586 , H01L21/67103 , H01L21/68707 , H01L21/68771
摘要： A wafer carrier (32) used in wafer treatments such as chemical vapor deposition has pockets (40) for holding the wafers (70) and support surfaces (56) for supporting the wafers above the floors (46) of the pockets. The carrier (32) is provided with thermal control features such as trenches (41) which form thermal barriers having lower thermal conductivity than surrounding portions of the carrier. These thermal control features promote a more uniform temperature distribution across the wafer surfaces (72, 74) and across the carrier top surface (34).
摘要翻译：用于诸如化学气相沉积之类的晶片处理中的晶片载体（32）具有用于保持晶片（70）的袋（40）和用于将晶片支撑在袋的地板（46）上方的支撑表面（56）。载体（32）设置有热控制特征，例如形成具有比载体的周围部分低的导热率的热障的沟槽（41）。这些热控制特征促进晶片表面（72,74）和载体顶表面（34）上的更均匀的温度分布。

2. 发明申请

WO2013012549A2 MULTI-CHAMBER CVD PROCESSING SYSTEM 审中-公开
标题翻译：多室CVD处理系统
公开(公告)号：WO2013012549A2
公开(公告)日：2013-01-24
申请号：PCT/US2012045179
申请日：2012-07-02
申请人： VEECO INSTR INC , PARANJPE AJIT , ARMOUR ERIC A , QUINN WILLIAM E
发明人： PARANJPE AJIT , ARMOUR ERIC A , QUINN WILLIAM E
IPC分类号： H01L21/205
CPC分类号： C23C16/4582 , C23C16/54 , C30B25/025 , C30B35/00
摘要： A multi-chamber CVD system includes a plurality of substrate carriers where each substrate carrier is adapted to support at least one substrate. A plurality of enclosures are each configured to form a deposition chamber enclosing one of the plurality of substrate carriers to maintain an independent chemical vapor deposition process chemistry for performing a processing step. A transport mechanism transports each of the plurality of substrate carriers to each of the plurality of enclosures in discrete steps that allow processing steps to be performed in the plurality of enclosures for a predetermined time. In some embodiments, the substrate carrier can be rotatable.
摘要翻译：多室CVD系统包括多个衬底载体，其中每个衬底载体适于支撑至少一个衬底。多个外壳各自被配置为形成封闭多个衬底载体中的一个的沉积室，以保持用于执行处理步骤的独立化学气相沉积工艺化学物质。传送机构以不连续的步骤将多个基板载体中的每一个传送至多个机壳中的每一个，这允许在多个机壳中执行处理步骤达预定时间。在一些实施例中，基板载体可以是可旋转的。

3. 发明申请

WO2012139006A2 METAL-ORGANIC VAPOR PHASE EPITAXY SYSTEM AND PROCESS 审中-公开
标题翻译：金属有机蒸汽相外延系统和工艺
公开(公告)号：WO2012139006A2
公开(公告)日：2012-10-11
申请号：PCT/US2012/032533
申请日：2012-04-06
申请人： VEECO INSTRUMENTS INC. , PARANJPE, Ajit , GURARY, Alexander , QUINN, William
发明人： PARANJPE, Ajit , GURARY, Alexander , QUINN, William
CPC分类号： C30B25/14 , C30B25/10 , C30B25/12 , C30B35/00
摘要： A VPE reactor is improved by providing temperature control to within 0.5 °C, and greater process gas uniformity via novel reactor shaping, unique wafer motion structures, improvements in thermal control systems, improvements in gas flow structures, improved methods for application of gas and temperature, and improved control systems for detecting and reducing process variation.
摘要翻译：通过提供温度控制在0.5°C以内，通过新型反应器成型，独特的晶片运动结构，热控制系统的改进，气流结构的改进，气体和温度的应用改进方法，改进了VPE反应器，以及用于检测和减少过程变化的改进的控制系统。

4. 发明申请

WO2013033315A2 WAFER CARRIER WITH THERMAL FEATURES 审中-公开
标题翻译：具有热特性的散热器
公开(公告)号：WO2013033315A2
公开(公告)日：2013-03-07
申请号：PCT/US2012/053016
申请日：2012-08-30
申请人： VEECO INSTRUMENTS INC. , PARANJPE, Ajit , VOLF, Boris , ARMOUR, Eric, A. , KRISHNAN, Sandeep , WEI, Guanghua , URBAN, Lukas
发明人： PARANJPE, Ajit , VOLF, Boris , ARMOUR, Eric, A. , KRISHNAN, Sandeep , WEI, Guanghua , URBAN, Lukas
IPC分类号： H01L21/683 , H01L21/205 , C23C16/458
CPC分类号： H01L21/68764 , C23C16/4584 , C23C16/4586 , H01L21/67103 , H01L21/68707 , H01L21/68771
摘要： A wafer carrier (32) used in wafer treatments such as chemical vapor deposition has pockets (40) for holding the wafers (70) and support surfaces (56) for supporting the wafers above the floors (46) of the pockets. The carrier (32) is provided with thermal control features such as trenches (41) which form thermal barriers having lower thermal conductivity than surrounding portions of the carrier. These thermal control features promote a more uniform temperature distribution across the wafer surfaces (72, 74) and across the carrier top surface (34).
摘要翻译：在诸如化学气相沉积的晶片处理中使用的晶片载体（32）具有用于保持晶片（70）的凹槽（40）和用于将晶片支撑在凹穴的地板（46）上方的支撑表面（56）。载体（32）设置有诸如沟槽（41）的热控制特征，其形成具有比载体周围部分更低的热导率的热障。这些热控制特征促使晶片表面（72,74）和跨越载体顶表面（34）的更均匀的温度分布。

5. 发明申请

WO2006033838A3 POLY-SILICON-GERMANIUM GATE STACK AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：多晶硅 - 锗栅极叠层及其形成方法
公开(公告)号：WO2006033838A3
公开(公告)日：2006-12-21
申请号：PCT/US2005031953
申请日：2005-09-07
申请人： APPLIED MATERIALS INC , PARANJPE AJIT , ZHANG KANGZHAN
发明人： PARANJPE AJIT , ZHANG KANGZHAN
IPC分类号： H01L29/49 , H01L21/28 , H01L29/51
CPC分类号： H01L21/28044 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/0262 , H01L21/28282 , H01L21/823828 , H01L29/4925 , H01L29/513
摘要： A CMOS gate stack that increases the inversion capacitance compared to a conventional CMOS gate stack has been described. Using a poly-SiGe gate, instead of the conventional poly-Si gate near the gate dielectric layer, increases the amount of implanted dopant that can be activated. This increase overcomes the polysilicon depletion problem that limits the inversion capacitance in the conventional CMOS gate stack. To integrate the poly-SiGe layer into the gate stack, a thin -Si layer is deposited between the gate dielectric layer and the poly-SiGe layer. To ensure proper salicide formation, a poly-Si layer is capped over the poly-SiGe layer. In order to obtain a fined-grained poly-Si over poly-SiGe, a second -Si layer is deposited between the poly-Si layer and the poly-SiGe layer.
摘要翻译：已经描述了与常规CMOS栅极叠层相比增加反转电容的CMOS栅极叠层。使用多晶硅锗栅极代替栅极介电层附近的传统多晶硅栅极增加了可被激活的注入掺杂剂的量。这种增加克服了限制常规CMOS栅极叠层中的反转电容的多晶硅耗尽问题。为了将多晶SiGe层集成到栅极堆叠中，在栅极电介质层和多晶SiGe层之间沉积薄Si层。为了确保适当的自对准硅化物形成，将多晶硅层盖在多晶硅锗层上。为了获得多晶SiGe上的细晶粒多晶硅，在多晶硅层和多晶SiGe层之间沉积第二-Si层。

6. 发明申请

WO2013012549A3 MULTI-CHAMBER CVD PROCESSING SYSTEM 审中-公开
公开(公告)号：WO2013012549A3
公开(公告)日：2013-01-24
申请号：PCT/US2012/045179
申请日：2012-07-02
申请人： VEECO INSTRUMENTS INC. , PARANJPE, Ajit , ARMOUR, Eric A. , QUINN, William E.
发明人： PARANJPE, Ajit , ARMOUR, Eric A. , QUINN, William E.
IPC分类号： H01L21/205
摘要： A multi-chamber CVD system includes a plurality of substrate carriers where each substrate carrier is adapted to support at least one substrate. A plurality of enclosures are each configured to form a deposition chamber enclosing one of the plurality of substrate carriers to maintain an independent chemical vapor deposition process chemistry for performing a processing step. A transport mechanism transports each of the plurality of substrate carriers to each of the plurality of enclosures in discrete steps that allow processing steps to be performed in the plurality of enclosures for a predetermined time. In some embodiments, the substrate carrier can be rotatable.

7. 发明申请

WO2012092064A8 WAFER PROCESSING WITH CARRIER EXTENSION 审中-公开
公开(公告)号：WO2012092064A8
公开(公告)日：2012-07-05
申请号：PCT/US2011/066489
申请日：2011-12-21
申请人： VEECO INSTRUMENTS INC. , MITROVIC, Bojan , WEI, Guanghua , ARMOUR, Eric, A. , PARANJPE, Ajit
发明人： MITROVIC, Bojan , WEI, Guanghua , ARMOUR, Eric, A. , PARANJPE, Ajit
IPC分类号： C23C16/455 , C23C16/458 , H01L21/687
摘要： Apparatus for treating wafers (74) using a wafer carrier (40) rotated about an axis is provided with a ring (52) which surrounds the wafer carrier during operation. Treatment gasses directed onto a top surface (64) of the carrier flow outwardly away from the axis over the carrier and over the ring, and pass downstream outside of the ring. The outwardly flowing gasses form a boundary layer (B) over the carrier and ring. The ring helps to maintain a boundary layer of substantially uniform thickness over the carrier, which promotes uniform treatment of the wafers.

8. 发明申请

WO2006065776A2 PROCESS SEQUENCE FOR DOPED SILICON FILL OF DEEP TRENCHES 审中-公开
标题翻译： DEEP TRENCHES DOPED SILICON FILL的过程序列
公开(公告)号：WO2006065776A2
公开(公告)日：2006-06-22
申请号：PCT/US2005/044985
申请日：2005-12-13
申请人： APPLIED MATERIALS, INC. , PARANJPE, Ajit , NAG, Somnath
发明人： PARANJPE, Ajit , NAG, Somnath
IPC分类号： H01L21/4763
CPC分类号： C23C16/045 , C23C16/24 , H01L21/76232 , H01L29/66181
摘要： A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method of forming a deep trench capacitor structure, the intermediate steps further including the capping of the void free filled trench with a layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant.
摘要翻译：提供了一种无空隙填充深沟槽结构的原位掺杂非晶硅的方法，其中在硅烷比例的温度，压力和掺杂剂下进行第一次填充，从而使得膜沉积从沟槽的底部发生向上。通过这个第一次填写，实现了超过100％的步骤覆盖。在第二填充步骤中，在改变的条件下进行沉积，以减少掺杂剂对沉积速率的影响，由此以超过第一填充的沉积速率的沉积速率完成沟槽填充。在这种形成深沟槽电容器结构的方法的应用中，中间步骤还包括用无定形硅层覆盖无空隙的填充沟槽，此后晶片的平面化，随后进行热退火以重新分配掺杂剂。

9. 发明申请

WO2012082323A1 SECTIONAL WAFER CARRIER 审中-公开
公开(公告)号：WO2012082323A1
公开(公告)日：2012-06-21
申请号：PCT/US2011/061615
申请日：2011-11-21
申请人： VEECO INSTRUMENTS INC. , GURARY, Alexander I. , KRAUS, Joseph Arthur , PARANJPE, Ajit , QUINN, William, E. , CREWE, David Albert
发明人： GURARY, Alexander I. , KRAUS, Joseph Arthur , PARANJPE, Ajit , QUINN, William, E. , CREWE, David Albert
IPC分类号： H01L21/683 , H01L21/208 , C23C16/458 , H01L21/68
CPC分类号： C23C16/4584 , C23C16/4585 , C23C16/4586 , H01L21/67754 , H01L21/68707 , H01L21/6875 , H01L21/68764 , H01L21/68771
摘要： A structure for a chemical vapor deposition reactor includes a support element (50) defining oppositely-facing substantially planar upper and lower surfaces and a vertical rotational axis (52) substantially perpendicular to the upper and lower surfaces, and a plurality of carrier sections (70) releasably engaged with the support element. Each carrier section (70) can include oppositely-facing substantially planar top and bottom surfaces and at least one aperture (73) extending between the top and bottom surfaces. The carrier sections (70) can be disposed on the support element (50) with the bottom surfaces (79) of the carrier sections facing toward the upper surface (59) of the support element, so that (wafers 30) can be held in the apertures (73) of the carrier sections with one surface (32) of each wafer confronting the support element and an opposite surface (31) exposed at the top (surface 78) of the carrier sections.
摘要翻译：用于化学气相沉积反应器的结构包括限定相对面对的基本平坦的上表面和下表面的支撑元件（50）和基本上垂直于上表面和下表面的垂直旋转轴线（52），以及多个承载部分）可释放地与支撑元件接合。每个载体部分（70）可以包括相对面对的基本平坦的顶部和底部表面以及在顶部和底部表面之间延伸的至少一个孔（73）。载体部分（70）可以设置在支撑元件（50）上，载体部分的底表面（79）面向支撑元件的上表面（59），使得（晶片30）可以保持在载体部分的孔（73）具有面对支撑元件的每个晶片的一个表面（32）和暴露在载体部分的顶部（表面78）处的相对表面（31）。

10. 发明申请

WO2011028597A1 SYSTEM FOR FABRICATING A PATTERN ON MAGNETIC RECORDING MEDIA 审中-公开
标题翻译：用于制作磁记录介质的图案的系统
公开(公告)号：WO2011028597A1
公开(公告)日：2011-03-10
申请号：PCT/US2010/046783
申请日：2010-08-26
申请人： VEECO INSTRUMENTS, INC. , PARANJPE, Ajit , LUSE, Todd, Arthur , FREMGEN, Roger, P. , SRINIVASAN, Narasimhan , ROOK, Katrina , DRUZ, Boris, L. , CELARU, Adrian
发明人： PARANJPE, Ajit , LUSE, Todd, Arthur , FREMGEN, Roger, P. , SRINIVASAN, Narasimhan , ROOK, Katrina , DRUZ, Boris, L. , CELARU, Adrian
IPC分类号： G11B5/65
CPC分类号： G11B5/855 , C23C14/042 , C23C14/046 , C23C14/505 , H01L21/67173 , H01L21/67709 , H01L21/67712 , H01L21/67718 , H01L21/67742 , H01L21/67754
摘要： An inline processing system for patterning magnetic recording layers on hard discs for use in a hard disc drive. Discs are processed on both sides simultaneously in a vertical orientation, in round plate-like holders called MDCs. A plurality (as many as 10) discs are held in a dial carrier of the MDC, and transferred from one process station to another. The dial carrier of the MDC may be rotated and/or angled at up to 70° from normal in each process station, so that one or a plurality of process sources may treat the discs simultaneously. This configuration provides time savings and a reduction in the number and size of process sources needed. A mask enhancement process for patterning of magnetic media, and a filling and planarizing process used therewith, are also disclosed.
摘要翻译：一种用于在用于硬盘驱动器的硬盘上图案化磁记录层的在线处理系统。光盘在垂直方向同时处理，在称为MDC的圆盘状支架中。多个（多达10个）盘被保存在MDC的拨号载体中，并从一个处理站传送到另一个处理站。 MDC的拨号盘可以在每个处理站中与正常旋转和/或成角度高达70°，使得一个或多个处理源可以同时处理盘。此配置可节省时间并减少所需的进程源的数量和大小。还公开了用于磁性介质图案化的掩模增强工艺，以及与其一起使用的填充和平坦化工艺。

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