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1. 发明申请

WO2009117002A1 ELECTROPHORETICALLY DEPOSITED CATHODE CAPACITOR 审中-公开
标题翻译：电沉积阴极电容器
公开(公告)号：WO2009117002A1
公开(公告)日：2009-09-24
申请号：PCT/US2008/057706
申请日：2008-03-20
申请人： VISHAY SPRAGUE, INC. , BREITHAUPT, Steve, , COHEN, Nissim, , EIDELMAN, Alex, , KATRARO, Reuven,
发明人： BREITHAUPT, Steve, , COHEN, Nissim, , EIDELMAN, Alex, , KATRARO, Reuven,
IPC分类号： H01G9/042
CPC分类号： H01G9/0425 , Y10T29/417
摘要： An electrolytic capacitor (10) includes a metal case (12), a porous pellet anode (18) disposed within the metal case, an electrolyte (16) disposed within the metal case, and a cathode element (14) formed of an elect-rophoretically deposited metal or metal oxide powder of a uniform thickness disposed within the metal case and surrounding the anode. A method of manufacturing an electrolytic capacitor includes providing a metal case (12), electrophoretically depositing on the metal can a refractory metal oxide to form a cathode element (14), and placing a porous pellet anode (18) and an electrolyte (16) within the can such that the cathode element (14) and the anode element (18) being separated by the electrolyte (16).
摘要翻译：电解电容器（10）包括金属壳体（12），设置在金属壳体内的多孔质颗粒阳极（18），设置在金属壳体内的电解质（16）和由电 - 经均匀厚度的金属或金属氧化物粉末沉积在金属壳体内并围绕阳极。一种制造电解电容器的方法包括：提供金属壳体（12），在金属罐上电泳沉积难熔金属氧化物以形成阴极元件（14），以及放置多孔颗粒阳极（18）和电解质（16）在阴极内使得阴极元件（14）和阳极元件（18）被电解质（16）分开。

2. 发明申请

WO2011053880A2 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO2011053880A2
公开(公告)日：2011-05-05
申请号：PCT/US2010/054877
申请日：2010-10-29
申请人： VISHAY-SILICONIX , PATTANAYAK, Deva , OWYANG, King , KASEM, Mohammed , TERRILL, Kyle , KATRARO, Reuven , CHEN, Kuo-In , CHOI, Calvin , CHEN, Qufei , LUI, Kam Hong , XU, Robert , WONG, Ronald
发明人： PATTANAYAK, Deva , OWYANG, King , KASEM, Mohammed , TERRILL, Kyle , KATRARO, Reuven , CHEN, Kuo-In , CHOI, Calvin , CHEN, Qufei , LUI, Kam Hong , XU, Robert , WONG, Ronald
IPC分类号： H01L21/60 , H01L21/28
CPC分类号： H01L29/7809 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L29/408 , H01L29/41766 , H01L29/45 , H01L29/456 , H01L29/66734 , H01L29/7813 , H01L2224/0401 , H01L2224/05 , H01L2224/05552 , H01L2224/05554 , H01L2224/06051 , H01L2224/13007 , H01L2224/13014 , H01L2224/13023 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.
摘要翻译：半导体器件（例如，倒装芯片）包括通过中间层与漏极接触分离的衬底层。通过中间层的沟槽状馈通元件用于在器件工作时电连接漏极接触和衬底层。

3. 发明申请

WO2008150262A1 CERAMIC DIELECTRIC FORMULATION FOR BROAD BAND UHF ANTENNA 审中-公开
标题翻译：用于宽带UHF天线的陶瓷电介质制剂
公开(公告)号：WO2008150262A1
公开(公告)日：2008-12-11
申请号：PCT/US2007/013442
申请日：2007-06-07
申请人： VISHAY INTERTECHNOLOGY, INC. , BERSHADSKY, Eli, , KRAVCHIK, Marina, , KATRARO, Reuven, , BEN-BASSAT, David, , ALON, Dani,
发明人： BERSHADSKY, Eli, , KRAVCHIK, Marina, , KATRARO, Reuven, , BEN-BASSAT, David, , ALON, Dani,
IPC分类号： C04B35/645 , H01G4/12
CPC分类号： H01Q9/0485 , C04B35/47 , C04B2235/3208 , C04B2235/3215 , C04B2235/3229 , C04B2235/3236 , C04B2235/3244 , C04B2235/3248 , C04B2235/3262 , C04B2235/3281 , C04B2235/3298 , C04B2235/349 , C04B2235/36 , H01G4/1227 , H01Q1/38
摘要： A dielectric ceramic composition has a dielectric constant, K, of at least 200 and a dielectric loss, DF, of 0.0006 or less at 1 MHz. The dielectric ceramic composition may be formed by sintering by firing in air without a controlled atmosphere. The dielectric ceramic composition may have a major component of 92.49 to 97.5 wt.% containing 60.15 to 68.2 wt.% strontium titanate, 11.02 to 23.59 wt.% calcium titanate and 7.11 to 21.32 wt. % barium titanate; and a minor component of 2.50 to 7.51 wt.% containing 1.18 to 3.55 wt% calcium zirconate, 0.50 to 1.54 wt.% bismuth trioxide, 0.2 to 0.59 wt.% zirconia, 0.02 to 0.07 wt.% manganese dioxide, 0.12 to 0.35 wt.% zinc oxide, 0.12 to 0.35 wt.% lead-free glass frit, 0.24 to 0.71 wt.% kaolin clay and 0.12 to 0.35 wt.% cerium oxide. UHF antennas and monolithic ceramic components may use the dielectric ceramic composition.
摘要翻译：介电陶瓷组合物的介电常数K至少为200，介电损耗DF在1MHz时为0.0006以下。电介质陶瓷组合物可以通过在没有受控气氛的空气中烧制而烧结而形成。电介质陶瓷组合物可以具有92.49至97.5重量％的主成分，其含有60.15至68.2重量％的钛酸锶，11.02至23.59重量％的钛酸钙和7.11至21.32重量％的钛酸锶。％钛酸钡; 和2.50〜7.51重量％的次要成分，含有1.18〜3.55重量％的锆酸钙，0.50〜1.54重量％的三氧化铋，0.2〜0.59重量％的氧化锆，0.02〜0.07重量％的二氧化锰，0.12〜0.35重量％的氧化锌，0.12-0.35重量％的无铅玻璃料，0.24-0.71重量％的高岭土和0.12-0.35重量％的氧化铈。 UHF天线和单片陶瓷组件可以使用介电陶瓷组合物。

4. 发明申请

WO2007130110A1 HIGH PRECISION CAPACITOR WITH STANDOFF 审中-公开
标题翻译：高精度电容器与标准
公开(公告)号：WO2007130110A1
公开(公告)日：2007-11-15
申请号：PCT/US2006/032304
申请日：2006-08-18
申请人： VISHAY INTERTECHNOLOGY, INC. , GOLDBERGER, Haim, , KATRARO, Reuven, , GOZALY, Doron,
发明人： GOLDBERGER, Haim, , KATRARO, Reuven, , GOZALY, Doron,
IPC分类号： H01G2/06 , H01L21/00
CPC分类号： H01G4/228 , H01G4/33 , H01L2224/11
摘要： An electronic component such as a capacitor includes a substrate having first and second principal surfaces, a dielectric layer overlaying the first principal surface of the substrate, a first electrode, and a second electrode. There is a passivation layer overlaying the first and second electrodes, a first opening being formed in the passivation layer over the first electrode and a second opening being formed in the passivation layer over the second electrode. A first bottom electrode termination is positioned in the first opening and a second bottom electrode termination is positioned in the second opening. The first bottom electrode termination is electrically connected to the first electrode and the second bottom electrode termination is electrically connected to the second electrode. A standoff is positioned between the first bottom electrode termination and the second bottom electrode termination and attached to the passivation layer to thereby provide support for the electronic component when mounted. The standoff provides resistance to tilting.
摘要翻译：诸如电容器的电子部件包括具有第一和第二主表面的基板，覆盖基板的第一主表面的电介质层，第一电极和第二电极。存在覆盖第一和第二电极的钝化层，第一开口形成在第一电极上的钝化层中，第二开口形成在第二电极上的钝化层中。第一底部电极终端位于第一开口中，而第二底部电极终端位于第二开口中。第一底部电极端子电连接到第一电极，第二底部电极端子电连接到第二电极。间隔件位于第一底部电极端子和第二底部电极端子之间并且附接到钝化层，从而在安装时为电子部件提供支撑。对立提供了对倾斜的抵抗力。

5. 发明申请

WO2011053880A3 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO2011053880A3
公开(公告)日：2011-08-04
申请号：PCT/US2010054877
申请日：2010-10-29
申请人： VISHAY SILICONIX , PATTANAYAK DEVA , OWYANG KING , KASEM MOHAMMED , TERRILL KYLE , KATRARO REUVEN , CHEN KUO-IN , CHOI CALVIN , CHEN QUFEI , LUI KAM HONG , XU ROBERT , WONG RONALD
发明人： PATTANAYAK DEVA , OWYANG KING , KASEM MOHAMMED , TERRILL KYLE , KATRARO REUVEN , CHEN KUO-IN , CHOI CALVIN , CHEN QUFEI , LUI KAM HONG , XU ROBERT , WONG RONALD
IPC分类号： H01L21/60 , H01L21/28
CPC分类号： H01L29/7809 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L29/408 , H01L29/41766 , H01L29/45 , H01L29/456 , H01L29/66734 , H01L29/7813 , H01L2224/0401 , H01L2224/05 , H01L2224/05552 , H01L2224/05554 , H01L2224/06051 , H01L2224/13007 , H01L2224/13014 , H01L2224/13023 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.
摘要翻译：半导体器件（例如，倒装芯片）包括通过中间层与漏极触点分开的衬底层。当装置被操作时，穿过中间层的沟槽状馈通元件被用于电连接漏极接触件和衬底层。

6. 发明申请

WO2010028138A3 BULK CAPACITOR AND METHOD 审中-公开
公开(公告)号：WO2010028138A3
公开(公告)日：2010-03-11
申请号：PCT/US2009/055874
申请日：2009-09-03
申请人： VISHAY SPRAGUE, INC. , KATRARO, Reuven , COHEN, Nissim , KRAVCHIK-VOLFSON, Marina , BERSHADSKY, Eli , BULTITUDE, John
发明人： KATRARO, Reuven , COHEN, Nissim , KRAVCHIK-VOLFSON, Marina , BERSHADSKY, Eli , BULTITUDE, John
IPC分类号： H01G9/042 , H01G9/00 , H01G9/15 , H01G9/052
摘要： A bulk capacitor includes a first electrode formed of a metal foil (12) and a semi-conductive porous ceramic body (18) formed on the metal foil. A dielectric layer (22) is formed on the porous ceramic body for example by oxidation. A conductive medium (16) is deposited on the porous ceramic body filling the pores of the porous ceramic body and forming a second electrode. The capacitor can then be encapsulated with various layers and can include conventional electrical terminations. A method of manufacturing a bulk capacitor includes forming a conductive porous ceramic body on a first electrode formed of a metal foil, oxidizing to form a dielectric layer and filling the porous body with a conductive medium to form a second electrode. A thin semi-conductive ceramic layer can also be disposed between the metal foil and the porous ceramic body.

7. 发明申请

WO2010028138A2 BULK CAPACITOR AND METHOD 审中-公开
标题翻译：大容量电容器和方法
公开(公告)号：WO2010028138A2
公开(公告)日：2010-03-11
申请号：PCT/US2009055874
申请日：2009-09-03
申请人： VISHAY SPRAGUE INC , KATRARO REUVEN , COHEN NISSIM , KRAVCHIK-VOLFSON MARINA , BERSHADSKY ELI , BULTITUDE JOHN
发明人： KATRARO REUVEN , COHEN NISSIM , KRAVCHIK-VOLFSON MARINA , BERSHADSKY ELI , BULTITUDE JOHN
IPC分类号： H01G4/06 , H01G7/00
CPC分类号： H01G9/15 , H01G9/0032 , H01G9/052 , H01G9/055 , Y10T29/435
摘要： A bulk capacitor includes a first electrode formed of a metal foil and a semi-conductive porous ceramic body formed on the metal foil. A dielectric layer is formed on the porous ceramic body for example by oxidation. A conductive medium is deposited on the porous ceramic body filling the pores of the porous ceramic body and forming a second electrode. The capacitor can then be encapsulated with various layers and can include conventional electrical terminations. A method of manufacturing a bulk capacitor includes forming a conductive porous ceramic body on a first electrode formed of a metal foil, oxidizing to form a dielectric layer and filling the porous body with a conductive medium to form a second electrode. A thin semi-conductive ceramic layer can also be disposed between the metal foil and the porous ceramic body.
摘要翻译：大容量电容器包括由金属箔形成的第一电极和形成在金属箔上的半导体多孔陶瓷体。例如通过氧化在多孔陶瓷体上形成电介质层。导电介质沉积在填充多孔陶瓷体的孔隙并形成第二电极的多孔陶瓷体上。然后电容器可以用各种层封装，并且可以包括常规的电终端。制造大容量电容器的方法包括在由金属箔形成的第一电极上形成导电多孔陶瓷体，氧化以形成电介质层，并用导电介质填充多孔体以形成第二电极。也可以在金属箔和多孔陶瓷体之间设置薄的半导体陶瓷层。

8. 发明申请

WO2004111659A2 METHODS AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT DEVICES 审中-公开
标题翻译：包装集成电路设备的方法和装置
公开(公告)号：WO2004111659A2
公开(公告)日：2004-12-23
申请号：PCT/IL2004/000521
申请日：2004-06-16
申请人： SHELLCASE LTD. , ZILBER, Gil , KATRARO, Reuven , AKSENTON, Julia , OGANESIAN, Vage
发明人： ZILBER, Gil , KATRARO, Reuven , AKSENTON, Julia , OGANESIAN, Vage
IPC分类号： G01R
CPC分类号： H01L24/13 , H01L23/3114 , H01L24/11 , H01L24/12 , H01L24/94 , H01L2224/02319 , H01L2224/02321 , H01L2224/02335 , H01L2224/0236 , H01L2224/024 , H01L2224/0401 , H01L2224/13099 , H01L2224/274 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.
摘要翻译：一种集成封装的集成电路器件，包括集成电路管芯，该集成电路管芯包括具有第一和第二大致平面的表面和边缘表面的结晶衬底和形成在第一大致平坦表面上的有源表面，形成在有源表面上的至少一个芯片级封装层，至少一个电触点形成在所述至少一个芯片级封装层上，所述至少一个电触点通过形成在所述第一大致平坦表面上的至少一个焊盘连接到所述有源表面上的电路。

9. 发明申请

WO2007064372A1 SURFACE MOUNT CHIP CAPACITOR 审中-公开
标题翻译：表面安装芯片电容器
公开(公告)号：WO2007064372A1
公开(公告)日：2007-06-07
申请号：PCT/US2006/031123
申请日：2006-08-10
申请人： VISHAY SPRAGUE, INC. , KATRARO, Reuven , KUSHNAREV, Lilia , COHEN, Nissim , GOLDBERGER, Haim
发明人： KATRARO, Reuven , KUSHNAREV, Lilia , COHEN, Nissim , GOLDBERGER, Haim
IPC分类号： H01G4/00 , H01G9/00
CPC分类号： H01G9/012 , H01G2/065 , H01G9/042 , H01G9/0425 , H01G9/08 , Y10T29/41 , Y10T29/417
摘要： A surface mount chip capacitor includes a metal substrate, a conductive powder element comprising a valve metal and partially surrounding the metal substrate with the metal substrate extending outwardly from the conductive powder towards the anode end of the surface mount chip capacitor, a silver body cathode at least partially surrounding the conductive powder element, a coating formed by vapor-phase deposition surrounding the silver body cathode, an insulative material formed about a portion of the substrate extending outwardly from the conductive powder, a conductive coating formed around the metal substrate at the anode end of the surface mount chip capacitor, an end termination anode electrically connected to the conductive coating at the anode end of the surface mount chip capacitor, and an end termination cathode electrically connected to the silver body cathode at the cathode end of the surface mount chip capacitor. The coating preferably comprises a parylene or a parylene derivative.
摘要翻译：表面安装片式电容器包括金属基板，包括阀金属的导电粉末元件，并且部分地围绕金属基板，金属基板从导电粉末朝向表面安装片式电容器的阳极端向外延伸，银体阴极至少部分地围绕导电粉末元件，通过围绕银体阴极的气相沉积形成的涂层，围绕从导电粉末向外延伸的基板的一部分形成的绝缘材料，在阳极处形成在金属基板周围的导电涂层表面安装片式电容器的端部，与表面贴装电容器的阳极端处的导电涂层电连接的端接端子阳极，以及电连接到表面安装芯片的阴极端处的银体阴极的端部端子阴极电容。涂层优选包含聚对二甲苯或聚对二甲苯衍生物。

10. 发明申请

WO2004111659A3 METHODS AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT DEVICES 审中-公开
标题翻译：包装集成电路设备的方法和装置
公开(公告)号：WO2004111659A3
公开(公告)日：2005-09-09
申请号：PCT/IL2004000521
申请日：2004-06-16
申请人： SHELLCASE LTD , ZILBER GIL , KATRARO REUVEN , AKSENTON JULIA , OGANESIAN VAGE
发明人： ZILBER GIL , KATRARO REUVEN , AKSENTON JULIA , OGANESIAN VAGE
IPC分类号： G01R20060101 , H01L21/44 , H01L23/02 , H01L23/31 , H01L23/485 , H01L23/495
CPC分类号： H01L24/13 , H01L23/3114 , H01L24/11 , H01L24/12 , H01L24/94 , H01L2224/02319 , H01L2224/02321 , H01L2224/02335 , H01L2224/0236 , H01L2224/024 , H01L2224/0401 , H01L2224/13099 , H01L2224/274 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： An integrally packaged integrated circuit device (10) including an integrated circuit die (22) including a crystalline substrate having first and second generally planar surfaces (26) and edge surfaces (25) and an active surface (24) formed on the first generally planar surface, at least one chip scale packaging layer (20) formed over the active surface and at least one electrical contact being connected to circuitry on the active surface by at least one pad (16) formed on the first generally planar surface.
摘要翻译：一种集成封装的集成电路器件（10），其包括集成电路管芯（22），该集成电路管芯（22）包括具有第一和第二大致平坦表面（26）和边缘表面（25）的结晶衬底和形成在第一大致平面在所述有源表面上形成至少一个芯片级封装层（20），并且至少一个电触点通过形成在所述第一大致平坦表面上的至少一个焊盘（16）连接到所述有源表面上的电路。

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