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1. 发明申请

WO2005004195A3 METHOD AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT DEVICES 审中-公开
标题翻译：包装集成电路设备的方法和装置
公开(公告)号：WO2005004195A3
公开(公告)日：2007-01-25
申请号：PCT/IL2004000589
申请日：2004-07-01
申请人： SHELLCASE LTD , ZILBER GIL , AKSENTON JULIA , OGANESIAN VAGE
发明人： ZILBER GIL , AKSENTON JULIA , OGANESIAN VAGE
IPC分类号： H01L27/15 , H01L20060101 , H01L21/00 , H01L21/44 , H01L21/48 , H01L21/50 , H01L23/06 , H01L23/31 , H01L29/22 , H01L29/267 , H01L31/0203 , H01L31/0232 , H01L31/12 , H01L33/48 , H01L33/62
CPC分类号： H01L27/14618 , H01L23/3114 , H01L24/11 , H01L27/14621 , H01L27/14632 , H01L27/14683 , H01L27/14685 , H01L27/14687 , H01L31/0203 , H01L31/02327 , H01L33/385 , H01L33/486 , H01L33/62 , H01L2224/0231 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05671 , H01L2224/1147 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging layer formed over the semiconductor circuitry and the first generally planar surface, an insulation layer formed over the second generally planar surface and the edge surfaces and at least one electrical conductor formed directly on the insulation layer overlying the second generally planar surface, the at least one electrical conductor being connected to the circuitry by at least one pad formed directly on the first generally planar surface.
摘要翻译：一种集成封装的集成电路器件，包括集成电路管芯，该集成电路管芯包括具有第一和第二大致平面的表面和边缘表面的晶体衬底和形成在第一大致平坦表面上的半导体电路，形成在半导体电路上的至少一个芯片级封装层和第一大致平坦的表面，形成在第二大体上平坦的表面和边缘表面上的绝缘层，以及直接形成在绝缘层上的至少一个电导体，覆盖在第二大体上平坦的表面上，所述至少一个电导体通过至少一个衬垫直接形成在第一大致平坦的表面上。

2. 发明申请

WO0251217A3 PACKAGED INTEGRATED CIRCUITS AND METHODS OF PRODUCING THEREOF 审中-公开
标题翻译：包装集成电路及其生产方法
公开(公告)号：WO0251217A3
公开(公告)日：2003-07-24
申请号：PCT/IL0101183
申请日：2001-12-19
申请人： SHELLCASE LTD , BADIHI AVNER
发明人： BADIHI AVNER
IPC分类号： H01L23/12 , H01L23/31 , H01L23/485 , H01L23/498 , H01L23/52 , H01L25/04 , H01L25/10 , H01L25/18 , H01L27/146 , H01L33/00 , H01L23/02 , H01L21/50 , H01L23/544
CPC分类号： H01L24/02 , H01L23/3114 , H01L23/49805 , H01L24/96 , H01L24/97 , H01L25/105 , H01L27/14643 , H01L33/62 , H01L2221/6834 , H01L2225/1023 , H01L2225/1058 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01058 , H01L2924/01078 , H01L2924/14
摘要： A packaged integrated circuit (10) and method for producing thereof including an integrated circuit substrate lying in a substrate plane (24) and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface (20) and at least some of the plurality of electrical contacts extending onto the second planar surface (22).
摘要翻译：一种封装集成电路（10）及其制造方法，包括位于基板平面（24）中并具有形成在其上的电路的集成电路基板，封装集成电路基板的封装，并且限定第一和第二平坦表面，衬底平面和多个电触头，每个电触点分别连接到衬底平面处的电路，所述多个电触头中的至少一些延伸到第一平面表面（20）上，并且所述多个电触头中的至少一些延伸到第二平面（22）。

3. 发明申请

WO1997047040A1 I.C. DEVICE WITH CONCEALED CONDUCTOR LINES 审中-公开
标题翻译：我知道了。带导体导线的器件
公开(公告)号：WO1997047040A1
公开(公告)日：1997-12-11
申请号：PCT/EP1996002342
申请日：1996-05-30
申请人： SHELLCASE LTD. , BADEHI, Pierre
发明人： SHELLCASE LTD.
IPC分类号： H01L23/58
CPC分类号： H01L23/57 , H01L2924/0002 , H01L2924/00
摘要： This application discloses an integrated circuit device (10) comprising an integrated circuit die having top (16) and bottom (17) surfaces formed of electrically insulative and mechanically protective material and electrically insulative edge surfaces having exposed sections of conductive pads, the protective material being resistant to plastic dissolving solvents, and the integrated circuit die being readily damageable upon physical tampering with the integrated circuit device (10). A method for production of an integrated circuit device (10) which is resistant to techniques employed to remove integrated circuit packaging is also disclosed.
摘要翻译：本申请公开了一种集成电路器件（10），其包括集成电路管芯，其具有由电绝缘和机械保护材料形成的顶部（16）和底部（17）表面，以及具有导电焊盘暴露部分的电绝缘边缘表面，所述保护材料耐塑性溶解溶剂，并且集成电路管芯在物理篡改集成电路器件（10）时容易损坏。还公开了一种用于消除集成电路封装技术的集成电路器件（10）的制造方法。

4. 发明申请

WO2004111659A2 METHODS AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT DEVICES 审中-公开
标题翻译：包装集成电路设备的方法和装置
公开(公告)号：WO2004111659A2
公开(公告)日：2004-12-23
申请号：PCT/IL2004/000521
申请日：2004-06-16
申请人： SHELLCASE LTD. , ZILBER, Gil , KATRARO, Reuven , AKSENTON, Julia , OGANESIAN, Vage
发明人： ZILBER, Gil , KATRARO, Reuven , AKSENTON, Julia , OGANESIAN, Vage
IPC分类号： G01R
CPC分类号： H01L24/13 , H01L23/3114 , H01L24/11 , H01L24/12 , H01L24/94 , H01L2224/02319 , H01L2224/02321 , H01L2224/02335 , H01L2224/0236 , H01L2224/024 , H01L2224/0401 , H01L2224/13099 , H01L2224/274 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.
摘要翻译：一种集成封装的集成电路器件，包括集成电路管芯，该集成电路管芯包括具有第一和第二大致平面的表面和边缘表面的结晶衬底和形成在第一大致平坦表面上的有源表面，形成在有源表面上的至少一个芯片级封装层，至少一个电触点形成在所述至少一个芯片级封装层上，所述至少一个电触点通过形成在所述第一大致平坦表面上的至少一个焊盘连接到所述有源表面上的电路。

5. 发明申请

WO1996036675A1 BONDING MACHINE 审中-公开
标题翻译：粘接机
公开(公告)号：WO1996036675A1
公开(公告)日：1996-11-21
申请号：PCT/EP1996001747
申请日：1996-04-25
申请人： SHELLCASE LTD. , BADEHI, Pierre
发明人： SHELLCASE LTD.
IPC分类号： C09J05/00
CPC分类号： B29C65/7847 , B29C65/483 , B29C65/485 , B29C65/521 , B29C66/1122 , B29C66/452 , B29C66/8242 , B29C66/8322 , B29C66/91212 , B29C66/91213 , B29C66/91231 , B29C66/91421 , B29C66/91431 , B29C66/9241 , B29C66/929 , B29C66/961 , C09J5/00
摘要： This invention discloses a method of bonding a lower substrate with an upper substrate comprising applying an adhesive (56) on at least one of the lower (12) and the upper (14) substrates, and rotating the lower and the upper substrates thereby to create a centrifugal force which causes the adhesive to spread between the lower and the upper substrates with a substantially uniform thickness, while applying a pressure upon the upper substrate thereby to bond the lower and the upper substrates. The invention also discloses an apparatus for bonding the lower substrate with the upper substrate.
摘要翻译：本发明公开了一种将下基板与上基板结合的方法，包括在下（12）和上（14）基板中的至少一个上施加粘合剂（56），并旋转下基板和上基板，从而形成使粘合剂以大致均匀的厚度在下基板和上基板之间铺展的离心力，同时向上基板施加压力从而结合下基板和上基板。本发明还公开了一种用于将下基板与上基板结合的装置。

6. 发明申请

WO1997050281A1 FILTER CHIP 审中-公开
标题翻译：过滤芯片
公开(公告)号：WO1997050281A1
公开(公告)日：1997-12-31
申请号：PCT/IL1996000029
申请日：1996-06-27
申请人： SHELLCASE LTD. , BADEHI, Pierre
发明人： SHELLCASE LTD.
IPC分类号： H05K01/14
CPC分类号： H01F41/042 , H01L23/645 , H01L2924/0002 , H05K1/16 , H05K3/0097 , H01L2924/00
摘要： Disclosed is a technique for producing a multiple element SMD passive circuit device (200) having formed thereon a plurality of passive circuit elements (206) including waferwise forming a multiplicity of groups of passive circuit elements on a wafer, each group including a plurality of passive circuit elements having contact pads (214), waferwise forming SMD connection pads by depositing conductive material over the wafer in electrical conductive engagement with the passive circuit elements, and thereafter dividing the wafer into a multiplicity of multiple element SMD passive circuit devices.
摘要翻译：公开了一种生产多元素SMD无源电路器件（200）的技术，该器件在其上形成有多个无源电路元件（206），包括在晶片上晶圆形成多组无源电路元件，每组包括多个被动具有接触焊盘（214）的电路元件，通过在晶片上沉积导电材料与无源电路元件导电接合，然后将晶片分成多个多元件SMD无源电路器件，从而晶片化地形成SMD连接焊盘。

7. 发明申请

WO1996002071A1 PACKAGED INTEGRATED CIRCUIT 审中-公开
标题翻译：包装集成电路
公开(公告)号：WO1996002071A1
公开(公告)日：1996-01-25
申请号：PCT/EP1995002702
申请日：1995-07-07
申请人： SHELLCASE LTD. , BADEHI, Pierre
发明人： SHELLCASE LTD.
IPC分类号： H01L23/485
CPC分类号： H01L24/02 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2924/0001 , H01L2924/0101 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01051 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/00014
摘要： The present invention seeks to provide an improved packaged integrated circuit including: a silicon substrate (10), at least one metal layer (16) formed on the silicon substrate and defining a plurality of pads, at least one packaging layer (12) formed over the at least one metal layer, a plurality of solder leads (20) formed on an exterior surface (22) of the at least one packaging layer, and electrical connections (19) extending directly from individual ones of the plurality of pads to individual ones of solder leads.
摘要翻译：本发明寻求提供一种改进的封装集成电路，包括：硅衬底（10），形成在硅衬底上并限定多个衬垫的至少一个金属层（16），至少一个封装层（12）所述至少一个金属层，形成在所述至少一个封装层的外表面（22）上的多个焊接引线（20）以及从所述多个焊盘中的单个焊盘直接延伸到各个焊盘的电连接（19）的焊锡引线。

8. 发明申请

WO2004111659A3 METHODS AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT DEVICES 审中-公开
标题翻译：包装集成电路设备的方法和装置
公开(公告)号：WO2004111659A3
公开(公告)日：2005-09-09
申请号：PCT/IL2004000521
申请日：2004-06-16
申请人： SHELLCASE LTD , ZILBER GIL , KATRARO REUVEN , AKSENTON JULIA , OGANESIAN VAGE
发明人： ZILBER GIL , KATRARO REUVEN , AKSENTON JULIA , OGANESIAN VAGE
IPC分类号： G01R20060101 , H01L21/44 , H01L23/02 , H01L23/31 , H01L23/485 , H01L23/495
CPC分类号： H01L24/13 , H01L23/3114 , H01L24/11 , H01L24/12 , H01L24/94 , H01L2224/02319 , H01L2224/02321 , H01L2224/02335 , H01L2224/0236 , H01L2224/024 , H01L2224/0401 , H01L2224/13099 , H01L2224/274 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： An integrally packaged integrated circuit device (10) including an integrated circuit die (22) including a crystalline substrate having first and second generally planar surfaces (26) and edge surfaces (25) and an active surface (24) formed on the first generally planar surface, at least one chip scale packaging layer (20) formed over the active surface and at least one electrical contact being connected to circuitry on the active surface by at least one pad (16) formed on the first generally planar surface.
摘要翻译：一种集成封装的集成电路器件（10），其包括集成电路管芯（22），该集成电路管芯（22）包括具有第一和第二大致平坦表面（26）和边缘表面（25）的结晶衬底和形成在第一大致平面在所述有源表面上形成至少一个芯片级封装层（20），并且至少一个电触点通过形成在所述第一大致平坦表面上的至少一个焊盘（16）连接到所述有源表面上的电路。

9. 发明申请

WO2005004195A2 METHOD AND APPARATUS FOR PACKAGING INTEGRATED CIRCUIT DEVICES 审中-公开
标题翻译：用于封装集成电路器件的方法和装置
公开(公告)号：WO2005004195A2
公开(公告)日：2005-01-13
申请号：PCT/IL2004/000589
申请日：2004-07-01
申请人： SHELLCASE LTD. , ZILBER, Gil , AKSENTON, Julia , OGANESIAN, Vage
发明人： ZILBER, Gil , AKSENTON, Julia , OGANESIAN, Vage
IPC分类号： H01L
CPC分类号： H01L27/14618 , H01L23/3114 , H01L24/11 , H01L27/14621 , H01L27/14632 , H01L27/14683 , H01L27/14685 , H01L27/14687 , H01L31/0203 , H01L31/02327 , H01L33/385 , H01L33/486 , H01L33/62 , H01L2224/0231 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05671 , H01L2224/1147 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging layer formed over the semiconductor circuitry and the first generally planar surface, an insulation layer formed over the second generally planar surface and the edge surfaces and at least one electrical conductor formed directly on the insulation layer overlying the second generally planar surface, the at least one electrical conductor being connected to the circuitry by at least one pad formed directly on the first generally planar surface.
摘要翻译：一种集成封装的集成电路器件，包括集成电路管芯，该集成电路管芯包括具有第一和第二大体上平坦的表面和边缘表面的晶体衬底和形成在第一大致平坦表面上的半导体电路，形成在半导体电路上的至少一个芯片级封装层和第一大致平坦的表面，形成在第二大体上平坦的表面和边缘表面上的绝缘层和直接形成在绝缘层上的至少一个电导体，覆盖在第二大体上平坦的表面上，所述至少一个电导体通过至少一个焊盘直接形成在第一大致平坦的表面上。

10. 发明申请

WO1995019645A1 METHODS AND APPARATUS FOR PRODUCING INTEGRATED CIRCUIT DEVICES 审中-公开
标题翻译：用于生产集成电路设备的方法和装置
公开(公告)号：WO1995019645A1
公开(公告)日：1995-07-20
申请号：PCT/EP1995000097
申请日：1995-01-10
申请人： SHELLCASE LTD. , BADEHI, Pierre
发明人： SHELLCASE LTD.
IPC分类号： H01L23/485
CPC分类号： H01L21/568 , H01L21/6835 , H01L21/78 , H01L24/97 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/00
摘要： A method for producing integrated circuit devices including the steps of producing a plurality of integrated circuits on a wafer having first and second planar surfaces, each of the integrated circuits including a multiplicity of pads, waferwise attaching to both said surfaces of the wafer a layer of protective material, thereafter partially cutting into the wafer and the protective material attached thereto, thereby to define notches along outlines of a plurality of prepackaged integrated circuit devices, forming metal contacts onto the plurality of prepackaged integrated circuit devices while they are still joined together on the wafer, at least a portion of said metal contacts extending into the notches and thereafter separating the plurality of prepackaged integrated circuit devices into individual devices. Integrated circuits produced according to the method are also disclosed and claimed.
摘要翻译：一种用于制造集成电路器件的方法，包括以下步骤：在具有第一和第二平面的晶片上制造多个集成电路，每个集成电路包括多个焊盘，晶片地附着在晶片的两个表面上，保护材料，然后部分地切入晶片和附着于其上的保护材料，从而沿着多个预先包装的集成电路器件的轮廓形成凹口，在多个预先封装的集成电路器件上形成金属触点，同时它们仍然连接在一起晶片，所述金属触点的至少一部分延伸到凹口中，然后将多个预先包装的集成电路器件分离成单独的器件。还公开并要求保护根据该方法生产的集成电路。

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