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1. 发明申请

WO2007146583A2 METHOD OF DESIGNING AN APPLICATION SPECIFIC PROBE CARD TEST SYSTEM 审中-公开
标题翻译：设计应用特定探头卡测试系统的方法
公开(公告)号：WO2007146583A2
公开(公告)日：2007-12-21
申请号：PCT/US2007/069810
申请日：2007-05-25
申请人： FORMFACTOR, INC. , MILLER, Charles, A. , CHRAFT, Matthew, E. , HENSON, Roy, J.
发明人： MILLER, Charles, A. , CHRAFT, Matthew, E. , HENSON, Roy, J.
IPC分类号： G01R31/02
CPC分类号： G01R31/31905 , G01R31/2889 , G01R31/31926 , G01R35/00
摘要： A method is provided for design and programming of a probe card with an on-board programmable controller in a wafer test system. Consideration of introduction of the programmable controller is included in a CAD wafer layout and probe card design process. The CAD design is further loaded into the programmable controller, such as an FPGA to program it: (1) to control direction of signals to particular ICs , even during the test process (2) to generate test vector signals to provide to the ICs , and (3) to receive test signals and process test results from the received signals. In some embodiments, burn-in only testing is provided to limit test system circuitry needed so that with a programmable controller on the probe card, text equipment external to the probe card can be eliminated or significantly reduced from conventional test equipment.
摘要翻译：提供了一种用于在晶片测试系统中设计和编程具有板上可编程控制器的探针卡的方法。引入可编程控制器的考虑因素包括在CAD晶圆布局和探针卡设计过程中。 CAD设计进一步加载到可编程控制器（例如FPGA）中以对其进行编程：（1）甚至在测试过程（2）期间控制信号到特定IC的方向，以产生测试向量信号以提供给IC，和（3）从接收信号接收测试信号和处理测试结果。在一些实施例中，仅提供老化测试以限制所需的测试系统电路，使得利用探针卡上的可编程控制器，可以从常规测试设备消除或显着减少探针卡外部的文本设备。

2. 发明申请

WO2008070466A3 SHARING RESOURCES IN A SYSTEM FOR TESTING SEMICONDUCTOR DEVICES 审中-公开
标题翻译：在测试半导体器件的系统中共享资源
公开(公告)号：WO2008070466A3
公开(公告)日：2008-11-06
申请号：PCT/US2007085483
申请日：2007-11-25
申请人： FORMFACTOR INC , CHRAFT MATTHEW E , ELDRIDGE BENJAMIN N , HENSON ROY J , SPORCK A NICHOLAS
发明人： CHRAFT MATTHEW E , ELDRIDGE BENJAMIN N , HENSON ROY J , SPORCK A NICHOLAS
IPC分类号： G01R31/02
CPC分类号： G01R31/31926 , G01R31/318511
摘要： Probes in a plurality of DUT probe groups can be connected in parallel to a single tester channel. In one aspect, digital potentiometers can be used to effectively switch the tester channel from a probe in one DUT probe group to a probe in another DUT probe group. In another aspect, switches in parallel with a resistor can accomplish such switching. In yet another aspect, a chip select terminal on each DUT can be used to effectively connect and disconnect internal DUT circuitry to the tester channel. Multiple DUT probe groups so connected can be used to create different patterns of DUT probe groups for testing different patterns of DUTs and thus facilitate sharing tester channels.
摘要翻译：多个DUT探针组中的探针可以并行连接到单个测试器通道。在一个方面，可以使用数字电位计来有效地将测试器通道从一个DUT探针组中的探针切换到另一个DUT探针组中的探针。另一方面，与电阻器并联的开关可以完成这种切换。在又一方面，每个DUT上的芯片选择端子可以用于有效连接和断开内部DUT电路与测试器通道的连接。如此连接的多个DUT探针组可用于创建不同模式的DUT探针组，以测试不同DUT的模式，从而便于共享测试器通道。

3. 发明申请

WO2007146583A3 METHOD OF DESIGNING AN APPLICATION SPECIFIC PROBE CARD TEST SYSTEM 审中-公开
标题翻译：设计应用特定探头卡测试系统的方法
公开(公告)号：WO2007146583A3
公开(公告)日：2009-02-26
申请号：PCT/US2007069810
申请日：2007-05-25
申请人： FORMFACTOR INC , MILLER CHARLES A , CHRAFT MATTHEW E , HENSON ROY J
发明人： MILLER CHARLES A , CHRAFT MATTHEW E , HENSON ROY J
IPC分类号： G01R31/02 , G01R1/073 , G01R1/36 , G01R31/28 , G01R31/319 , G01R35/00
CPC分类号： G01R31/31905 , G01R31/2889 , G01R31/31926 , G01R35/00
摘要： A method is provided for design and programming of a probe card with an on-board programmable controller in a wafer test system. Consideration of introduction of the programmable controller is included in a CAD wafer layout and probe card design process. The CAD design is further loaded into the programmable controller, such as an FPGA to program it: (1) to control direction of signals to particular ICs , even during the test process (2) to generate test vector signals to provide to the ICs , and (3) to receive test signals and process test results from the received signals. In some embodiments, burn-in only testing is provided to limit test system circuitry needed so that with a programmable controller on the probe card, text equipment external to the probe card can be eliminated or significantly reduced from conventional test equipment.
摘要翻译：提供了一种用于在晶片测试系统中设计和编程具有板上可编程控制器的探针卡的方法。引入可编程控制器的考虑因素包括在CAD晶圆布局和探针卡设计过程中。 CAD设计进一步加载到可编程控制器（例如FPGA）中以对其进行编程：（1）甚至在测试过程（2）期间控制信号到特定IC的方向，以产生测试向量信号以提供给IC，和（3）从接收信号接收测试信号和处理测试结果。在一些实施例中，仅提供老化测试以限制所需的测试系统电路，使得利用探针卡上的可编程控制器，可以从常规测试设备消除或显着减少探针卡外部的文本设备。

4. 发明申请

WO2008008570A2 SAWING TILE CORNERS ON PROBE CARD SUBSTRATES 审中-公开
标题翻译：在探针卡片基板上锯成角度
公开(公告)号：WO2008008570A2
公开(公告)日：2008-01-17
申请号：PCT/US2007/069816
申请日：2007-05-25
申请人： FORMFACTOR, INC. , ELDRIDGE, Benjamin, N. , MATHEWS, Peter B. , SHINDE, Makarand, S. , HOBBS, Eric D. , HENSON, Roy, J.
发明人： ELDRIDGE, Benjamin, N. , MATHEWS, Peter B. , SHINDE, Makarand, S. , HOBBS, Eric D. , HENSON, Roy, J.
IPC分类号： G01R31/26
CPC分类号： G01R1/07342
摘要： A composite substrate for testing semiconductor devices is formed by selecting a plurality of substantially identical individual substrates, cutting a corner from at least some of the individual substrates in accordance with their position in a final array configuration, and then assembling the individual substrates into the final array configuration. The final array configuration of substrates with corners cut or sawed away conforms more closely to the surface area of a wafer being tested, and can easily fit within space limits of a test environment.
摘要翻译：用于测试半导体器件的复合衬底通过选择多个基本上相同的单独衬底形成，根据它们在最终阵列构型中的位置从至少一些单个衬底切割拐角，然后将各个衬底组装成最终阵列配置。具有切割或锯切的角落的基底的最终阵列配置更接近于正被测试的晶片的表面积，并且可以容易地配合在测试环境的空间极限内。

5. 发明申请

WO2006083856A1 PROGRAMMABLE DEVICES TO ROUTE SIGNALS ON PROBE CARDS 审中-公开
标题翻译：可编程设备用于探测卡上的信号
公开(公告)号：WO2006083856A1
公开(公告)日：2006-08-10
申请号：PCT/US2006/003386
申请日：2006-01-30
申请人： FORMFACTOR, INC. , GRANICHER, Dane, C. , HENSON, Roy, J. , MILLER, Charles, A.
发明人： GRANICHER, Dane, C. , HENSON, Roy, J. , MILLER, Charles, A.
CPC分类号： G01R31/31926 , G01R1/07385 , G01R31/2889
摘要： A probe card of a wafer test system includes one or more programmable Ics , such as FPGAS (150), to provide routing from individual test signal channels to one of multiple probes (16). The programmable ICs can be placed on a base PCB (30) of the probe card, or on a daughtercard (100) attached to the probe card. With programmability, the PCB (30) can be used to switch limited test system channels away from unused probes (16). Programmability further enables a single probe card to more effectively test devices having the same pad array, but having different pin-outs for different device options. Reprogrammability also allows test engineers to re-program as they are debugging a test program. Because the programmable IC (150) typically includes buffers that introduce an unknown delay, in one embodiment measurement of the delay is accomplished by first programming the programmable IC (150) to provide a loop back path to the test system so that buffer delay can be measured, and then reprogramming the programmable IC (150) now with a known delay to connect to a device being tested.
摘要翻译：晶片测试系统的探针卡包括一个或多个可编程IC，例如FPGAS（150），以提供从各个测试信号通道到多个探针（16）之一的路由。可编程IC可以放置在探针卡的基板（30）上，或者放置在附接到探针卡的子卡（100）上。具有可编程性，PCB（30）可用于将有限的测试系统通道从未使用的探头（16）切换出去。可编程性进一步使单个探针卡更有效地测试具有相同焊盘阵列但具有不同引脚的不同器件选项的器件。可重编程序还允许测试工程师在调试测试程序时进行重新编程。因为可编程IC（150）通常包括引入未知延迟的缓冲器，在一个实施例中，通过首先对可编程IC（150）编程以提供到测试系统的回送路径来实现延迟的测量，使得缓冲器延迟可以测量，然后以可知的延迟对可编程IC（150）进行重新编程，以连接到正被测试的设备。

6. 发明申请

WO2006073736A2 PROBE HEAD ARRAYS 审中-公开
标题翻译：探头头阵
公开(公告)号：WO2006073736A2
公开(公告)日：2006-07-13
申请号：PCT/US2005/045582
申请日：2005-12-15
申请人： FORMFACTOR, INC. , HENSON, Roy, J. , LONG, John, M.
发明人： HENSON, Roy, J. , LONG, John, M.
IPC分类号： G01R31/02
CPC分类号： G01R1/07357
摘要： A probe head for testing devices formed on a semiconductor wafer includes a plurality of probe DUT (device under test) arrays. Each device under test includes pads that are urged into pressure contact with probes in a corresponding probe DUT array. The probe arrays patterns have discontinuities such as indentations, protuberances, islands and openings that are opposite at least one device when the probes contact the pads.
摘要翻译：用于测试形成在半导体晶片上的器件的探针头包括多个探针DUT（待测器件）阵列。被测器件中的每一个器件都包含被压入与相应探头DUT阵列中的探头压力接触的焊盘。当探针接触垫时，探针阵列图案具有不连续性，例如凹陷，突起，岛和开口，其与至少一个装置相对。

7. 发明申请

WO2008028171A2 METHOD AND APPARATUS FOR SWITCHING TESTER RESOURCES 审中-公开
标题翻译：用于切换测试资源的方法和装置
公开(公告)号：WO2008028171A2
公开(公告)日：2008-03-06
申请号：PCT/US2007/077467
申请日：2007-09-01
申请人： FORMFACTOR, INC. , SPORCK, A., Nicholas , HENSON, Roy, J.
发明人： SPORCK, A., Nicholas , HENSON, Roy, J.
IPC分类号： G01R31/02
CPC分类号： G01R31/2889 , G01R1/07385
摘要： A contactor device comprising a plurality of probes disposed to contact ones of the electronic devices can be electrically connected to a source of test signals. A switch can be activated electrically connecting a connection to the source of test signals to a selected one of a first group of electrically connected ones of the probes disposed to contact a first set of a plurality of the electronic devices or a second group of electrically connected ones of the probes disposed to contact a second set of a plurality of the electronic devices.
摘要翻译：包括设置成接触电子装置的多个探针的接触器装置可电连接到测试信号源。可以激活开关，将连接到测试信号源的连接电连接到被设置为接触多个电子设备的第一组的第一组电连接的探针中的选定的一个或第二组电连接探针中的一个被设置为接触多个电子设备的第二组。

8. 发明申请

WO2005103740A3 INTELLIGENT PROBE CARD ARCHITECTURE 审中-公开
标题翻译：智能探针卡建筑
公开(公告)号：WO2005103740A3
公开(公告)日：2006-06-29
申请号：PCT/US2005013850
申请日：2005-04-21
申请人： FORMFACTOR INC , MILLER CHARLES A , CHRAFT MATTHEW E , HENSON ROY J
发明人： MILLER CHARLES A , CHRAFT MATTHEW E , HENSON ROY J
IPC分类号： G01R31/02 , G01R1/073 , G01R1/36 , G01R29/00 , G01R31/26 , G01R31/28 , G01R31/319 , G01R35/00 , H01L21/66 , H01R11/18 , H01R13/00 , H01R13/24
CPC分类号： G01R31/31905 , G01R1/07385 , G01R1/36 , G01R31/2889 , G01R35/00
摘要： A probe card for a wafer test system is provided with a number of on board features enabling fan out of a test system controller channel to test multiple DUTs on a wafer, while limiting undesirable effects of fan out on test results. On board features of the probe card include one or more of the following: (a) DUT signal isolation provided by placing resistors in series with each DUT input to isolate failed DUTs; (b) DUT power isolation provided by switches, current limiters, or regulators in series with each DUT power pin to isolate the power supply from failed DUTs; (c) self test provided using an on board micro-controller or FPGA; (d) stacked daughter cards provided as part of the probe card to accommodate the additional on board test circuitry; and (e) use of a interface bus between a base PCB and daughter cards of the probe card, or the test system controller to minimize the number of interface wires between the base PCB and daughter cards or between the base PCB and the test system controller.
摘要翻译：用于晶片测试系统的探针卡具有多个板上特征，使扇出测试系统控制器通道以测试晶片上的多个DUT，同时限制扇出对测试结果的不期望的影响。探头卡的板载功能包括以下一个或多个功能：（a）通过将电阻器与每个DUT输入串联放置来隔离故障DUT提供的DUT信号隔离; （b）与每个DUT电源引脚串联的开关，限流器或稳压器提供的DUT电源隔离，以将电源与失效的DUT隔离; （c）使用板上微控制器或FPGA提供的自检; （d）作为探针卡的一部分提供的堆叠子卡，以适应额外的板上测试电路; 和（e）在基板PCB和探针卡的子卡之间使用接口总线或测试系统控制器以最小化基板PCB和子卡之间或基板和测试系统控制器之间的接口线的数量。

9. 发明申请

WO2005103740A2 INTELLIGENT PROBE CARD ARCHITECTURE 审中-公开
标题翻译：智能探头卡建筑
公开(公告)号：WO2005103740A2
公开(公告)日：2005-11-03
申请号：PCT/US2005/013850
申请日：2005-04-21
申请人： FORMFACTOR, INC. , MILLER, Charles, A. , CHRAFT, Matthew, E. , HENSON, Roy, J.
发明人： MILLER, Charles, A. , CHRAFT, Matthew, E. , HENSON, Roy, J.
IPC分类号： G01R31/02
CPC分类号： G01R31/31905 , G01R1/07385 , G01R1/36 , G01R31/2889 , G01R35/00
摘要： A probe card for a wafer test system is provided with a number of on board features enabling fan out of a test system controller channel to test multiple DUTs on a wafer, while limiting undesirable effects of fan out on test results. On board features of the probe card include one or more of the following: (a) DUT signal isolation provided by placing resistors in series with each DUT input to isolate failed DUTs; (b) DUT power isolation provided by switches, current limiters, or regulators in series with each DUT power pin to isolate the power supply from failed DUTs; (c) self test provided using an on board micro-controller or FPGA; (d) stacked daughter cards provided as part of the probe card to accommodate the additional on board test circuitry; and (e) use of a interface bus between a base PCB and daughter cards of the probe card, or the test system controller to minimize the number of interface wires between the base PCB and daughter cards or between the base PCB and the test system controller.
摘要翻译：用于晶片测试系统的探针卡具有许多机载功能，使得扇出测试系统控制器通道能够测试晶片上的多个DUT，同时限制扇出对测试结果的不期望的影响。探头卡的板上功能包括以下一个或多个功能：（a）通过将电阻与每个DUT输入串联放置来隔离故障的DUT，提供DUT信号隔离; （b）与每个DUT电源引脚串联的开关，限流器或稳压器提供的DUT电源隔离，以将电源与失效的DUT隔离; （c）使用板上微控制器或FPGA提供的自检; （d）作为探针卡的一部分提供的堆叠子卡，以容纳附加的板上测试电路; 以及（e）在基板PCB和探针卡的子卡之间使用接口总线或测试系统控制器以最小化基板PCB和子卡之间或者基板PCB与测试系统控制器之间的接口线的数量。

10. 发明申请

WO2008008570A3 SAWING TILE CORNERS ON PROBE CARD SUBSTRATES 审中-公开
标题翻译：在探针卡片基板上锯成角度
公开(公告)号：WO2008008570A3
公开(公告)日：2009-02-12
申请号：PCT/US2007069816
申请日：2007-05-25
申请人： FORMFACTOR INC , ELDRIDGE BENJAMIN N , MATHEWS PETER B , SHINDE MAKARAND S , HOBBS ERIC D , HENSON ROY J
发明人： ELDRIDGE BENJAMIN N , MATHEWS PETER B , SHINDE MAKARAND S , HOBBS ERIC D , HENSON ROY J
IPC分类号： H01L31/00
CPC分类号： G01R1/07342
摘要： A composite substrate for testing semiconductor devices is formed by selecting a plurality of substantially identical individual substrates, cutting a corner from at least some of the individual substrates in accordance with their position in a final array configuration, and then assembling the individual substrates into the final array configuration. The final array configuration of substrates with corners cut or sawed away conforms more closely to the surface area of a wafer being tested, and can easily fit within space limits of a test environment.
摘要翻译：用于测试半导体器件的复合衬底通过选择多个基本上相同的单独衬底形成，根据它们在最终阵列构型中的位置从至少一些单个衬底切割拐角，然后将各个衬底组装成最终阵列配置。具有切割或锯切的角落的基底的最终阵列配置更接近于正被测试的晶片的表面积，并且可以容易地配合在测试环境的空间极限内。

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