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    • 3. 发明申请
    • METHOD OF DESIGNING AN APPLICATION SPECIFIC PROBE CARD TEST SYSTEM
    • 设计应用特定探头卡测试系统的方法
    • WO2007146583A2
    • 2007-12-21
    • PCT/US2007/069810
    • 2007-05-25
    • FORMFACTOR, INC.MILLER, Charles, A.CHRAFT, Matthew, E.HENSON, Roy, J.
    • MILLER, Charles, A.CHRAFT, Matthew, E.HENSON, Roy, J.
    • G01R31/02
    • G01R31/31905G01R31/2889G01R31/31926G01R35/00
    • A method is provided for design and programming of a probe card with an on-board programmable controller in a wafer test system. Consideration of introduction of the programmable controller is included in a CAD wafer layout and probe card design process. The CAD design is further loaded into the programmable controller, such as an FPGA to program it: (1) to control direction of signals to particular ICs , even during the test process (2) to generate test vector signals to provide to the ICs , and (3) to receive test signals and process test results from the received signals. In some embodiments, burn-in only testing is provided to limit test system circuitry needed so that with a programmable controller on the probe card, text equipment external to the probe card can be eliminated or significantly reduced from conventional test equipment.
    • 提供了一种用于在晶片测试系统中设计和编程具有板上可编程控制器的探针卡的方法。 引入可编程控制器的考虑因素包括在CAD晶圆布局和探针卡设计过程中。 CAD设计进一步加载到可编程控制器(例如FPGA)中以对其进行编程:(1)甚至在测试过程(2)期间控制信号到特定IC的方向,以产生测试向量信号以提供给IC, 和(3)从接收信号接收测试信号和处理测试结果。 在一些实施例中,仅提供老化测试以限制所需的测试系统电路,使得利用探针卡上的可编程控制器,可以从常规测试设备消除或显着减少探针卡外部的文本设备。
    • 4. 发明申请
    • INTELLIGENT PROBE CARD ARCHITECTURE
    • 智能探针卡建筑
    • WO2005103740A3
    • 2006-06-29
    • PCT/US2005013850
    • 2005-04-21
    • FORMFACTOR INCMILLER CHARLES ACHRAFT MATTHEW EHENSON ROY J
    • MILLER CHARLES ACHRAFT MATTHEW EHENSON ROY J
    • G01R31/02G01R1/073G01R1/36G01R29/00G01R31/26G01R31/28G01R31/319G01R35/00H01L21/66H01R11/18H01R13/00H01R13/24
    • G01R31/31905G01R1/07385G01R1/36G01R31/2889G01R35/00
    • A probe card for a wafer test system is provided with a number of on board features enabling fan out of a test system controller channel to test multiple DUTs on a wafer, while limiting undesirable effects of fan out on test results. On board features of the probe card include one or more of the following: (a) DUT signal isolation provided by placing resistors in series with each DUT input to isolate failed DUTs; (b) DUT power isolation provided by switches, current limiters, or regulators in series with each DUT power pin to isolate the power supply from failed DUTs; (c) self test provided using an on board micro-controller or FPGA; (d) stacked daughter cards provided as part of the probe card to accommodate the additional on board test circuitry; and (e) use of a interface bus between a base PCB and daughter cards of the probe card, or the test system controller to minimize the number of interface wires between the base PCB and daughter cards or between the base PCB and the test system controller.
    • 用于晶片测试系统的探针卡具有多个板上特征,使扇出测试系统控制器通道以测试晶片上的多个DUT,同时限制扇出对测试结果的不期望的影响。 探头卡的板载功能包括以下一个或多个功能:(a)通过将电阻器与每个DUT输入串联放置来隔离故障DUT提供的DUT信号隔离; (b)与每个DUT电源引脚串联的开关,限流器或稳压器提供的DUT电源隔离,以将电源与失效的DUT隔离; (c)使用板上微控制器或FPGA提供的自检; (d)作为探针卡的一部分提供的堆叠子卡,以适应额外的板上测试电路; 和(e)在基板PCB和探针卡的子卡之间使用接口总线或测试系统控制器以最小化基板PCB和子卡之间或基板和测试系统控制器之间的接口线的数量 。
    • 5. 发明申请
    • INTELLIGENT PROBE CARD ARCHITECTURE
    • 智能探头卡建筑
    • WO2005103740A2
    • 2005-11-03
    • PCT/US2005/013850
    • 2005-04-21
    • FORMFACTOR, INC.MILLER, Charles, A.CHRAFT, Matthew, E.HENSON, Roy, J.
    • MILLER, Charles, A.CHRAFT, Matthew, E.HENSON, Roy, J.
    • G01R31/02
    • G01R31/31905G01R1/07385G01R1/36G01R31/2889G01R35/00
    • A probe card for a wafer test system is provided with a number of on board features enabling fan out of a test system controller channel to test multiple DUTs on a wafer, while limiting undesirable effects of fan out on test results. On board features of the probe card include one or more of the following: (a) DUT signal isolation provided by placing resistors in series with each DUT input to isolate failed DUTs; (b) DUT power isolation provided by switches, current limiters, or regulators in series with each DUT power pin to isolate the power supply from failed DUTs; (c) self test provided using an on board micro-controller or FPGA; (d) stacked daughter cards provided as part of the probe card to accommodate the additional on board test circuitry; and (e) use of a interface bus between a base PCB and daughter cards of the probe card, or the test system controller to minimize the number of interface wires between the base PCB and daughter cards or between the base PCB and the test system controller.
    • 用于晶片测试系统的探针卡具有许多机载功能,使得扇出测试系统控制器通道能够测试晶片上的多个DUT,同时限制扇出对测试结果的不期望的影响。 探头卡的板上功能包括以下一个或多个功能:(a)通过将电阻与每个DUT输入串联放置来隔离故障的DUT,提供DUT信号隔离; (b)与每个DUT电源引脚串联的开关,限流器或稳压器提供的DUT电源隔离,以将电源与失效的DUT隔离; (c)使用板上微控制器或FPGA提供的自检; (d)作为探针卡的一部分提供的堆叠子卡,以容纳附加的板上测试电路; 以及(e)在基板PCB和探针卡的子卡之间使用接口总线或测试系统控制器以最小化基板PCB和子卡之间或者基板PCB与测试系统控制器之间的接口线的数量 。