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1. 发明申请

WO2017201001A1 EFFICIENT HUB SWITCHING FOR MOBILE NETWORK DEVICES 审中-公开
标题翻译：移动网络设备的高效集线器交换
公开(公告)号：WO2017201001A1
公开(公告)日：2017-11-23
申请号：PCT/US2017/032839
申请日：2017-05-16
申请人： HALL, David, R. , HALL, Mark, D. , BOSWELL, Craig , KNIGHT, Jedediah
发明人： HALL, David, R. , HALL, Mark, D. , BOSWELL, Craig , KNIGHT, Jedediah
IPC分类号： H04W28/16 , H04L27/10 , H04L29/08
摘要： A system for efficient hub switching of mobile network devices is disclosed. The system includes a peripheral device (PD), a first control hub, and a second control hub. The PD includes a wireless long range transceiver and a microcontroller, and is controlled wirelessly by the first control hub. The first control hub and second network hub each have a wireless long range transceiver, hardware processors, and hardware memory that stores system operation information. The system operation information includes instructions for controlling the PD. Additionally, the system operation information includes instructions for listening for a response from the PD. The listening instructions include an expected response timeframe after the control instructions are sent. The system operation information further includes instructions for requesting the second control hub control the PD. Furthermore, the system operation information includes instructions for taking over control of the PD.
摘要翻译：公开了一种用于移动网络设备的高效集线器交换的系统。该系统包括外围设备（PD），第一控制集线器和第二控制集线器。 PD包括一个无线长距离收发器和一个微控制器，并由第一个控制集线器进行无线控制。第一控制集线器和第二网络集线器各自具有无线长距离收发器，硬件处理器和存储系统操作信息的硬件存储器。系统操作信息包括用于控制PD的指令。另外，系统操作信息包括用于收听来自PD的响应的指令。收听指令包括控制指令发送后的预期响应时间范围。系统操作信息还包括用于请求第二控制集线器控制PD的指令。此外，系统操作信息包括用于接管PD的控制的指令。

2. 发明申请

WO2007136884A3 EPI T-GATE STRUCTURE FOR CoSi2 EXTENDIBILITY 审中-公开
标题翻译： EPI T-GATE结构的CoSi2可扩展性
公开(公告)号：WO2007136884A3
公开(公告)日：2008-11-06
申请号：PCT/US2007060302
申请日：2007-01-10
申请人： FREESCALE SEMICONDUCTOR INC , HALL MARK D , JAWARANI DHARMESH , SHROFF MEHUL D , TRAVIS EDWARD O
发明人： HALL MARK D , JAWARANI DHARMESH , SHROFF MEHUL D , TRAVIS EDWARD O
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/28114 , H01L29/42376 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor process and apparatus provide a T-shaped structure (96) formed from a polysilicon structure (10) and an epitaxially grown polysilicon layer (70) and having a narrower bottom critical dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may be formed from a first material (such as CoSi 2 ) in at least the upper region (90) of the T-shaped structure (96) without incurring the increased resistance caused by agglomeration and voiding that can occur with certain silicides at the smaller critical dimensions.
摘要翻译：半导体工艺和装置提供由多晶硅结构（10）和外延生长的多晶硅层（70）形成并且具有较窄的底部临界尺寸（例如，等于或低于40nm）形成的T形结构（96）和更大的顶部临界尺寸（例如，在40nm以上），使得硅化物可以在至少T形的上部区域（90）中由第一材料（例如CoSi 2 N 2）形成，结构（96），而不会导致由于在较小临界尺寸下某些硅化物可能发生的附聚和空隙引起的增加的电阻。

3. 发明申请

WO2007098302A2 POLY PRE-DOPING ANNEALS FOR IMPROVED GATE PROFILES 审中-公开
标题翻译：用于改进的浇口型材的聚合预涂布
公开(公告)号：WO2007098302A2
公开(公告)日：2007-08-30
申请号：PCT/US2007060654
申请日：2007-01-18
申请人： FREESCALE SEMICONDUCTOR INC , SHROFF MEHUL D , HALL MARK D , GRUDOWSKI PAUL , STEPHENS TAB A , STOUT PHILLIP J , ADETUTU OLUBUNMI O
发明人： SHROFF MEHUL D , HALL MARK D , GRUDOWSKI PAUL , STEPHENS TAB A , STOUT PHILLIP J , ADETUTU OLUBUNMI O
IPC分类号： H01L21/336
CPC分类号： H01L21/28035 , H01L21/28123 , H01L21/32155 , H01L21/823437 , H01L21/823828
摘要： A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (32) formed over a substrate (11), thereby forming an etched gate (92, 94) having a vertical sidewall profile by implanting the gate stack (32) with a nitrogen (42) and a dopant (52) and then heating the polysilicon gate stack (32) at a selected temperature using rapid thermal annealing (62) to anneal the nitrogen and dopant so that subsequent etching of the polysilicon gate stack (32) creates an etched gate (92, 94) having more idealized vertical gate sidewall profiles.
摘要翻译：半导体工艺和设备使用预定的图案化和蚀刻步骤序列来蚀刻在衬底（11）上形成的栅极堆叠（32），从而通过注入栅叠层而形成具有垂直侧壁轮廓的蚀刻栅极（92,94）（32）和氮（42）和掺杂剂（52），然后使用快速热退火（62）在选定的温度下加热多晶硅栅极堆叠（32）以退火氮和掺杂剂，以便后续蚀刻多晶硅栅极堆叠（32）产生具有更理想化的垂直栅极侧壁轮廓的蚀刻栅极（92,94）。

4. 发明申请

WO2010014287A1 SEMICONDUCTOR DEVICES WITH EXTENDED ACTIVE REGIONS 审中-公开
标题翻译：具有扩展活动区域的半导体器件
公开(公告)号：WO2010014287A1
公开(公告)日：2010-02-04
申请号：PCT/US2009/043457
申请日：2009-05-11
申请人： FREESCALE SEMICONDUCTOR INC. , HALL, Mark, D. , ABELN, Glenn, C. , FU, Chong-Cheng
发明人： HALL, Mark, D. , ABELN, Glenn, C. , FU, Chong-Cheng
IPC分类号： H01L21/76 , H01L21/336 , H01L21/8244
CPC分类号： H01L21/76232 , H01L21/8252 , H01L21/84 , H01L27/0207 , H01L27/11
摘要： A method of making a semiconductor device (10) is achieved in and over a semiconductor layer. A trench (18, 20, 22) is formed adjacent to a first active area (24, 26, 28, 30). The trench is filled with insulating material (32, 34, 36). A masking feature (48, 50, 52) is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench (54, 56, 58, 60). A first epitaxial region (62, 66) is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region.
摘要翻译：在半导体层中和之上实现制造半导体器件（10）的方法。与第一有效区域（24,26,28,30）相邻地形成沟槽（18,20,22）。沟槽填充绝缘材料（32,34,36）。掩模特征（48,50,52）形成在沟槽的中心部分上，以在掩蔽特征的第一侧和第一有效区域之间露出沟槽的第一侧。蚀刻到沟槽的第一侧的步骤在沟槽（54,56,58,60）中留下第一凹槽。在第一凹槽中生长第一外延区域（62,66）以使第一有源区域延伸以包括第一凹部，从而形成延伸的第一有源区域。

5. 发明申请

WO2005013320A2 A SEMICONDUCTOR DEVICE HAVING AN ORGANIC ANTI-REFLECTIVE COATING (ARC) AND METHOD THEREFOR 审中-公开
标题翻译：具有有机抗反射涂层（ARC）的半导体器件及其方法
公开(公告)号：WO2005013320A2
公开(公告)日：2005-02-10
申请号：PCT/US2004/022434
申请日：2004-07-13
申请人： FREESCALE SEMICONDUCTOR, INC. , REBER, Douglas, M. , HALL, Mark, D. , JUNKER, Kurt, H. , PATTERSON, Kyle, W. , STEPHENS, Tab Allen , THEISS, Edward, K. , SRIKANTESWARA, Dakshina-Murthy , WRIGHT, Marilyn Irene
发明人： REBER, Douglas, M. , HALL, Mark, D. , JUNKER, Kurt, H. , PATTERSON, Kyle, W. , STEPHENS, Tab Allen , THEISS, Edward, K. , SRIKANTESWARA, Dakshina-Murthy , WRIGHT, Marilyn Irene
IPC分类号： H01L
CPC分类号： H01L21/02164 , H01L21/02274 , H01L21/0276 , H01L21/0332 , H01L21/0338 , H01L21/28035 , H01L21/28123 , H01L21/31612 , H01L21/32139 , H01L29/6659 , H01L29/7833 , Y10S438/902 , Y10S438/952
摘要： In a making a semiconductor device (10), a patterning stack above a conductive material (16) that is to be etched has a patterned photoresist layer (22) that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer (20). The TEOS layer (20) is deposited at a lower temperature than is conventional. The low temperature TEOS layer (20) is over an organic anti-reflective coating (ARC) (18) that is over the conductive layer (16). The low temperature TEOS layer (20) provides adhesion between the organic ARC (18) and the photoresist (22), has low defectivity, operates as a hard mask, and serves as a phase shift layer that helps, in combination with the organic ARC (18), to reduce undesired reflection.
摘要翻译：在制造半导体器件（10）中，待蚀刻的导电材料（16）上方的图案化叠层具有图案化的光致抗蚀剂层（22），其用于将四乙基原硅酸盐（TEOS）层（20）。 TEOS层（20）在比常规的较低温度下沉积。低温TEOS层（20）位于导电层（16）上方的有机抗反射涂层（ARC）（18）之上。低温TEOS层（20）提供有机ARC（18）和光致抗蚀剂（22）之间的粘附，具有低缺陷性，作为硬掩模操作，并且用作相移层，其与有机ARC （18），以减少不期望的反射。

6. 发明申请

WO2005013320A3 A SEMICONDUCTOR DEVICE HAVING AN ORGANIC ANTI-REFLECTIVE COATING (ARC) AND METHOD THEREFOR 审中-公开
标题翻译：具有有机抗反射涂层（ARC）的半导体器件及其方法
公开(公告)号：WO2005013320A3
公开(公告)日：2005-04-07
申请号：PCT/US2004022434
申请日：2004-07-13
申请人： FREESCALE SEMICONDUCTOR INC , REBER DOUGLAS M , HALL MARK D , JUNKER KURT H , PATTERSON KYLE W , STEPHENS TAB ALLEN , THEISS EDWARD K , SRIKANTESWARA DAKSHINA-MURTHY , WRIGHT MARILYN IRENE
发明人： REBER DOUGLAS M , HALL MARK D , JUNKER KURT H , PATTERSON KYLE W , STEPHENS TAB ALLEN , THEISS EDWARD K , SRIKANTESWARA DAKSHINA-MURTHY , WRIGHT MARILYN IRENE
IPC分类号： H01L21/027 , H01L21/033 , H01L21/28 , H01L21/3213 , H01L21/332
CPC分类号： H01L21/02164 , H01L21/02274 , H01L21/0276 , H01L21/0332 , H01L21/0338 , H01L21/28035 , H01L21/28123 , H01L21/31612 , H01L21/32139 , H01L29/6659 , H01L29/7833 , Y10S438/902 , Y10S438/952
摘要： In a making a semiconductor device (10), a patterning stack above a conductive material (16) that is to be etched has a patterned photoresist layer (22) that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer (20). The TEOS layer (20) is deposited at a lower temperature than is conventional. The low temperature TEOS layer (20) is over an organic anti-reflective coating (ARC) (18) that is over the conductive layer (16). The low temperature TEOS layer (20) provides adhesion between the organic ARC (18) and the photoresist (22), has low defectivity, operates as a hard mask, and serves as a phase shift layer that helps, in combination with the organic ARC (18), to reduce undesired reflection.
摘要翻译：在制造半导体器件（10）中，要被蚀刻的导电材料（16）上方的图案化叠层具有图案化的光致抗蚀剂层（22），其用于图案化下面的四乙基原硅酸盐（TEOS）层（20）。 TEOS层（20）在比常规温度更低的温度下沉积。低温TEOS层（20）位于导电层（16）上方的有机抗反射涂层（ARC）（18）之上。低温TEOS层（20）提供了有机ARC（18）和光致抗蚀剂（22）之间的粘附力，具有低缺陷率，作为硬掩模起作用并且用作相移层，其有助于与有机ARC （18），以减少不希望的反射。

7. 发明申请

WO2008109221A1 TRENCH FORMATION IN A SEMICONDUCTOR MATERIAL 审中-公开
标题翻译：半导体材料中的形成
公开(公告)号：WO2008109221A1
公开(公告)日：2008-09-12
申请号：PCT/US2008/053133
申请日：2008-02-06
申请人： FREESCALE SEMICONDUCTOR INC. , HALL, Mark D. , ABELN, Glenn C. , GRANT, John M.
发明人： HALL, Mark D. , ABELN, Glenn C. , GRANT, John M.
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76283 , H01L21/84 , H01L27/11 , H01L27/1104 , H01L29/66757 , H01L29/78621
摘要： A semiconductor device (10) is formed on a semiconductor layer (16). A gate dielectric layer (18) is formed over the semiconductor layer. A layer of gate material (20) is formed over the gate dielectric layer. The layer of gate material is patterned to form a gate structure (20). Using the gate structure as a mask, an implant (24) into the semiconductor layer is performed. To form a first patterned gate structure (20) and a trench (42) in the semiconductor layer (16) surrounding a first portion (28) and a second portion (30) of the semiconductor layer and the gate, an etch through the gate structure (20) and the semiconductor layer (16) is performed. The trench (42) is filled with insulating material (46).
摘要翻译：半导体器件（10）形成在半导体层（16）上。栅电介质层（18）形成在半导体层上。栅极材料层（20）形成在栅极介质层上。图案化栅极材料层以形成栅极结构（20）。使用栅极结构作为掩模，进行到半导体层中的注入（24）。为了在半导体层（16）中形成围绕半导体层和栅极的第一部分（28）和第二部分（30）的第一图案化栅极结构（20）和沟槽（42），通过栅极结构（20）和半导体层（16）。沟槽（42）填充有绝缘材料（46）。

8. 发明申请

WO2007136884A2 EPI T-GATE STRUCTURE FOR CoSi2 EXTENDIBILITY 审中-公开
标题翻译： EPI T-GATE结构的CoSi2可扩展性
公开(公告)号：WO2007136884A2
公开(公告)日：2007-11-29
申请号：PCT/US2007/060302
申请日：2007-01-10
申请人： FREESCALE SEMICONDUCTOR INC. , HALL, Mark D. , JAWARANI, Dharmesh , SHROFF, Mehul D. , TRAVIS, Edward O.
发明人： HALL, Mark D. , JAWARANI, Dharmesh , SHROFF, Mehul D. , TRAVIS, Edward O.
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/28114 , H01L29/42376 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor process and apparatus provide a T-shaped structure (96) formed from a polysilicon structure (10) and an epitaxially grown polysilicon layer (70) and having a narrower bottom critical dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may be formed from a first material (such as CoSi2) in at least the upper region (90) of the T-shaped structure (96) without incurring the increased resistance caused by agglomeration and voiding that can occur with certain silicides at the smaller critical dimensions.
摘要翻译：半导体工艺和装置提供由多晶硅结构（10）和外延生长的多晶硅层（70）形成并且具有较窄的底部临界尺寸（例如，等于或低于40nm）形成的T形结构（96）和较大的顶部临界尺寸（例如，40nm以上），使得硅化物可以在至少T形结构（96）的上部区域（90）中由第一材料（例如CoSi 2）形成，而不会增加在较小的临界尺寸下，某些硅化物可能会发生聚集和排空引起的电阻。

9. 发明申请

WO2007098302A3 POLY PRE-DOPING ANNEALS FOR IMPROVED GATE PROFILES 审中-公开
公开(公告)号：WO2007098302A3
公开(公告)日：2007-08-30
申请号：PCT/US2007/060654
申请日：2007-01-18
申请人： FREESCALE SEMICONDUCTOR INC. , SHROFF, Mehul D. , HALL, Mark D. , GRUDOWSKI, Paul , STEPHENS, Tab A. , STOUT, Phillip J. , ADETUTU, Olubunmi O.
发明人： SHROFF, Mehul D. , HALL, Mark D. , GRUDOWSKI, Paul , STEPHENS, Tab A. , STOUT, Phillip J. , ADETUTU, Olubunmi O.
IPC分类号： H01L21/336
摘要： A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (32) formed over a substrate (11), thereby forming an etched gate (92, 94) having a vertical sidewall profile by implanting the gate stack (32) with a nitrogen (42) and a dopant (52) and then heating the polysilicon gate stack (32) at a selected temperature using rapid thermal annealing (62) to anneal the nitrogen and dopant so that subsequent etching of the polysilicon gate stack (32) creates an etched gate (92, 94) having more idealized vertical gate sidewall profiles.

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