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1. 发明申请

WO2008094745A1 ELECTRONIC DEVICE INCLUDING INSULATING LAYERS HAVING DIFFERENT STRAINS AND A PROCESS FOR FORMING THE ELECTRONIC DEVICE 审中-公开
标题翻译：包括具有不同应变的绝缘层的电子器件和用于形成电子器件的工艺
公开(公告)号：WO2008094745A1
公开(公告)日：2008-08-07
申请号：PCT/US2008/050969
申请日：2008-01-14
申请人： FREESCALE SEMICONDUCTOR INC. , GRUDOWSKI, Paul, A. , KOLAGUNTA, Venkat, R. , SHROFF, Mehul, D.
发明人： GRUDOWSKI, Paul, A. , KOLAGUNTA, Venkat, R. , SHROFF, Mehul, D.
IPC分类号： H01L21/76
CPC分类号： H01L27/1203 , H01L21/0214 , H01L21/0217 , H01L21/02266 , H01L21/0228 , H01L21/31105 , H01L21/3143 , H01L21/3185 , H01L21/76264 , H01L21/84 , H01L29/78 , H01L29/7843
摘要： An electronic device can include a field isolation region (22) and a first insulating layer (42) having a first strain and having a portion (421), which from a top view, lies entirely within the field isolation region (22). The electronic device can also include a second insulating layer (72) having a second strain different from the first strain and including an opening. From a top view, the portion (421) of the first insulating layer (72) can lie within the opening in the second insulating layer (72). In one embodiment, the field isolation region (22) can include a dummy structure (241) and the portion of the first insulating layer (421) can overlie the dummy structure (241). A process of forming the electronic device can include forming an island portion (421) of an insulating layer (72) wherein from a top view, the island portion (421) lies entirely within the field isolation region (22).
摘要翻译：电子设备可以包括场隔离区域（22）和具有第一应变的第一绝缘层（42），并具有从顶视图完全位于场隔离区域（22）内的部分（421）。电子设备还可以包括具有不同于第一应变的第二应变并且包括开口的第二绝缘层（72）。从顶部看，第一绝缘层（72）的部分（421）可以位于第二绝缘层（72）的开口内。在一个实施例中，场隔离区域（22）可以包括虚拟结构（241），并且第一绝缘层（421）的部分可以覆盖虚拟结构（241）。形成电子器件的方法可以包括形成绝缘层（72）的岛部（421），其中从顶视图，岛部（421）完全位于场隔离区（22）内。

2. 发明申请

WO2007100929A2 METHOD AND APPARATUS FOR INDICATING DIRECTIONALITY IN INTEGRATED CIRCUIT MANUFACTURING 审中-公开
标题翻译：一体化电路制造中指示方向的方法与装置
公开(公告)号：WO2007100929A2
公开(公告)日：2007-09-07
申请号：PCT/US2007060257
申请日：2007-01-09
申请人： FREESCALE SEMICONDUCTOR INC , TRAVIS EDWARD O , SHROFF MEHUL D , SMELTZER DONALD E , SMITH TRACI L
发明人： TRAVIS EDWARD O , SHROFF MEHUL D , SMELTZER DONALD E , SMITH TRACI L
CPC分类号： H01L23/544 , H01L22/34 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (10) includes a visually discernable indicator (128, 130, 132, or 134) formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit.
摘要翻译：集成电路（10）包括形成为集成电路的一部分的视觉辨别指示器（128,130,132或134），以指示集成电路的非视觉辨别特性的方向性。

3. 发明申请

WO2007136884A2 EPI T-GATE STRUCTURE FOR CoSi2 EXTENDIBILITY 审中-公开
标题翻译： EPI T-GATE结构的CoSi2可扩展性
公开(公告)号：WO2007136884A2
公开(公告)日：2007-11-29
申请号：PCT/US2007/060302
申请日：2007-01-10
申请人： FREESCALE SEMICONDUCTOR INC. , HALL, Mark D. , JAWARANI, Dharmesh , SHROFF, Mehul D. , TRAVIS, Edward O.
发明人： HALL, Mark D. , JAWARANI, Dharmesh , SHROFF, Mehul D. , TRAVIS, Edward O.
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/28114 , H01L29/42376 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor process and apparatus provide a T-shaped structure (96) formed from a polysilicon structure (10) and an epitaxially grown polysilicon layer (70) and having a narrower bottom critical dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may be formed from a first material (such as CoSi2) in at least the upper region (90) of the T-shaped structure (96) without incurring the increased resistance caused by agglomeration and voiding that can occur with certain silicides at the smaller critical dimensions.
摘要翻译：半导体工艺和装置提供由多晶硅结构（10）和外延生长的多晶硅层（70）形成并且具有较窄的底部临界尺寸（例如，等于或低于40nm）形成的T形结构（96）和较大的顶部临界尺寸（例如，40nm以上），使得硅化物可以在至少T形结构（96）的上部区域（90）中由第一材料（例如CoSi 2）形成，而不会增加在较小的临界尺寸下，某些硅化物可能会发生聚集和排空引起的电阻。

4. 发明申请

WO2007098302A3 POLY PRE-DOPING ANNEALS FOR IMPROVED GATE PROFILES 审中-公开
公开(公告)号：WO2007098302A3
公开(公告)日：2007-08-30
申请号：PCT/US2007/060654
申请日：2007-01-18
申请人： FREESCALE SEMICONDUCTOR INC. , SHROFF, Mehul D. , HALL, Mark D. , GRUDOWSKI, Paul , STEPHENS, Tab A. , STOUT, Phillip J. , ADETUTU, Olubunmi O.
发明人： SHROFF, Mehul D. , HALL, Mark D. , GRUDOWSKI, Paul , STEPHENS, Tab A. , STOUT, Phillip J. , ADETUTU, Olubunmi O.
IPC分类号： H01L21/336
摘要： A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (32) formed over a substrate (11), thereby forming an etched gate (92, 94) having a vertical sidewall profile by implanting the gate stack (32) with a nitrogen (42) and a dopant (52) and then heating the polysilicon gate stack (32) at a selected temperature using rapid thermal annealing (62) to anneal the nitrogen and dopant so that subsequent etching of the polysilicon gate stack (32) creates an etched gate (92, 94) having more idealized vertical gate sidewall profiles.

5. 发明申请

WO2007097814A2 SEMICONDUCTOR DEVICE HAVING STRESSORS AND METHOD FOR FORMING 审中-公开
标题翻译：具有应力的半导体器件和形成方法
公开(公告)号：WO2007097814A2
公开(公告)日：2007-08-30
申请号：PCT/US2006/060638
申请日：2006-11-08
申请人： FREESCALE SEMICONDUCTOR INC. , SHROFF, Mehul D. , GRUDOWSKI, Paul A.
发明人： SHROFF, Mehul D. , GRUDOWSKI, Paul A.
IPC分类号： H01L29/94
CPC分类号： H01L29/7843 , H01L21/3185 , H01L21/76802 , H01L21/76829 , H01L21/823807 , H01L21/823864 , H01L21/823871 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： N channel (113, 115) and P channel (111) transistors are enhanced by applying stressor layers of tensile (128) and compressive (126), respectively, over them. A previously unknown problem was discovered concerning the two stressor layers, which both may conveniently be nitride but made somewhat differently. The two stressors have different etch rates which results in deleterious effects when etching a contact hole at the interface between the two stressors. A contact to a gate is often preferably half way between N and P channel transistors which is also the seemingly best location for the border between the two stressor layers. The contact etch at the border can result in pitting of the underlying gate structure or in residual nitride in the contact hole. Therefore, it has been found beneficial to ensure that each contact (154) is at least some predetermined distance from the stressor of the opposite type from the one the contact is passing through.
摘要翻译：通过分别在其上施加拉伸（128）和压缩（126）的应力层，增强了N沟道（113,115）和P沟道（111）晶体管。发现关于两个应力层的以前未知的问题，这两个应力层都可以方便地是氮化的，但是略有不同。两个应力源具有不同的蚀刻速率，这在蚀刻两个应激物之间的界面处的接触孔时会产生有害影响。与栅极的接触通常优选地在N沟道晶体管和P沟道晶体管之间的中间，这也是两个应力层之间边界看似最好的位置。在边界处的接触蚀刻可导致底层栅极结构或接触孔中的残余氮化物的点蚀。因此，已经发现有益的是确保每个接触件（154）与接触件通过的相反类型的应力器至少一定的距离。

6. 发明申请

WO2007100929A3 METHOD AND APPARATUS FOR INDICATING DIRECTIONALITY IN INTEGRATED CIRCUIT MANUFACTURING 审中-公开
公开(公告)号：WO2007100929A3
公开(公告)日：2007-09-07
申请号：PCT/US2007/060257
申请日：2007-01-09
申请人： FREESCALE SEMICONDUCTOR INC. , TRAVIS, Edward O. , SHROFF, Mehul D. , SMELTZER, Donald E. , SMITH, Traci L.
发明人： TRAVIS, Edward O. , SHROFF, Mehul D. , SMELTZER, Donald E. , SMITH, Traci L.
IPC分类号： H01L23/544
摘要： An integrated circuit (10) includes a visually discernable indicator (128, 130, 132, or 134) formed as part of the integrated circuit to indicate a directionality of a non-visually discernable characteristic of the integrated circuit.

7. 发明申请

WO2006068788A3 LAYOUT MODIFICATION USING MULTILAYER-BASED CONSTRAINTS 审中-公开
标题翻译：使用基于多层次约束的布局修改
公开(公告)号：WO2006068788A3
公开(公告)日：2007-06-21
申请号：PCT/US2005043218
申请日：2005-11-30
申请人： FREESCALE SEMICONDUCTOR INC , LUCAS KEVIN D , BOONE ROBERT E , SHROFF MEHUL D , STROZEWSKI KIRK J , YUAN CHI-MIN , PORTER JASON T
发明人： LUCAS KEVIN D , BOONE ROBERT E , SHROFF MEHUL D , STROZEWSKI KIRK J , YUAN CHI-MIN , PORTER JASON T
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for improving manufacturability of a design (310) includes performing space or enclosure checks (320) on multiple interacting layers (330, 360, 370, 380) of a layout design and then using the resulting space or enclosure data to move predetermined feature edges in an altered design database (340) to decrease the risk of features widths, feature spaces or feature enclosures being patterned smaller than designed. In some embodiments, the upsized features are larger in the wafer circuit pattern than are drawn in a designed database. The method for improving manufacturability of a design, in some embodiments, is stored on a computer readable storage medium.
摘要翻译：一种用于改进设计（310）的可制造性的方法包括在布局设计的多个交互层（330,360,370,380）上执行空间或外壳检查（320），然后使用所得到的空间或外壳数据来移动预定特征改变设计数据库（340）中的边缘，以减少特征宽度，特征空间或特征外壳的图案比设计的风险更小。在一些实施例中，晶片电路图案中的大尺寸特征比在设计的数据库中绘制的特征更大。在一些实施例中，用于提高设计的可制造性的方法被存储在计算机可读存储介质上。

8. 发明申请

WO2007136884A3 EPI T-GATE STRUCTURE FOR CoSi2 EXTENDIBILITY 审中-公开
标题翻译： EPI T-GATE结构的CoSi2可扩展性
公开(公告)号：WO2007136884A3
公开(公告)日：2008-11-06
申请号：PCT/US2007060302
申请日：2007-01-10
申请人： FREESCALE SEMICONDUCTOR INC , HALL MARK D , JAWARANI DHARMESH , SHROFF MEHUL D , TRAVIS EDWARD O
发明人： HALL MARK D , JAWARANI DHARMESH , SHROFF MEHUL D , TRAVIS EDWARD O
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/28114 , H01L29/42376 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor process and apparatus provide a T-shaped structure (96) formed from a polysilicon structure (10) and an epitaxially grown polysilicon layer (70) and having a narrower bottom critical dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may be formed from a first material (such as CoSi 2 ) in at least the upper region (90) of the T-shaped structure (96) without incurring the increased resistance caused by agglomeration and voiding that can occur with certain silicides at the smaller critical dimensions.
摘要翻译：半导体工艺和装置提供由多晶硅结构（10）和外延生长的多晶硅层（70）形成并且具有较窄的底部临界尺寸（例如，等于或低于40nm）形成的T形结构（96）和更大的顶部临界尺寸（例如，在40nm以上），使得硅化物可以在至少T形的上部区域（90）中由第一材料（例如CoSi 2 N 2）形成，结构（96），而不会导致由于在较小临界尺寸下某些硅化物可能发生的附聚和空隙引起的增加的电阻。

9. 发明申请

WO2007097814A3 SEMICONDUCTOR DEVICE HAVING STRESSORS AND METHOD FOR FORMING 审中-公开
标题翻译：具有应力的半导体器件和形成方法
公开(公告)号：WO2007097814A3
公开(公告)日：2008-10-09
申请号：PCT/US2006060638
申请日：2006-11-08
申请人： FREESCALE SEMICONDUCTOR INC , SHROFF MEHUL D , GRUDOWSKI PAUL A
发明人： SHROFF MEHUL D , GRUDOWSKI PAUL A
IPC分类号： H01L21/335 , H01L27/088
CPC分类号： H01L21/823807 , H01L21/3185 , H01L21/76802 , H01L21/76829 , H01L21/823864 , H01L21/823871 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/7843
摘要： N channel (113, 115) and P channel (111) transistors are enhanced by applying stressor layers of tensile (128) and compressive (126), respectively, over them. A previously unknown problem was discovered concerning the two stressor layers, which both may conveniently be nitride but made somewhat differently. The two stressors have different etch rates which results in deleterious effects when etching a contact hole at the interface between the two stressors. A contact to a gate is often preferably half way between N and P channel transistors which is also the seemingly best location for the border between the two stressor layers. The contact etch at the border can result in pitting of the underlying gate structure or in residual nitride in the contact hole. Therefore, it has been found beneficial to ensure that each contact (154) is at least some predetermined distance from the stressor of the opposite type from the one the contact is passing through.
摘要翻译：通过分别在其上施加拉伸（128）和压缩（126）的应力层，增强了N沟道（113,115）和P沟道（111）晶体管。发现关于两个应力层的以前未知的问题，这两个应力层都可以方便地是氮化的，但是略有不同。两个应力源具有不同的蚀刻速率，这在蚀刻两个应激物之间的界面处的接触孔时会产生有害影响。与栅极的接触通常优选地在N沟道晶体管和P沟道晶体管之间的中间，这也是两个应力层之间边界看似最好的位置。在边界处的接触蚀刻可导致底层栅极结构或接触孔中的残余氮化物的点蚀。因此，已经发现有益的是确保每个接触件（154）与接触件通过的相反类型的应力器至少一定的距离。

10. 发明申请

WO2007098302A2 POLY PRE-DOPING ANNEALS FOR IMPROVED GATE PROFILES 审中-公开
标题翻译：用于改进的浇口型材的聚合预涂布
公开(公告)号：WO2007098302A2
公开(公告)日：2007-08-30
申请号：PCT/US2007060654
申请日：2007-01-18
申请人： FREESCALE SEMICONDUCTOR INC , SHROFF MEHUL D , HALL MARK D , GRUDOWSKI PAUL , STEPHENS TAB A , STOUT PHILLIP J , ADETUTU OLUBUNMI O
发明人： SHROFF MEHUL D , HALL MARK D , GRUDOWSKI PAUL , STEPHENS TAB A , STOUT PHILLIP J , ADETUTU OLUBUNMI O
IPC分类号： H01L21/336
CPC分类号： H01L21/28035 , H01L21/28123 , H01L21/32155 , H01L21/823437 , H01L21/823828
摘要： A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (32) formed over a substrate (11), thereby forming an etched gate (92, 94) having a vertical sidewall profile by implanting the gate stack (32) with a nitrogen (42) and a dopant (52) and then heating the polysilicon gate stack (32) at a selected temperature using rapid thermal annealing (62) to anneal the nitrogen and dopant so that subsequent etching of the polysilicon gate stack (32) creates an etched gate (92, 94) having more idealized vertical gate sidewall profiles.
摘要翻译：半导体工艺和设备使用预定的图案化和蚀刻步骤序列来蚀刻在衬底（11）上形成的栅极堆叠（32），从而通过注入栅叠层而形成具有垂直侧壁轮廓的蚀刻栅极（92,94）（32）和氮（42）和掺杂剂（52），然后使用快速热退火（62）在选定的温度下加热多晶硅栅极堆叠（32）以退火氮和掺杂剂，以便后续蚀刻多晶硅栅极堆叠（32）产生具有更理想化的垂直栅极侧壁轮廓的蚀刻栅极（92,94）。

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