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1. 发明申请

WO2006096232A2 METHOD OF MAKING AN INTEGRATED CIRCUIT BY MODIFYING A DESIGN LAYOUT BY ACCOUNTING FOR A PARAMETER THAT VARIES BASED ON A LOCATION WITHIN AN EXPOSURE FIELD 审中-公开
标题翻译：通过对基于在接触场中的位置的变量的参数进行会计修改设计布局来制作集成电路的方法
公开(公告)号：WO2006096232A2
公开(公告)日：2006-09-14
申请号：PCT/US2006/000612
申请日：2006-01-10
申请人： FREESCALE SEMICONDUCTOR, INC. , LUCAS, Kevin, D. , BOONE, Robert, E. , PATTERSON, Kyle, W.
发明人： LUCAS, Kevin, D. , BOONE, Robert, E. , PATTERSON, Kyle, W.
IPC分类号： G03F7/00
CPC分类号： G03F7/70441 , G03F7/70941
摘要： An original layout of an integrated circuit is modified using optical proximity correction (OPC) to obtain a second layout. During OPC, a sensitivity to flare for each feature is conveniently identified (2). To map (4) the flare, the amplitude of intensity is mapped over a field of exposure, which is typically a rectangle-shaped area corresponding to an exposure of a stepper. The field of exposure is divided into regions in which a region is characterized as having substantially the same amplitude throughout. For each feature a decision (14) is made whether to make a further correction or not. If correction is desired, the amount of correction is based in part on the region in which the feature is located and the sensitivity of the feature. This same approach is applicable to other properties than flare that vary based on the location within the field of exposure.
摘要翻译：使用光学邻近校正（OPC）来修改集成电路的原始布局以获得第二布局。在OPC期间，可以方便地识别每个特征对flare的敏感度（2）。为了映射（4）耀斑，将强度的幅度映射在曝光场上，该场通常是对应于步进曝光的矩形区域。曝光领域被划分为其中区域被表征为具有基本上相同振幅的区域。对于每个特征，做出是否进一步校正的决定（14）。如果需要校正，校正量部分地基于特征所在的区域和特征的灵敏度。这种相同的方法适用于根据暴露领域内的位置而变化的其他特性。

2. 发明申请

WO2005013320A2 A SEMICONDUCTOR DEVICE HAVING AN ORGANIC ANTI-REFLECTIVE COATING (ARC) AND METHOD THEREFOR 审中-公开
标题翻译：具有有机抗反射涂层（ARC）的半导体器件及其方法
公开(公告)号：WO2005013320A2
公开(公告)日：2005-02-10
申请号：PCT/US2004/022434
申请日：2004-07-13
申请人： FREESCALE SEMICONDUCTOR, INC. , REBER, Douglas, M. , HALL, Mark, D. , JUNKER, Kurt, H. , PATTERSON, Kyle, W. , STEPHENS, Tab Allen , THEISS, Edward, K. , SRIKANTESWARA, Dakshina-Murthy , WRIGHT, Marilyn Irene
发明人： REBER, Douglas, M. , HALL, Mark, D. , JUNKER, Kurt, H. , PATTERSON, Kyle, W. , STEPHENS, Tab Allen , THEISS, Edward, K. , SRIKANTESWARA, Dakshina-Murthy , WRIGHT, Marilyn Irene
IPC分类号： H01L
CPC分类号： H01L21/02164 , H01L21/02274 , H01L21/0276 , H01L21/0332 , H01L21/0338 , H01L21/28035 , H01L21/28123 , H01L21/31612 , H01L21/32139 , H01L29/6659 , H01L29/7833 , Y10S438/902 , Y10S438/952
摘要： In a making a semiconductor device (10), a patterning stack above a conductive material (16) that is to be etched has a patterned photoresist layer (22) that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer (20). The TEOS layer (20) is deposited at a lower temperature than is conventional. The low temperature TEOS layer (20) is over an organic anti-reflective coating (ARC) (18) that is over the conductive layer (16). The low temperature TEOS layer (20) provides adhesion between the organic ARC (18) and the photoresist (22), has low defectivity, operates as a hard mask, and serves as a phase shift layer that helps, in combination with the organic ARC (18), to reduce undesired reflection.
摘要翻译：在制造半导体器件（10）中，待蚀刻的导电材料（16）上方的图案化叠层具有图案化的光致抗蚀剂层（22），其用于将四乙基原硅酸盐（TEOS）层（20）。 TEOS层（20）在比常规的较低温度下沉积。低温TEOS层（20）位于导电层（16）上方的有机抗反射涂层（ARC）（18）之上。低温TEOS层（20）提供有机ARC（18）和光致抗蚀剂（22）之间的粘附，具有低缺陷性，作为硬掩模操作，并且用作相移层，其与有机ARC （18），以减少不期望的反射。

3. 发明申请

WO2006096232A3 METHOD OF MAKING AN INTEGRATED CIRCUIT BY MODIFYING A DESIGN LAYOUT 审中-公开
标题翻译：通过修改设计布局制作集成电路的方法
公开(公告)号：WO2006096232A3
公开(公告)日：2009-04-16
申请号：PCT/US2006000612
申请日：2006-01-10
申请人： FREESCALE SEMICONDUCTOR INC , LUCAS KEVIN D , BOONE ROBERT E , PATTERSON KYLE W
发明人： LUCAS KEVIN D , BOONE ROBERT E , PATTERSON KYLE W
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F7/70941
摘要： An original layout of an integrated circuit is modified using optical proximity correction (OPC) to obtain a second layout. During OPC, a sensitivity to flare for each feature is conveniently identified (2). To map (4) the flare, the amplitude of intensity is mapped over a field of exposure, which is typically a rectangle-shaped area corresponding to an exposure of a stepper. The field of exposure is divided into regions in which a region is characterized as having substantially the same amplitude throughout. For each feature a decision (14) is made whether to make a further correction or not. If correction is desired, the amount of correction is based in part on the region in which the feature is located and the sensitivity of the feature. This same approach is applicable to other properties than flare that vary based on the location within the field of exposure.
摘要翻译：使用光学邻近校正（OPC）修改集成电路的原始布局以获得第二布局。在OPC期间，方便地识别每个特征对闪光的敏感度（2）。为了映射（4）耀斑，强度的幅度被映射在曝光场上，该场通常是对应于步进曝光的矩形区域。曝光领域被划分为其中区域被表征为具有基本上相同振幅的区域。对于每个特征，做出是否进一步校正的决定（14）。如果需要校正，校正量部分地基于特征所在的区域和特征的灵敏度。这种相同的方法适用于根据暴露领域内的位置而变化的其他特性。

4. 发明申请

WO2005013320A3 A SEMICONDUCTOR DEVICE HAVING AN ORGANIC ANTI-REFLECTIVE COATING (ARC) AND METHOD THEREFOR 审中-公开
标题翻译：具有有机抗反射涂层（ARC）的半导体器件及其方法
公开(公告)号：WO2005013320A3
公开(公告)日：2005-04-07
申请号：PCT/US2004022434
申请日：2004-07-13
申请人： FREESCALE SEMICONDUCTOR INC , REBER DOUGLAS M , HALL MARK D , JUNKER KURT H , PATTERSON KYLE W , STEPHENS TAB ALLEN , THEISS EDWARD K , SRIKANTESWARA DAKSHINA-MURTHY , WRIGHT MARILYN IRENE
发明人： REBER DOUGLAS M , HALL MARK D , JUNKER KURT H , PATTERSON KYLE W , STEPHENS TAB ALLEN , THEISS EDWARD K , SRIKANTESWARA DAKSHINA-MURTHY , WRIGHT MARILYN IRENE
IPC分类号： H01L21/027 , H01L21/033 , H01L21/28 , H01L21/3213 , H01L21/332
CPC分类号： H01L21/02164 , H01L21/02274 , H01L21/0276 , H01L21/0332 , H01L21/0338 , H01L21/28035 , H01L21/28123 , H01L21/31612 , H01L21/32139 , H01L29/6659 , H01L29/7833 , Y10S438/902 , Y10S438/952
摘要： In a making a semiconductor device (10), a patterning stack above a conductive material (16) that is to be etched has a patterned photoresist layer (22) that is used to pattern an underlying a tetraethyl-ortho-silicate (TEOS) layer (20). The TEOS layer (20) is deposited at a lower temperature than is conventional. The low temperature TEOS layer (20) is over an organic anti-reflective coating (ARC) (18) that is over the conductive layer (16). The low temperature TEOS layer (20) provides adhesion between the organic ARC (18) and the photoresist (22), has low defectivity, operates as a hard mask, and serves as a phase shift layer that helps, in combination with the organic ARC (18), to reduce undesired reflection.
摘要翻译：在制造半导体器件（10）中，要被蚀刻的导电材料（16）上方的图案化叠层具有图案化的光致抗蚀剂层（22），其用于图案化下面的四乙基原硅酸盐（TEOS）层（20）。 TEOS层（20）在比常规温度更低的温度下沉积。低温TEOS层（20）位于导电层（16）上方的有机抗反射涂层（ARC）（18）之上。低温TEOS层（20）提供了有机ARC（18）和光致抗蚀剂（22）之间的粘附力，具有低缺陷率，作为硬掩模起作用并且用作相移层，其有助于与有机ARC （18），以减少不希望的反射。

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