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1. 发明申请

WO2008109221A1 TRENCH FORMATION IN A SEMICONDUCTOR MATERIAL 审中-公开
标题翻译：半导体材料中的形成
公开(公告)号：WO2008109221A1
公开(公告)日：2008-09-12
申请号：PCT/US2008/053133
申请日：2008-02-06
申请人： FREESCALE SEMICONDUCTOR INC. , HALL, Mark D. , ABELN, Glenn C. , GRANT, John M.
发明人： HALL, Mark D. , ABELN, Glenn C. , GRANT, John M.
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76283 , H01L21/84 , H01L27/11 , H01L27/1104 , H01L29/66757 , H01L29/78621
摘要： A semiconductor device (10) is formed on a semiconductor layer (16). A gate dielectric layer (18) is formed over the semiconductor layer. A layer of gate material (20) is formed over the gate dielectric layer. The layer of gate material is patterned to form a gate structure (20). Using the gate structure as a mask, an implant (24) into the semiconductor layer is performed. To form a first patterned gate structure (20) and a trench (42) in the semiconductor layer (16) surrounding a first portion (28) and a second portion (30) of the semiconductor layer and the gate, an etch through the gate structure (20) and the semiconductor layer (16) is performed. The trench (42) is filled with insulating material (46).
摘要翻译：半导体器件（10）形成在半导体层（16）上。栅电介质层（18）形成在半导体层上。栅极材料层（20）形成在栅极介质层上。图案化栅极材料层以形成栅极结构（20）。使用栅极结构作为掩模，进行到半导体层中的注入（24）。为了在半导体层（16）中形成围绕半导体层和栅极的第一部分（28）和第二部分（30）的第一图案化栅极结构（20）和沟槽（42），通过栅极结构（20）和半导体层（16）。沟槽（42）填充有绝缘材料（46）。

2. 发明申请

WO2006112964A3 METHOD OF FORMING TRENCH ISOLATION IN A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：WO2006112964A3
公开(公告)日：2006-10-26
申请号：PCT/US2006/008253
申请日：2006-03-08
申请人： FREESCALE SEMICONDUCTOR, INC. , VAN GOMPEL, Toni D. , ABELN, Glenn C. , BECKAGE, Peter J. , GILLILAND, Kyle T. , JAHANBANI, Mohamad , BURNETT, James D.
发明人： VAN GOMPEL, Toni D. , ABELN, Glenn C. , BECKAGE, Peter J. , GILLILAND, Kyle T. , JAHANBANI, Mohamad , BURNETT, James D.
IPC分类号： H01L21/76
摘要： Divots (35, 36) may particularly be a problem for isolation trenches (22, 24) that are shallow. These divots (35, 36) may have a negative impact on the performance of the integrated circuit (49). Densification heating may be used to reduce the size and/or depth of these divots (35, 36) during manufacturing. For example, densification heating may be done at a temperature of at least 1100 degrees Celsius for at least 10 minutes after filling the isolation trenches (22, 24) with dielectric material (30). This densification heating may improve the variation in threshold voltages of transistors (e.g. 48) on an integrated circuit (49), particularly SOI (silicon on insulator) devices. SRAM cells (50) in particular may benefit from this densification heating.

3. 发明申请

WO2008063741A2 TWO-PORT SRAM HAVING IMPROVED WRITE OPERATION 审中-公开
标题翻译：双端口SRAM具有改进的写操作
公开(公告)号：WO2008063741A2
公开(公告)日：2008-05-29
申请号：PCT/US2007/079709
申请日：2007-09-27
申请人： FREESCALE SEMICONDUCTOR INC. , ABELN, Glenn C. , BURNETT, James D. , HERR, Lawrence N. , HIGMAN, Jack M.
发明人： ABELN, Glenn C. , BURNETT, James D. , HERR, Lawrence N. , HIGMAN, Jack M.
IPC分类号： G11C11/00 , G11C5/14 , G11C8/00
CPC分类号： G11C8/16 , G11C11/419
摘要： A two-port SRAM memory cell (20) includes a pair of cross-coupled inverters (40) coupled to storage nodes. An access transistor (54) is coupled between each storage node (SN, SNB) and a write bit line (WBL0) and controlled by a write word line (WWL0). The write word line is also coupled to a power supply terminal of the pair of cross-coupled inverters (40). During a write operation, the write word line is asserted. A voltage at the power supply terminal of the cross-coupled inverters (40) follows the write word line voltage, thus making it easier for the stored logic state at the storage nodes to change, if necessary. At the end of the write operation, the write word line is de-asserted, allowing the cross-coupled inverters (40) to function normally and hold the logic state of the storage node (SN). Coupling the power supply node of the cross-coupled inverters allows faster write operations without harming cell stability.
摘要翻译：双端口SRAM存储单元（20）包括耦合到存储节点的一对交叉耦合的反相器（40）。存取晶体管（54）耦合在每个存储节点（SN，SNB）和写入位线（WBL0）之间并由写入字线（WWL0）控制。写字线还耦合到该对交叉耦合逆变器（40）的电源端子。在写入操作期间，写入字线被断言。交叉耦合逆变器（40）的电源端子处的电压跟随写入字线电压，因此如果需要，存储节点处的存储的逻辑状态变得更容易。在写操作结束时，写字线被取消断言，允许交叉耦合的反相器（40）正常工作并保持存储节点（SN）的逻辑状态。耦合交叉耦合逆变器的电源节点允许更快的写入操作，而不会损害电池稳定性。

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