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1. 发明申请

WO2010014441A2 HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS 审中-公开
标题翻译：高信号电平符合输入/输出电路
公开(公告)号：WO2010014441A2
公开(公告)日：2010-02-04
申请号：PCT/US2009/050973
申请日：2009-07-17
申请人： QUALCOMM INCORPORATED , SHANKAR, Vijay , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
发明人： SHANKAR, Vijay , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
IPC分类号： G06F13/38
CPC分类号： G06F13/4072 , G06F13/385
摘要： A signal interface circuit has a signal path for communicatively coupling host circuitry to peripheral circuitry of multiple peripherals. Communication signals in the signal path are of a peripheral signal level. The signal path has electronic components adapted for use in communicating signals between the host circuitry and the peripheral circuitry. The electronic components in the signal path have reliability limits less than the peripheral signal level. The configuration of the electronic components in the signal path allow communication of signals at the peripheral signal level.
摘要翻译：信号接口电路具有用于将主机电路通信地耦合到多个外围设备的外围电路的信号路径。信号路径中的通信信号是外围信号电平。信号路径具有适用于在主机电路和外围电路之间传送信号的电子组件。信号路径中的电子元件的可靠性限制小于外围信号电平。信号路径中的电子组件的配置允许以外围信号级别传送信号。

2. 发明申请

WO2009018285A2 VOLTAGE TOLERANT FLOATING N-WELL CIRCUIT 审中-公开
标题翻译：容许电压的浮动N阱电路
公开(公告)号：WO2009018285A2
公开(公告)日：2009-02-05
申请号：PCT/US2008071494
申请日：2008-07-29
申请人： QUALCOMM INC , GUPTA ABHEEK , SRINIVAS VAISHNAV , MOHAN VIVEK
发明人： GUPTA ABHEEK , SRINIVAS VAISHNAV , MOHAN VIVEK
IPC分类号： H03K19/003
CPC分类号： H03K19/018592 , H03K19/00384
摘要： Methods and apparatuses are presented for voltage tolerant floating N-well circuits. An apparatus for mitigating leakage currents caused by input voltages is presented which includes a first transistor having a source coupled to a positive voltage supply, and a drain coupled to a floating node. The apparatus may further include a controllable pull down path coupled to a negative voltage supply and the first transistor, wherein the controllable pull-down path is configured to turn on the first transistor and pull-up the floating node during a first state. The apparatus may further include a second transistor having a source coupled to a gate of the first transistor, and drain coupled to the floating node, wherein the second transistor is configured to place the floating node at a floating potential during a second state.
摘要翻译：提出了用于耐压浮置N阱电路的方法和装置。提出了一种用于减轻由输入电压引起的泄漏电流的设备，其包括具有耦合到正电压源的源极和耦合到浮动节点的漏极的第一晶体管。该装置还可以包括耦合到负电压电源和第一晶体管的可控下拉路径，其中可控下拉路径被配置为在第一状态期间导通第一晶体管并上拉浮动节点。该装置还可以包括第二晶体管，该第二晶体管具有耦合到第一晶体管的栅极的源极和耦合到浮动节点的漏极，其中第二晶体管被配置为在第二状态期间将浮置节点置于浮动电位。

3. 发明申请

WO2010014441A3 HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS 审中-公开
标题翻译：高信号电平输入/输出电路
公开(公告)号：WO2010014441A3
公开(公告)日：2010-04-01
申请号：PCT/US2009050973
申请日：2009-07-17
申请人： QUALCOMM INC , SHANKAR VIJAY , GUPTA ABHEEK , SRINIVAS VAISHNAV , MOHAN VIVEK
发明人： SHANKAR VIJAY , GUPTA ABHEEK , SRINIVAS VAISHNAV , MOHAN VIVEK
IPC分类号： G06F13/38
CPC分类号： G06F13/4072 , G06F13/385
摘要： A signal interface circuit has a signal path for communicatively coupling host circuitry to peripheral circuitry of multiple peripherals. Communication signals in the signal path are of a peripheral signal level. The signal path has electronic components adapted for use in communicating signals between the host circuitry and the peripheral circuitry. The electronic components in the signal path have reliability limits less than the peripheral signal level. The configuration of the electronic components in the signal path allow communication of signals at the peripheral signal level.
摘要翻译：信号接口电路具有用于将主机电路通信耦合到多个外围设备的外围电路的信号路径。信号路径中的通信信号为周边信号电平。信号路径具有适于在主机电路和外围电路之间传送信号的电子部件。信号路径中的电子元件具有小于外围信号电平的可靠性限制。信号路径中的电子部件的配置允许以外围信号电平进行信号的通信。

4. 发明申请

WO2010014477A1 HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS 审中-公开
标题翻译：高信号电平输入/输出电路
公开(公告)号：WO2010014477A1
公开(公告)日：2010-02-04
申请号：PCT/US2009/051419
申请日：2009-07-22
申请人： QUALCOMM INCORPORATED , SHANKAR, Vijay , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
发明人： SHANKAR, Vijay , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K19/00315 , H03K19/018507 , H03K19/018585
摘要： An interface input (fig.2: 220) has an input circuit (fig.10: 221) adapted to receive input signal levels (padloc) higher than a maximum signal level that a host circuitry's electronic components can reliably handle. The input circuit (fig.10: 221) shifts the level of the input signal (padloc) to a desired signal level. A keeper circuit (keeper: pull up 1011; pull down 1012) is coupled to the input circuit and maintains trigger levels of the shifted signals (lvl_dn_int) consistent with the input signal level (padloc).
摘要翻译：接口输入（图2：220）具有适于接收高于主机电路的电子部件可以可靠地处理的最大信号电平的输入信号电平（padloc）的输入电路（图10：221）。输入电路（图10：221）将输入信号（padloc）的电平移动到期望的信号电平。保持器电路（保持器：上拉1011;下拉1012）耦合到输入电路，并保持与输入信号电平（padloc）一致的移位信号（lvl_dn_int）的触发电平。

5. 发明申请

WO2010014443A1 HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS 审中-公开
标题翻译：高信号电平输入/输出电路
公开(公告)号：WO2010014443A1
公开(公告)日：2010-02-04
申请号：PCT/US2009/050978
申请日：2009-07-17
申请人： QUALCOMM INCORPORATED , SHANKAR, Vijay , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
发明人： SHANKAR, Vijay , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
IPC分类号： G01R19/165 , H03K19/0185 , H03K19/003
CPC分类号： H03K19/018507 , G01R19/16519 , G01R19/16552 , H03K19/00315
摘要： (213) has an input circui (M5,M6,M7) adapted to accept signals of multiple signal levels for detecting a specific level. The signal levels include a first signal level and a larger second signal level. Electronic components of the input circuit have reliability levels less than the second signal level. A latch circuit (710) is coupled to the input circuit (M5,M6,M7) for latching a signal consistent with a detected level of an accepted signal.
摘要翻译：（213）具有适于接收用于检测特定电平的多个信号电平的信号的输入电路（M5，M6，M7）。信号电平包括第一信号电平和较大的第二信号电平。输入电路的电子元件具有小于第二信号电平的可靠性水平。锁存电路（710）耦合到输入电路（M5，M6，M7），用于锁存与所接收信号的检测电平一致的信号。

6. 发明申请

WO2010014474A3 HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS 审中-公开
公开(公告)号：WO2010014474A3
公开(公告)日：2010-02-04
申请号：PCT/US2009/051406
申请日：2009-07-22
申请人： QUALCOMM INCORPORATED , SHANKAR, Vijay , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
发明人： SHANKAR, Vijay , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
IPC分类号： H03K19/0185 , H03K19/003 , H03K19/0175
摘要： A signal driver (211) for an interface circuit has a first stage level shifter (311) to accept input signals and output signals at a first signal level. The signal driver (211) also has a second stage level shifter (312) coupled to the first stage level shifter (311) to output signals at a second signal level. Electronic components of the first (311) and second (312) stage level shifter have reliability limits less than the second signal level. The first and second stage configurations of the first stage level shifter (311) and the second stage level shifter (312) prevents exposing the electronic components to terminal to terminal signal levels higher than the reliability limits when processing signals for output at the second signal level.

7. 发明申请

WO2010014474A2 HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS 审中-公开
标题翻译：高信号电平输入/输出电路
公开(公告)号：WO2010014474A2
公开(公告)日：2010-02-04
申请号：PCT/US2009051406
申请日：2009-07-22
申请人： QUALCOMM INC , SHANKAR VIJAY , GUPTA ABHEEK , SRINIVAS VAISHNAV , MOHAN VIVEK
发明人： SHANKAR VIJAY , GUPTA ABHEEK , SRINIVAS VAISHNAV , MOHAN VIVEK
IPC分类号： H03K19/0185 , H03K19/003 , H03K19/0175
CPC分类号： H03K19/00315 , H03K19/017581 , H03K19/018507
摘要： A signal driver for an interface circuit has a first stage level shifter to accept input signals and output signals at a first signal level. The signal driver also has a second stage level shifter coupled to the first stage level shifter to output signals at a second signal level. Electronic components of the first and second stage level shifter have reliability limits less than the second signal level. The first and second stage configurations of the first stage level shifter and the second stage level shifter prevents exposing the electronic components to terminal to terminal signal levels higher than the reliability limits when processing signals for output at the second signal level.
摘要翻译：用于接口电路的信号驱动器具有第一级电平移位器，以接收输入信号并以第一信号电平输出信号。信号驱动器还具有耦合到第一级电平移位器的第二级电平移位器，以在第二信号电平输出信号。第一级和第二级电平移位器的电子部件具有小于第二信号电平的可靠性限制。第一级电平移位器和第二级电平转换器的第一和第二级配置防止当处理用于在第二信号电平输出的信号时将电子部件暴露于高于可靠性限制的端对端信号电平。

8. 发明申请

WO2010014473A1 HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS 审中-公开
标题翻译：高信号电平输入/输出电路
公开(公告)号：WO2010014473A1
公开(公告)日：2010-02-04
申请号：PCT/US2009/051395
申请日：2009-07-22
申请人： QUALCOMM INCORPORATED , SHANKAR, Vijay , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
发明人： SHANKAR, Vijay , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
IPC分类号： H03K19/00
CPC分类号： H03K19/00315 , H03K19/018507
摘要： A level shifter (410) has at least two pull down circuits (Ml, M2, 412 or M3, M4, 422). The circuit is made of electronic components with reliability limits less than a maximum signal level output by the level shifter. The level shifter also has a timing circuit (411, 421) coupled to the pull down circuits (Ml, M2, 412 or M3, M4, 422). The timing circuit (411, 421) controls a time of application of an input signal (input, input_n), to the pull down circuits preventing a terminal to terminal signal level experienced by the electronic components exceeding the reliability limits.
摘要翻译：电平移位器（410）具有至少两个下拉电路（M1，M2，412或M3，M4,422）。该电路由可靠性限制小于电平转换器输出的最大信号电平的电子元件组成。电平移位器还具有耦合到下拉电路（M1，M2，412或M3，M4,422）的定时电路（411,421）。定时电路（411,421）控制向下拉电路施加输入信号（input，input_n）的时间，从而防止电子部件超过可靠性限制的终端信号电平。

9. 发明申请

WO2009018285A3 VOLTAGE TOLERANT FLOATING N-WELL CIRCUIT 审中-公开
公开(公告)号：WO2009018285A3
公开(公告)日：2009-02-05
申请号：PCT/US2008/071494
申请日：2008-07-29
申请人： QUALCOMM INCORPORATED , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
发明人： GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
IPC分类号： H03K19/003
摘要： Methods and apparatuses are presented for voltage tolerant floating N-well circuits. An apparatus for mitigating leakage currents caused by input voltages is presented which includes a first transistor having a source coupled to a positive voltage supply, and a drain coupled to a floating node. The apparatus may further include a controllable pull down path coupled to a negative voltage supply and the first transistor, wherein the controllable pull-down path is configured to turn on the first transistor and pull-up the floating node during a first state. The apparatus may further include a second transistor having a source coupled to a gate of the first transistor, and drain coupled to the floating node, wherein the second transistor is configured to place the floating node at a floating potential during a second state.

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