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1. 发明申请

WO2010014441A3 HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS 审中-公开
标题翻译：高信号电平输入/输出电路
公开(公告)号：WO2010014441A3
公开(公告)日：2010-04-01
申请号：PCT/US2009050973
申请日：2009-07-17
申请人： QUALCOMM INC , SHANKAR VIJAY , GUPTA ABHEEK , SRINIVAS VAISHNAV , MOHAN VIVEK
发明人： SHANKAR VIJAY , GUPTA ABHEEK , SRINIVAS VAISHNAV , MOHAN VIVEK
IPC分类号： G06F13/38
CPC分类号： G06F13/4072 , G06F13/385
摘要： A signal interface circuit has a signal path for communicatively coupling host circuitry to peripheral circuitry of multiple peripherals. Communication signals in the signal path are of a peripheral signal level. The signal path has electronic components adapted for use in communicating signals between the host circuitry and the peripheral circuitry. The electronic components in the signal path have reliability limits less than the peripheral signal level. The configuration of the electronic components in the signal path allow communication of signals at the peripheral signal level.
摘要翻译：信号接口电路具有用于将主机电路通信耦合到多个外围设备的外围电路的信号路径。信号路径中的通信信号为周边信号电平。信号路径具有适于在主机电路和外围电路之间传送信号的电子部件。信号路径中的电子元件具有小于外围信号电平的可靠性限制。信号路径中的电子部件的配置允许以外围信号电平进行信号的通信。

2. 发明申请

WO2010014477A1 HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS 审中-公开
标题翻译：高信号电平输入/输出电路
公开(公告)号：WO2010014477A1
公开(公告)日：2010-02-04
申请号：PCT/US2009/051419
申请日：2009-07-22
申请人： QUALCOMM INCORPORATED , SHANKAR, Vijay , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
发明人： SHANKAR, Vijay , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K19/00315 , H03K19/018507 , H03K19/018585
摘要： An interface input (fig.2: 220) has an input circuit (fig.10: 221) adapted to receive input signal levels (padloc) higher than a maximum signal level that a host circuitry's electronic components can reliably handle. The input circuit (fig.10: 221) shifts the level of the input signal (padloc) to a desired signal level. A keeper circuit (keeper: pull up 1011; pull down 1012) is coupled to the input circuit and maintains trigger levels of the shifted signals (lvl_dn_int) consistent with the input signal level (padloc).
摘要翻译：接口输入（图2：220）具有适于接收高于主机电路的电子部件可以可靠地处理的最大信号电平的输入信号电平（padloc）的输入电路（图10：221）。输入电路（图10：221）将输入信号（padloc）的电平移动到期望的信号电平。保持器电路（保持器：上拉1011;下拉1012）耦合到输入电路，并保持与输入信号电平（padloc）一致的移位信号（lvl_dn_int）的触发电平。

3. 发明申请

WO2010014443A1 HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS 审中-公开
标题翻译：高信号电平输入/输出电路
公开(公告)号：WO2010014443A1
公开(公告)日：2010-02-04
申请号：PCT/US2009/050978
申请日：2009-07-17
申请人： QUALCOMM INCORPORATED , SHANKAR, Vijay , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
发明人： SHANKAR, Vijay , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
IPC分类号： G01R19/165 , H03K19/0185 , H03K19/003
CPC分类号： H03K19/018507 , G01R19/16519 , G01R19/16552 , H03K19/00315
摘要： (213) has an input circui (M5,M6,M7) adapted to accept signals of multiple signal levels for detecting a specific level. The signal levels include a first signal level and a larger second signal level. Electronic components of the input circuit have reliability levels less than the second signal level. A latch circuit (710) is coupled to the input circuit (M5,M6,M7) for latching a signal consistent with a detected level of an accepted signal.
摘要翻译：（213）具有适于接收用于检测特定电平的多个信号电平的信号的输入电路（M5，M6，M7）。信号电平包括第一信号电平和较大的第二信号电平。输入电路的电子元件具有小于第二信号电平的可靠性水平。锁存电路（710）耦合到输入电路（M5，M6，M7），用于锁存与所接收信号的检测电平一致的信号。

4. 发明申请

WO2007059443A2 CLOCK SIGNAL GENERATION TECHNIQUES FOR MEMORIES THAT DO NOT GENERATE A STROBE 审中-公开
标题翻译：不产生STROBE的记忆的时钟信号发生技术
公开(公告)号：WO2007059443A2
公开(公告)日：2007-05-24
申请号：PCT/US2006/060797
申请日：2006-11-10
申请人： QUALCOMM INCORPORATED , SRINIVAS, Vaishnav , KAPOOR, Sanat , MADDALI, Srinivas , MOHAN, Vivek
发明人： SRINIVAS, Vaishnav , KAPOOR, Sanat , MADDALI, Srinivas , MOHAN, Vivek
IPC分类号： G06F13/16 , G11C7/10
CPC分类号： G11C7/1051
摘要： This disclosure describes a clock circuit for a memory controller. The described circuit uses a processor clock signal to generate an input clock signal for use during write operations to the memory, or to generate a feedback clock signal for use during read operations from the memory. The circuit is particularly applicable to mobile wireless devices that include memories that do not generate a strobe. The clock circuit may comprise a driver in series with a resistor element that generates an input clock signal for input to a memory, and a resistor-capacitor (RC) filter in series with a receiver that generates a feedback clock signal for output from the memory, wherein an input to the RC filter is tapped between the driver and the resistor element.
摘要翻译：本公开描述了用于存储器控制器的时钟电路。所描述的电路使用处理器时钟信号来产生用于在对存储器的写入操作期间使用的输入时钟信号，或者产生用于在来自存储器的读取操作期间使用的反馈时钟信号。该电路特别适用于包括不产生频闪的存储器的移动无线设备。时钟电路可以包括与电阻器元件串联的驱动器，该电阻器产生用于输入到存储器的输入时钟信号，以及与产生用于从存储器输出的反馈时钟信号的接收器串联的电阻器 - 电容器（RC）滤波器其中在所述驱动器和所述电阻器元件之间分接所述RC滤波器的输入。

5. 发明申请

WO2005107073A1 BREAK BEFORE MAKE PREDRIVER AND LEVEL-SHIFTER 审中-公开
标题翻译：在做预处理和水平切换之前
公开(公告)号：WO2005107073A1
公开(公告)日：2005-11-10
申请号：PCT/US2005/012479
申请日：2005-04-12
申请人： QUALCOMM INCORPORATED , SRINIVAS, Vaishnav , MOHAN, Vivek
发明人： SRINIVAS, Vaishnav , MOHAN, Vivek
IPC分类号： H03K19/00
CPC分类号： H03K19/0013 , H03K3/356113 , H03K17/08122
摘要： A break-before-make predriver for disabling a PFET of an output driver before enabling an NFET, and vice versa. The predriver includes an input inverter, two cross-coupled inverters, and output buffers. The predriver provides enhanced break-before-make action through sizing the NFETs larger than the PFETs in the predriver's cross-coupled inverters. The input inverter, the cross-coupled inverters and the first and second output buffers are sized with respect to each other such that substantially equal break before make action is provided on both rising and falling edges. The predriver also includes level-shifting capabilities through a different voltage supply at the PFETs of the cross-coupled inverter. The predriver also includes two data output nodes for connection to the two inputs of an output driver. The predriver provides for tristate action by disabling the signal from the predriver output nodes.
摘要翻译：用于在启用NFET之前禁用输出驱动器的PFET的前置制造预驱动器，反之亦然。预驱动器包括输入反相器，两个交叉耦合的反相器和输出缓冲器。预驱动器通过将大于预驱动器交叉耦合逆变器中的PFET的NFET尺寸进行调整，从而提供增强的“先行后制”动作。输入反相器，交叉耦合反相器和第一和第二输出缓冲器相对于彼此大小，使得在上升沿和下降沿两者之间提供在作用之前基本相等的断开。预驱动器还包括通过交叉耦合逆变器的PFET处的不同电压源的电平转换能力。预驱动器还包括用于连接到输出驱动器的两个输入的两个数据输出节点。预驱动器通过禁用来自预驱动输出节点的信号来提供三态动作。

6. 发明申请

WO2010062834A1 LOW VOLTAGE DIFFERENTIAL SIGNALING DRIVER WITH PROGRAMMABLE ON-CHIP RESISTOR TERMINATION 审中-公开
标题翻译：具有可编程片上电阻终止的低电压差分信号驱动器
公开(公告)号：WO2010062834A1
公开(公告)日：2010-06-03
申请号：PCT/US2009/065314
申请日：2009-11-20
申请人： QUALCOMM INCORPORATED , DIXIT, Abhay S. , SRINIVAS, Vaishnav
发明人： DIXIT, Abhay S. , SRINIVAS, Vaishnav
IPC分类号： H03F3/45 , H04L25/02
CPC分类号： H03F3/45946 , H03F3/45179 , H03F3/45475 , H03F2200/78 , H03F2203/45424 , H03F2203/45434 , H03F2203/45641 , H03F2203/45642 , H03F2203/45646 , H03F2203/45681 , H03F2203/45682 , H03F2203/45686 , H03F2203/45696 , H03F2203/45702 , H03F2203/45726 , H04L25/0272
摘要： A low voltage differential signaling driver is disclosed and may include a current steering output circuit having a first driver output and a second driver output. The low voltage differential signaling driver may also include a programmable on-chip resistor.
摘要翻译：公开了一种低电压差分信号驱动器，并且可以包括具有第一驱动器输出和第二驱动器输出的电流转向输出电路。低电压差分信号驱动器还可以包括可编程片上电阻器。

7. 发明申请

WO2010014441A2 HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS 审中-公开
标题翻译：高信号电平符合输入/输出电路
公开(公告)号：WO2010014441A2
公开(公告)日：2010-02-04
申请号：PCT/US2009/050973
申请日：2009-07-17
申请人： QUALCOMM INCORPORATED , SHANKAR, Vijay , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
发明人： SHANKAR, Vijay , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
IPC分类号： G06F13/38
CPC分类号： G06F13/4072 , G06F13/385
摘要： A signal interface circuit has a signal path for communicatively coupling host circuitry to peripheral circuitry of multiple peripherals. Communication signals in the signal path are of a peripheral signal level. The signal path has electronic components adapted for use in communicating signals between the host circuitry and the peripheral circuitry. The electronic components in the signal path have reliability limits less than the peripheral signal level. The configuration of the electronic components in the signal path allow communication of signals at the peripheral signal level.
摘要翻译：信号接口电路具有用于将主机电路通信地耦合到多个外围设备的外围电路的信号路径。信号路径中的通信信号是外围信号电平。信号路径具有适用于在主机电路和外围电路之间传送信号的电子组件。信号路径中的电子元件的可靠性限制小于外围信号电平。信号路径中的电子组件的配置允许以外围信号级别传送信号。

8. 发明申请

WO2009018285A2 VOLTAGE TOLERANT FLOATING N-WELL CIRCUIT 审中-公开
标题翻译：容许电压的浮动N阱电路
公开(公告)号：WO2009018285A2
公开(公告)日：2009-02-05
申请号：PCT/US2008071494
申请日：2008-07-29
申请人： QUALCOMM INC , GUPTA ABHEEK , SRINIVAS VAISHNAV , MOHAN VIVEK
发明人： GUPTA ABHEEK , SRINIVAS VAISHNAV , MOHAN VIVEK
IPC分类号： H03K19/003
CPC分类号： H03K19/018592 , H03K19/00384
摘要： Methods and apparatuses are presented for voltage tolerant floating N-well circuits. An apparatus for mitigating leakage currents caused by input voltages is presented which includes a first transistor having a source coupled to a positive voltage supply, and a drain coupled to a floating node. The apparatus may further include a controllable pull down path coupled to a negative voltage supply and the first transistor, wherein the controllable pull-down path is configured to turn on the first transistor and pull-up the floating node during a first state. The apparatus may further include a second transistor having a source coupled to a gate of the first transistor, and drain coupled to the floating node, wherein the second transistor is configured to place the floating node at a floating potential during a second state.
摘要翻译：提出了用于耐压浮置N阱电路的方法和装置。提出了一种用于减轻由输入电压引起的泄漏电流的设备，其包括具有耦合到正电压源的源极和耦合到浮动节点的漏极的第一晶体管。该装置还可以包括耦合到负电压电源和第一晶体管的可控下拉路径，其中可控下拉路径被配置为在第一状态期间导通第一晶体管并上拉浮动节点。该装置还可以包括第二晶体管，该第二晶体管具有耦合到第一晶体管的栅极的源极和耦合到浮动节点的漏极，其中第二晶体管被配置为在第二状态期间将浮置节点置于浮动电位。

9. 发明申请

WO2007059443A3 CLOCK SIGNAL GENERATION TECHNIQUES FOR MEMORIES THAT DO NOT GENERATE A STROBE 审中-公开
标题翻译：不产生频闪的记忆的时钟信号产生技术
公开(公告)号：WO2007059443A3
公开(公告)日：2007-07-26
申请号：PCT/US2006060797
申请日：2006-11-10
申请人： QUALCOMM INC , SRINIVAS VAISHNAV , KAPOOR SANAT , MADDALI SRINIVAS , MOHAN VIVEK
发明人： SRINIVAS VAISHNAV , KAPOOR SANAT , MADDALI SRINIVAS , MOHAN VIVEK
IPC分类号： G06F13/16 , G11C7/10
CPC分类号： G11C7/1051
摘要： This disclosure describes a clock circuit for a memory controller. The described circuit uses a processor clock signal to generate an input clock signal for use during write operations to the memory, or to generate a feedback clock signal for use during read operations from the memory. The circuit is particularly applicable to mobile wireless devices that include memories that do not generate a strobe. The clock circuit may comprise a driver in series with a resistor element that generates an input clock signal for input to a memory, and a resistor-capacitor (RC) filter in series with a receiver that generates a feedback clock signal for output from the memory, wherein an input to the RC filter is tapped between the driver and the resistor element.
摘要翻译：本公开描述了用于存储器控制器的时钟电路。所描述的电路使用处理器时钟信号来产生输入时钟信号以在对存储器的写入操作期间使用，或者产生反馈时钟信号以在从存储器读取操作期间使用。该电路特别适用于包括不产生频闪的存储器的移动无线设备。时钟电路可以包括与产生用于输入到存储器的输入时钟信号的电阻器元件串联的驱动器和与接收器串联的电阻器 - 电容器（RC）滤波器，所述接收器产生用于从存储器输出的反馈时钟信号其中，在所述驱动器和所述电阻器元件之间分接到所述RC滤波器的输入。

10. 发明申请

WO2010014474A3 HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS 审中-公开
公开(公告)号：WO2010014474A3
公开(公告)日：2010-02-04
申请号：PCT/US2009/051406
申请日：2009-07-22
申请人： QUALCOMM INCORPORATED , SHANKAR, Vijay , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
发明人： SHANKAR, Vijay , GUPTA, Abheek , SRINIVAS, Vaishnav , MOHAN, Vivek
IPC分类号： H03K19/0185 , H03K19/003 , H03K19/0175
摘要： A signal driver (211) for an interface circuit has a first stage level shifter (311) to accept input signals and output signals at a first signal level. The signal driver (211) also has a second stage level shifter (312) coupled to the first stage level shifter (311) to output signals at a second signal level. Electronic components of the first (311) and second (312) stage level shifter have reliability limits less than the second signal level. The first and second stage configurations of the first stage level shifter (311) and the second stage level shifter (312) prevents exposing the electronic components to terminal to terminal signal levels higher than the reliability limits when processing signals for output at the second signal level.

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