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1. 发明申请

WO2008109341A3 OPTIMIZED POWER SUPPLY FOR AN ELECTRONIC SYSTEM 审中-公开
标题翻译：电子系统的优化电源
公开(公告)号：WO2008109341A3
公开(公告)日：2008-12-24
申请号：PCT/US2008055294
申请日：2008-02-28
申请人： RAMBUS INC , ZERBE JARED LEVAN , KIM JAEHA , FRANS YOHAN U , NGUYEN HUY M
发明人： ZERBE JARED LEVAN , KIM JAEHA , FRANS YOHAN U , NGUYEN HUY M
IPC分类号： G05F1/46 , H01L21/8238
CPC分类号： G05F1/10 , G06F1/26 , Y10T307/406 , Y10T307/50
摘要： A method of adjusting a voltage supply to an electronic device coupled to a wired communication link in accordance with a performance metric associated with the wired communication link. A voltage adjust signal is generated based on the performance metric. The voltage adjustment signal is then used for updating the voltage supply to the electronic device.
摘要翻译：一种根据与有线通信链路相关联的性能度量调整耦合到有线通信链路的电子设备的电压供应的方法。基于性能度量生成电压调节信号。电压调整信号然后用于更新电子设备的电压供应。

2. 发明申请

WO2008076700A3 INTERFACE WITH VARIABLE DATA RATE 审中-公开
标题翻译：具有可变数据速率的接口
公开(公告)号：WO2008076700A3
公开(公告)日：2008-12-11
申请号：PCT/US2007087027
申请日：2007-12-10
申请人： RAMBUS INC , FRANS YOHAN U , LEE HAE-CHANG , LEIBOWITZ BRIAN S , LI SIMON , NGUYEN NHAT M
发明人： FRANS YOHAN U , LEE HAE-CHANG , LEIBOWITZ BRIAN S , LI SIMON , NGUYEN NHAT M
IPC分类号： H04L1/00 , G01R29/26 , H04B17/00 , H04L1/20 , H04L1/24 , H04L5/14
CPC分类号： G06F13/4286 , G06F13/385 , G06F13/4068 , H04L1/0002 , H04L1/0015 , H04L1/203 , H04L1/205 , H04L1/243 , H04L5/1446 , H04L25/0262 , H04L25/0292 , Y02B60/31 , Y02D50/10
摘要： A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined errorrate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.
摘要翻译：装置包括耦合到节点的发射器，其中节点将耦合到有线链路。发射机具有多种操作模式，包括校准模式，其中根据与有线链路相对应的电压容限以预定误差率确定有线链路上的通信数据速率范围。通信数据速率的范围包括最大数据速率，其可以是初始数据速率的非整数倍。

3. 发明申请

WO2005034355A2 CLOCK-DATA RECOVERY (“CDR”) CIRCUIT, APPARATUS AND METHOD FOR VARIABLE FREQUENCY DATA 审中-公开
标题翻译：时钟数据恢复（“CDR”）电路，可变频率数据的装置和方法
公开(公告)号：WO2005034355A2
公开(公告)日：2005-04-14
申请号：PCT/US2004/031784
申请日：2004-09-28
申请人： RAMBUS INCORPORATED , KIM, Dennis , WEI, Jason , FRANS, Yohan , BYSTROM, Todd , NGUYEN, Nhat , DONNELLY, Kevin
发明人： KIM, Dennis , WEI, Jason , FRANS, Yohan , BYSTROM, Todd , NGUYEN, Nhat , DONNELLY, Kevin
IPC分类号： H03L
CPC分类号： H03L7/0814 , H03L7/091 , H04L7/0331
摘要： A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the clock circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the clock circuit includes the Stall logic, the indicator and the counter. In a fifth embodiment of the present invention, the clock circuit includes an Averaging circuit to output a phase adjust signal responsive to the averaging of a first and second adjust signals for a predetermined period of time.
摘要翻译：诸如CDR电路的电路包括采样器，以在本发明的实施例中接收具有响应于时钟信号的可变数据比特率的数据信号。时钟电路耦合到采样器并且响应于可选择的更新速率和可选择的相位调整步长而产生时钟信号。在本发明的第二实施例中，时钟电路包括耦合到第一，第二和第三级的失调逻辑，并且能够响应于第一和第二级输出信号保持相位调整信号。在本发明的第三实施例中，指示器检测可变数据比特率，并且计数器为调整信号提供可选择的相位调整步长。在本发明的第四实施例中，时钟电路包括失速逻辑，指示器和计数器。在本发明的第五实施例中，时钟电路包括平均电路，用于响应于在预定时间段内的第一和第二调整信号的平均来输出相位调整信号。

4. 发明申请

WO2012154507A1 SUPPORTING CALIBRATION FOR SUB-RATE OPERATION IN CLOCKED MEMORY SYSTEMS 审中-公开
标题翻译：支持在时钟记忆系统中进行子频率运算的校准
公开(公告)号：WO2012154507A1
公开(公告)日：2012-11-15
申请号：PCT/US2012/036370
申请日：2012-05-03
申请人： RAMBUS INC. , BANSAL, Akash , FRANS, Yohan U. , KASAMSETTY, Kishore V. , BYSTROM, Todd , LI, Simon , VAIDYANATH, Arun
发明人： BANSAL, Akash , FRANS, Yohan U. , KASAMSETTY, Kishore V. , BYSTROM, Todd , LI, Simon , VAIDYANATH, Arun
IPC分类号： G11C7/00 , G06F1/04
CPC分类号： G11C7/22 , G06F1/10 , G11C7/222 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., 1/2, 1/4 or 1/8 of the full-rate frequency). The system then uses this sub-rate calibration state when the clocked memory system is operating at the sub-rate frequency. This calculation of the sub-rate state calibration states eliminates the need to perform an additional time-consuming calibration operation for each sub-rate.
摘要翻译：公开的实施例涉及一种时钟存储器系统，其以全速率频率执行校准操作，以确定指定时钟信号与时钟控制的存储器系统中相应的数据信号之间的延迟的全速率校准状态。接下来，时钟存储器系统使用全速率校准状态来计算子速率校准状态，其与子速率频率（例如，全速率的1/2速率，1/4或1/8）相关联频率）。当时钟存储器系统以子速率频率工作时，系统然后使用该子速率校准状态。子速率状态校准状态的这种计算消除了对每个子速率执行附加耗时的校准操作的需要。

5. 发明申请

WO2008144152A1 INJECTION-LOCKED CLOCK MULTIPLIER 审中-公开
标题翻译：注射锁定时间累加器
公开(公告)号：WO2008144152A1
公开(公告)日：2008-11-27
申请号：PCT/US2008/061118
申请日：2008-04-22
申请人： RAMBUS INC. , LEIBOWITZ, Brian S. , FRANS, Yohan , LEE, Hae-chang , KIM, Jaeha
发明人： FRANS, Yohan , LEE, Hae-chang , KIM, Jaeha
IPC分类号： H03L7/24
CPC分类号： H03L7/24 , H03L7/083 , H03L7/099 , H03L7/10
摘要： Embodiments of a clock circuit are described. This clock circuit includes an oscillator, which includes a resonance circuit having a resonance frequency, that outputs a first clock signal having a first frequency. Furthermore, a digital controller is coupled to the oscillator. This digital controller modifies the resonance frequency of the oscillator during a first mode of operation of the clock circuit, and the modifying is ceased during a second mode of operation of the clock circuit. In addition, an injection circuit is coupled to the oscillator. This injection circuit provides a second clock signal having a second frequency to the oscillator. Note that the second clock signal injection locks a phase and/or the first frequency of the first clock signal. Also note that a ratio of the first frequency to the second frequency is greater than or equal to one.
摘要翻译：描述时钟电路的实施例。该时钟电路包括振荡器，其包括具有谐振频率的谐振电路，该谐振电路输出具有第一频率的第一时钟信号。此外，数字控制器耦合到振荡器。该数字控制器在时钟电路的第一操作模式期间修改振荡器的谐振频率，并且在时钟电路的第二操作模式期间中止修改。此外，注入电路耦合到振荡器。该注入电路向振荡器提供具有第二频率的第二时钟信号。注意，第二时钟信号注入锁定第一时钟信号的相位和/或第一频率。还要注意，第一频率与第二频率的比率大于或等于1。

6. 发明申请

WO2009065050A1 DATA-DEPENDET VOLTAGE REGULATOR 审中-公开
标题翻译：数据依赖电压调节器
公开(公告)号：WO2009065050A1
公开(公告)日：2009-05-22
申请号：PCT/US2008/083655
申请日：2008-11-14
申请人： RAMBUS INC. , FRANS, Yohan , LEIBOWITZ, Brian , NGUYEN, Nhat
发明人： FRANS, Yohan , LEIBOWITZ, Brian , NGUYEN, Nhat
IPC分类号： G05F1/56
CPC分类号： G05F1/56
摘要： A data-dependent voltage regulator maintains a relatively stable voltage in the presence of data-induced supply-current fluctuations. The regulator includes a feedback path through a replica load that provides a data-dependent replica voltage for fast feedback. The regulator reduces data-dependent supply- voltage fluctuations on a regulated voltage without resorting to a compensation current.
摘要翻译：数据相关的电压调节器在数据引起的电源电流波动的情况下保持相对稳定的电压。调节器包括通过复制负载的反馈路径，其提供用于快速反馈的数据相关副本电压。调节器可减少稳压电压下的数据相关电源电压波动，而无需使用补偿电流。

7. 发明申请

WO2008109341A2 OPTIMIZED POWER SUPPLY FOR AN ELECTRONIC SYSTEM 审中-公开
标题翻译：电子系统优化电源
公开(公告)号：WO2008109341A2
公开(公告)日：2008-09-12
申请号：PCT/US2008/055294
申请日：2008-02-28
申请人： RAMBUS INC. , ZERBE, Jared, Levan , KIM, Jaeha , FRANS, Yohan, U. , NGUYEN, Huy, M.
发明人： ZERBE, Jared, Levan , KIM, Jaeha , FRANS, Yohan, U. , NGUYEN, Huy, M.
IPC分类号： G05F1/46 , H01L21/8238
CPC分类号： G05F1/10 , G06F1/26 , Y10T307/406 , Y10T307/50
摘要： A method of adjusting a voltage supply to an electronic device coupled to a wired communication link in accordance with a performance metric associated with the wired communication link. A voltage adjust signal is generated based on the performance metric. The voltage adjustment signal is then used for updating the voltage supply to the electronic device.
摘要翻译：根据与有线通信链路相关联的性能度量来调整与有线通信链路耦合的电子设备的电压供应的方法。基于性能度量产生电压调整信号。然后，电压调整信号用于更新对电子设备的电压供应。

8. 发明申请

WO2013009418A1 HIGH-SPEED LOW-POWER STACKED TRANSCEIVER 审中-公开
标题翻译：高速低功耗堆叠收发器
公开(公告)号：WO2013009418A1
公开(公告)日：2013-01-17
申请号：PCT/US2012/041864
申请日：2012-06-11
申请人： RAMBUS INC. , NGUYEN, Huy , KAVIANI, Kambiz , FRANS, Yohan
发明人： NGUYEN, Huy , KAVIANI, Kambiz , FRANS, Yohan
IPC分类号： H03K19/0175 , H03K19/0944 , H03K19/0948
CPC分类号： H03K19/017509 , H04L25/0274 , H04L25/0282 , H04L25/0294 , H04L25/03146 , H04L25/03878
摘要： A transceiver includes a transmitter and receiver that form a series current path between two power- supply nodes. Powering both the transmitter and receiver with the same supply current saves power. The transmitter functions as a resistive load for the receiver, and thus performs useful work with power that would otherwise be dissipated as waste heat.
摘要翻译：收发器包括在两个电源节点之间形成串联电流路径的发射器和接收器。以相同的电源电流为发射器和接收器供电节省电力。发射器作为接收器的电阻负载起作用，因此可以用功率进行有用的工作，否则这些功率将作为废热消散。

9. 发明申请

WO2012082274A2 TIMING-DRIFT CALIBRATION 审中-公开
标题翻译：时序移位校准
公开(公告)号：WO2012082274A2
公开(公告)日：2012-06-21
申请号：PCT/US2011/060213
申请日：2011-11-10
申请人： RAMBUS INC. , FRANS, Yohan, U. , ELLIS, Wayne, F. , BANSAL, Akash
发明人： FRANS, Yohan, U. , ELLIS, Wayne, F. , BANSAL, Akash
IPC分类号： G11C7/22 , G11C7/10
CPC分类号： G11C29/50012 , G01R23/02 , G01R23/15 , G01R35/005 , G06F1/08 , G06F1/12 , G06F11/1604 , G06F13/1689 , G11C7/04 , G11C7/22 , G11C7/222 , G11C7/225 , G11C8/18 , G11C29/023 , G11C29/028 , G11C2207/2254 , H03L1/02
摘要： The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device.
摘要翻译：所公开的实施例涉及支持定时漂移校准的存储器系统的组件。在具体实施例中，该存储器系统包含存储器件（或多个器件），其包括可产生频率的时钟分配电路和振荡器电路，其中频率变化表示时钟分配电路的定时漂移。存储装置还包括被配置为测量振荡器电路的频率的测量电路。此外，存储器系统包含存储器控制器，该存储器控制器可向存储器件发送请求以触发存储器件以测量振荡器电路的频率。存储器控制器还被配置为从存储器件接收测量的频率，并使用测量的频率来确定存储器件中的定时漂移。

10. 发明申请

WO2011156041A1 INTEGRATED CIRCUIT DEVICE TIMING CALIBRATION 审中-公开
标题翻译：集成电路设备时序校准
公开(公告)号：WO2011156041A1
公开(公告)日：2011-12-15
申请号：PCT/US2011/029144
申请日：2011-03-21
申请人： RAMBUS INC. , OH, Kyung Suk , FRANS, Yohan U. , BANSAL, Akash , LEIBOWITZ, Brian S.
发明人： OH, Kyung Suk , FRANS, Yohan U. , BANSAL, Akash , LEIBOWITZ, Brian S.
IPC分类号： G11C7/22 , H04L7/00
CPC分类号： H03K5/135 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254 , H04L7/0008 , H04L7/02 , H04L7/033 , H04L7/10
摘要： Techniques for performing timing calibration for an integrated circuit (IC) device are described. During operation, a first integrated circuit device transmits a first calibration pattern having differently delayed rising edge transitions with respect to a timing reference. The first integrated circuit device additionally transmits a second calibration pattern having differently delayed falling edge transitions with respect to the timing reference. Next, the first integrated circuit generates a timing offset for transmitting data from the first integrated circuit device. This timing offset is derived from information received from a second integrated circuit device sampling the first calibration pattern and the second calibration pattern.
摘要翻译：描述了用于执行集成电路（IC）装置的定时校准的技术。在操作期间，第一集成电路装置相对于定时参考发送具有不同延迟的上升沿转变的第一校准模式。第一集成电路装置另外发送相对于定时参考具有不同延迟的下降沿跃迁的第二校准模式。接下来，第一集成电路产生用于从第一集成电路器件发送数据的定时偏移。该定时偏移是从对第一校准图案和第二校准图案采样的第二集成电路装置接收的信息导出的。

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