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1. 发明申请

WO2008011053A1 MEMORY CELL SYSTEM WITH CHARGE TRAP 审中-公开
标题翻译：带有电荷捕获的存储单元系统
公开(公告)号：WO2008011053A1
公开(公告)日：2008-01-24
申请号：PCT/US2007/016250
申请日：2007-07-17
申请人： SPANSION LLC , ADVANCED MICRO DEVICES, INC. , DING, Meng , JOSHI, Amol, Ramesh , XUE, Lei , ORIMOTO, Takashi , CHANG, Kuo-Tung
发明人： DING, Meng , JOSHI, Amol, Ramesh , XUE, Lei , ORIMOTO, Takashi , CHANG, Kuo-Tung
IPC分类号： H01L21/28 , H01L29/51 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11563 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/513 , H01L29/792
摘要： A memory cell system (1000) is provided including forming a first insulator layer (212) over a semiconductor substrate (204), forming a charge trap layer (216) over the first insulator layer (212), forming an intermediate layer (218) over the charge trap layer (216), and forming a second insulator layer (220) with the intermediate layer (218).
摘要翻译：提供一种存储单元系统（1000），包括在半导体衬底（204）上形成第一绝缘体层（212），在第一绝缘体层（212）上形成电荷陷阱层（216），形成中间层（218）在所述电荷陷阱层（216）之上，以及与所述中间层（218）形成第二绝缘体层（220）。

2. 发明申请

WO2007114955A3 METHODS FOR ERASING AND PROGRAMMING MEMORY DEVICES 审中-公开
公开(公告)号：WO2007114955A3
公开(公告)日：2007-10-11
申请号：PCT/US2007/008683
申请日：2007-04-05
申请人： SPANSION LLC , DING, Meng , LIU, Zhizheng , ZHENG, Wei
发明人： DING, Meng , LIU, Zhizheng , ZHENG, Wei
IPC分类号： G11C16/04 , G11C11/56
摘要： A dual-bit memory device includes a first charge storage region (164A) spaced apart from a second charge storage region (164B) by an isolation region (170). Techniques for erasing a memory can be provided in which electrons can be injected into the charge storage regions (164 A, B) to erase the charge storage regions (164 A, B). Other techniques for programming a memory can be provided in which holes can be injected into at least one of the charge storage regions (164 A, B) to program the charge storage regions (164 A, B).

3. 发明申请

WO2007114955A2 METHODS FOR ERASING AND PROGRAMMING MEMORY DEVICES 审中-公开
标题翻译：擦除和编程存储器件的方法
公开(公告)号：WO2007114955A2
公开(公告)日：2007-10-11
申请号：PCT/US2007008683
申请日：2007-04-05
申请人： SPANSION LLC , DING MENG , LIU ZHIZHENG , ZHENG WEI
发明人： DING MENG , LIU ZHIZHENG , ZHENG WEI
CPC分类号： H01L29/7923 , G11C16/0475 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/7887
摘要： A dual-bit memory device includes a first charge storage region (164A) spaced apart from a second charge storage region (164B) by an isolation region (170). Techniques for erasing a memory can be provided in which electrons can be injected into the charge storage regions (164 A, B) to erase the charge storage regions (164 A, B). Other techniques for programming a memory can be provided in which holes can be injected into at least one of the charge storage regions (164 A, B) to program the charge storage regions (164 A, B).
摘要翻译：双位存储器件包括通过隔离区域（170）与第二电荷存储区域（164B）间隔开的第一电荷存储区域（164A）。可以提供用于擦除存储器的技术，其中电子可以被注入到电荷存储区域（164A，B）中以擦除电荷存储区域（164A，B）。可以提供用于编程存储器的其它技术，其中可以将空穴注入到电荷存储区域（164A，B）中的至少一个中，以对电荷存储区域（164A，B）进行编程。

4. 发明申请

WO2008016487A2 MEMORY CELL SYSTEM WITH MULTIPLE NITRIDE LAYERS 审中-公开
标题翻译：具有多层氮化物层的存储单元系统
公开(公告)号：WO2008016487A2
公开(公告)日：2008-02-07
申请号：PCT/US2007/016251
申请日：2007-07-17
申请人： SPANSION LLC , ADVANCED MICRO DEVICES, INC. , XUE, Lei , SUGINO, Rinji , SUH, YouSeok , SHIRAIWA, Hidehiko , DING, Meng , FANG, Shenqing , JEON, Joong
发明人： XUE, Lei , SUGINO, Rinji , SUH, YouSeok , SHIRAIWA, Hidehiko , DING, Meng , FANG, Shenqing , JEON, Joong
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/513
摘要： A memory cell system (1200) is provided including forming a first insulator layer (512) over a semiconductor substrate (504), forming a charge trap layer (514) over the first insulator layer (512), forming a second insulator layer (520) over the charge trap layer (514), forming a top blocking intermediate layer (516) over the second insulator layer (520), and forming a contact layer (506) over the top blocking intermediate layer (516).
摘要翻译：提供了存储单元系统（1200），包括在半导体衬底（504）上形成第一绝缘体层（512），在第一绝缘体层（512）上形成电荷陷阱层（514），形成第二绝缘体层）在所述电荷陷阱层（514）上方，在所述第二绝缘体层（520）上形成顶部阻挡中间层（516），以及在所述顶部阻挡中间层（516）上方形成接触层（506）。

5. 发明申请

WO2008140661A1 FLASH MEMORY CELL WITH A GATE HAVING A FLARING SHAPE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：具有具有变形形状的门的闪存单元及其制造方法
公开(公告)号：WO2008140661A1
公开(公告)日：2008-11-20
申请号：PCT/US2008/004667
申请日：2008-04-10
申请人： SPANSION LLC , DING, Meng , SUH, YouSeok , FANG, Shenqing , CHANG, Kuo-Tung
发明人： DING, Meng , SUH, YouSeok , FANG, Shenqing , CHANG, Kuo-Tung
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L23/528 , H01L27/02
CPC分类号： H01L29/788 , H01L21/28273 , H01L21/28282 , H01L21/762 , H01L21/76224 , H01L27/0207 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42324 , H01L29/4234 , H01L29/792
摘要： An embodiment of the present invention is directed to a method of forming a memory cell. The method includes etching a trench in a substrate and filling the trench with an oxide to form a shallow trench isolation (STI) region. A portion of an actxve region of the substrate that comes in contact with the STI region forms a bitline-STI edge. The method further includes forming a gate structure over the active region of the substrate and over the STI region. The gate structure has a first width substantially over the center of the active region of the substrate and a second width substantially over the bitline-STI edge, and the second width is greater than the first width. An electrical current (330) flows along the bitlines (310) that are covered by wordlines (320).
摘要翻译：本发明的实施例涉及一种形成存储单元的方法。该方法包括蚀刻衬底中的沟槽并用氧化物填充沟槽以形成浅沟槽隔离（STI）区域。与STI区域接触的衬底的actxve区域的一部分形成位线STI边缘。该方法还包括在衬底的有源区上方和STI区上方形成栅极结构。栅极结构具有基本上在衬底的有源区域的中心上方的第一宽度和基本上位于STI边缘的第二宽度，并且第二宽度大于第一宽度。电流（330）沿着由字线（320）覆盖的位线（310）流动。

6. 发明申请

WO2007117617A1 FLASH MEMORY PROGRAMMING AND VERIFICATION WITH REDUCED LEAKAGE CURRENT 审中-公开
标题翻译：具有降低漏电流的闪存存储器编程和验证
公开(公告)号：WO2007117617A1
公开(公告)日：2007-10-18
申请号：PCT/US2007/008606
申请日：2007-04-05
申请人： SPANSION LLC , MELIK-MARTIROSIAN, Ashot , RUNNION, Ed , RANDOLPH, Mark , DING, Meng
发明人： MELIK-MARTIROSIAN, Ashot , RUNNION, Ed , RANDOLPH, Mark , DING, Meng
IPC分类号： G11C16/04 , G11C16/10 , G11C16/34
CPC分类号： G11C16/0475 , G11C16/12 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459
摘要： A flash memory system (300) configured in accordance with an example embodiment of the invention employs a virtual ground array architecture (302). During programming operations, target memory cells (406) are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells (406). A positive source bias voltage may also be applied to target memory cells (506) during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.
摘要翻译：根据本发明的示例性实施例配置的闪存系统（300）采用虚拟接地阵列架构（302）。在编程操作期间，目标存储器单元（406）被偏置为正的源偏置电压，以减少或消除另外可能通过目标存储单元（406）传导的漏电流。在验证操作（程序验证，软程序验证，擦除验证）期间，也可以将正源偏置电压施加到目标存储器单元（506），以减少或消除可能在验证操作中引入错误的泄漏电流。

7. 发明申请

WO2006128073A1 READ-ONLY MEMORY ARRAY WITH DIELECTRIC BREAKDOWN PROGRAMMABILITY 审中-公开
标题翻译：只读存储器阵列具有介质断开可编程性
公开(公告)号：WO2006128073A1
公开(公告)日：2006-11-30
申请号：PCT/US2006/020634
申请日：2006-05-25
申请人： SPANSION LLC , DING, Meng , LIU, Zhizheng , HE, Yi , RANDOLPH, Mark, W.
发明人： DING, Meng , LIU, Zhizheng , HE, Yi , RANDOLPH, Mark, W.
IPC分类号： H01L27/102 , G11C17/14 , H01L27/115
CPC分类号： G11C17/16 , G11C2213/72 , H01L27/1021 , H01L27/112 , H01L27/11206 , H01L27/118
摘要： According to one exemplary embodiment, a programmable ROM array includes at least one bitline (204c) situated in a substrate. The programmable ROM array further includes at least one wordline (202b) situated over the at least one bitline (204c). The programmable ROM array further includes a memory cell (206) situated at an intersection of the at least one bitline (204c) and the at least one wordline (202b), where the memory cell (206) includes a dielectric region (216) situated between the at least one bitline (204c) and the at least one wordline (202b). A programming operation causes the memory cell (206) to change from a first logic state to a second logic state by causing the dielectric region (216) to break down. The programming operation causes the memory cell (206) to operate as a diode. A resistance of the memory cell (206) can be measured in a read operation to determine if the memory cell (206) has the first or second logic state.
摘要翻译：根据一个示例性实施例，可编程ROM阵列包括位于衬底中的至少一个位线（204c）。可编程ROM阵列还包括位于所述至少一个位线（204c）上方的至少一个字线（202b）。可编程ROM阵列还包括位于至少一个位线（204c）和至少一个字线（202b）的相交处的存储单元（206），其中存储单元（206）包括位于在所述至少一个位线（204c）和所述至少一个字线（202b）之间。通过使介电区域（216）分解，编程操作使存储单元（206）从第一逻辑状态改变到第二逻辑状态。编程操作使存储单元（206）作为二极管工作。可以在读取操作中测量存储器单元（206）的电阻，以确定存储单元（206）是否具有第一或第二逻辑状态。

8. 发明申请

WO2008016487A3 MEMORY CELL SYSTEM WITH MULTIPLE NITRIDE LAYERS 审中-公开
标题翻译：具有多个氮化物层的存储器单元系统
公开(公告)号：WO2008016487A3
公开(公告)日：2008-06-05
申请号：PCT/US2007016251
申请日：2007-07-17
申请人： SPANSION LLC , ADVANCED MICRO DEVICES INC , XUE LEI , SUGINO RINJI , SUH YOUSEOK , SHIRAIWA HIDEHIKO , DING MENG , FANG SHENQING , JEON JOONG
发明人： XUE LEI , SUGINO RINJI , SUH YOUSEOK , SHIRAIWA HIDEHIKO , DING MENG , FANG SHENQING , JEON JOONG
IPC分类号： H01L21/28 , H01L21/8246 , H01L27/115 , H01L29/423 , H01L29/51 , H01L29/792
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/513
摘要： A memory cell system (1200) is provided including forming a first insulator layer (512) over a semiconductor substrate (504), forming a charge trap layer (514) over the first insulator layer (512), forming a second insulator layer (520) over the charge trap layer (514), forming a top blocking intermediate layer (516) over the second insulator layer (520), and forming a contact layer (506) over the top blocking intermediate layer (516).
摘要翻译：提供了一种存储器单元系统（1200），包括在半导体衬底（504）上方形成第一绝缘体层（512），在第一绝缘体层（512）上方形成电荷捕获层（514），形成第二绝缘体层（520 ）在电荷陷阱层（514）上方，在第二绝缘体层（520）上方形成顶部阻挡中间层（516），并且在顶部阻挡中间层（516）上方形成接触层（506）。

9. 发明申请

WO2007117610A3 METHODS FOR ERASING MEMORY DEVICES AND MULTI-LEVEL PROGRAMMING MEMORY DEVICE 审中-公开
标题翻译：擦除存储器设备和多级编程存储器设备的方法
公开(公告)号：WO2007117610A3
公开(公告)日：2007-12-06
申请号：PCT/US2007008596
申请日：2007-04-05
申请人： SPANSION LLC , ZHENG WEI , DING MENG
发明人： ZHENG WEI , DING MENG
IPC分类号： G11C11/56
CPC分类号： G11C16/14 , G11C16/0458 , G11C16/0475 , H01L29/7887 , H01L29/7923
摘要： A memory (150) includes a first charge storage region (164A) spaced apart from a second charge storage region (164B) by an isolation region (170). Techniques for erasing a memory (150) are provided in which electrons are Fowler-Nordheim (FN) tunneled out of at least one of the charge storage regions (164 A, B) into a substrate (154) to erase the at least one charge storage region of the memory (150). Other techniques are provided for programming a single charge storage region at multiple different levels or states.
摘要翻译：存储器（150）包括通过隔离区（170）与第二电荷存储区（164B）隔开的第一电荷存储区（164A）。提供了用于擦除存储器（150）的技术，其中电子是Fowler-Nordheim（FN）从至少一个电荷存储区域（164A，B）隧穿到衬底（154）中以擦除至少一个电荷存储器（150）的存储区域。提供其他技术用于在多个不同级别或状态下编程单个电荷存储区域。

10. 发明申请

WO2007117610A2 METHODS FOR ERASING MEMORY DEVICES AND MULTI-LEVEL PROGRAMMING MEMORY DEVICE 审中-公开
标题翻译：用于擦除存储器件和多级编程存储器件的方法
公开(公告)号：WO2007117610A2
公开(公告)日：2007-10-18
申请号：PCT/US2007/008596
申请日：2007-04-05
申请人： SPANSION LLC , ZHENG, Wei , DING, Meng
发明人： ZHENG, Wei , DING, Meng
CPC分类号： G11C16/14 , G11C16/0458 , G11C16/0475 , H01L29/7887 , H01L29/7923
摘要： A memory (150) includes a first charge storage region (164A) spaced apart from a second charge storage region (164B) by an isolation region (170). Techniques for erasing a memory (150) are provided in which electrons are Fowler-Nordheim (FN) tunneled out of at least one of the charge storage regions (164 A, B) into a substrate (154) to erase the at least one charge storage region of the memory (150). Other techniques are provided for programming a single charge storage region at multiple different levels or states.
摘要翻译：存储器（150）包括通过隔离区域（170）与第二电荷存储区域（164B）间隔开的第一电荷存储区域（164A）。提供了用于擦除存储器（150）的技术，其中电子是Fowler-Nordheim（FN）从电荷存储区域（164A，B）中的至少一个隧道传输到衬底（154）中以擦除至少一个电荷存储器（150）的存储区域。提供了用于在多个不同级别或状态下编程单个电荷存储区域的其它技术。

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