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1. 发明申请

WO2006065531A3 CMOS NVM BITCELL AND INTEGRATED CIRCUIT 审中-公开
公开(公告)号：WO2006065531A3
公开(公告)日：2006-06-22
申请号：PCT/US2005/043219
申请日：2005-11-30
申请人： FREESCALE SEMICONDUCTOR, INC. , PARRIS, Patrice , DE FRESART, Edouard, D. , DE SOUZA, Richard, D. , MORRISON, Jennifer, H.
发明人： PARRIS, Patrice , DE FRESART, Edouard, D. , DE SOUZA, Richard, D. , MORRISON, Jennifer, H.
IPC分类号： H01L21/336
摘要： A non-volatile memory bitcell structure (10) is disclosed that includes a dual capacitor structure. A first metal-insulator-metal (MIM) capacitor (14) having a first capacitance value includes a first top plate (20), a first bottom plate (16), and a first dielectric (18) disposed in-between the first top plate and the first bottom plate. A second metal-insulator-metal (MIM) capacitor (22) having a second capacitance value includes a second top plate (26), a second bottom plate (16), and a second dielectric (24) disposed in-between the second top plate and the second bottom plate. An element (16) of the first MIM capacitor (14) is electrically coupled in common with an element (16) of the second MIM capacitor (22). In addition, the first capacitance value is greater than the second capacitance value.

2. 发明申请

WO2006121564A3 HIGH VOLTAGE FIELD EFFECT DEVICE AND METHOD 审中-公开
标题翻译：高电压场效应器件及方法
公开(公告)号：WO2006121564A3
公开(公告)日：2007-05-03
申请号：PCT/US2006013737
申请日：2006-04-07
申请人： FREESCALE SEMICONDUCTOR INC , DE FRESART EDOUARD D , DE SOUZA RICHARD J , LIN XIN , MORRISON JENNIFER H , PARRIS PATRICE M , ZITOUNI MOANISS
发明人： DE FRESART EDOUARD D , DE SOUZA RICHARD J , LIN XIN , MORRISON JENNIFER H , PARRIS PATRICE M , ZITOUNI MOANISS
IPC分类号： H01L29/76 , H01L21/336 , H01L21/8234 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7835 , H01L29/0847 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92') serially located between the channel (90) and the source (70, 70') or drain (76, 76'). A buried region (96, 96') of the same conductivity type as the drift space (92, 92') and the source (70, 70') or drain (76, 76') is provided below the drift space (92, 92'), separated therefrom in depth by a narrow gap (94, 94') and ohmically coupled to the source (70, 70') or drain (76, 76'). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94'). As the S-D voltage (Vo) and current (109, Io) increase, this difference (Vt) induces high field conduction between the drift space (92, 92') and the buried region (96, 96') and diverts part (112, It) of the S-D current (109, Io) through the buried region (96, 96') and away from the near surface portions of the drift space (92, 92') where breakdown generally occurs. Thus, BVdss is increased
摘要翻译：为具有增加的源 - 漏击穿电压（BVdss）的MOSFET（50,99,199）提供了方法和装置。源极（S）（70）和漏极（D）（76）通过栅极（84）下面的沟道（90）和串联地位于沟道（90）之间的一个或多个载流子漂移空间（92,92'）间隔开）和源极（70,70'）或漏极（76,76'）。与漂移空间（92,92'）和源极（70,70'）或漏极（76,76'）相同的导电类型的掩埋区域（96,96'）设置在漂移空间（92,92'）的下方， 92'），通过狭窄的间隙（94,94'）深度地分离，并且与欧姆耦合到源极（70,70'）或漏极（76,76'）。通过漂移空间的电流（110）在该间隙（94,94'）上产生电位差（Vt）。随着SD电压（Vo）和电流（109，Io）的增加，该差值（Vt）引起漂移空间（92,92'）和掩埋区域（96,96'）之间的高场导通，并且转移部分，It）通过掩埋区域（96,96'）并远离漂移空间（92,92'）的通常发生击穿的漂移空间（92,92'）的近表面部分的SD电流（109，Io）。因此，BVdss增加

3. 发明申请

WO2007070050A1 POWER MOSFET AND METHOD OF MAKING THE SAME 审中-公开
标题翻译：功率MOSFET及其制造方法
公开(公告)号：WO2007070050A1
公开(公告)日：2007-06-21
申请号：PCT/US2005/045432
申请日：2005-12-14
申请人： FREESCALE SEMICONDUCTOR, INC. , DE FRESART, Edouard D. , FENG, Zhu-Qing , QIN, Ganming , WANG, Pei-Lin , WANG, Xiao-Ping , ZHOU, Hong-Wei
发明人： DE FRESART, Edouard D. , FENG, Zhu-Qing , QIN, Ganming , WANG, Pei-Lin , WANG, Xiao-Ping , ZHOU, Hong-Wei
IPC分类号： H01L29/78 , H01L29/08 , H01L29/423 , H01L21/336 , H01L29/49 , H01L29/45
CPC分类号： H01L29/7802 , H01L29/0847 , H01L29/0878 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66712
摘要： A MOS device (40, 70) comprising first and second N-type source regions (50), electrically in parallel, located in spaced-apart P- type body regions (46), separated by an N-type JFET region (56) at a first surface (45). Channel regions (47) underlying the gate (53) at the first surface (45), extend from the source regions (50) through portions (47) of the body regions (46) to the JFET region (56) which communicates via an N-epi region (44) with an underlying drain region (42). Ion implantation is used to tailor the doping density (86, 92) in the JFET region (56) so that the net active doping concentration (86, 92) in a central portion (X{θ) of the JFET region (56) decreases substantially linearly from the first surface (45) toward the underlying N epi region (44). A thickened gate dielectric layer region (72) may be provided on said control portion of the JFET region (56).
摘要翻译：一种由N型JFET区域（56）隔开的包括第一和第二N型源极区域（50）的MOS器件（40,70），该第一和第二N型源极区域电并联，位于间隔开的P-型体区域（46）在第一表面（45）处。在第一表面（45）处在栅极（53）下方的通道区域（47）从源极区域（50）延伸通过体区（46）的部分（47）延伸到JFET区域（56），JFET区域具有下面的漏极区域（42）的N外延区域（44）。使用离子注入来定制JFET区域（56）中的掺杂密度（86,92），使得JFET区域（56）的中心部分（X（λ））中的净有源掺杂浓度（86,92）减小从第一表面（45）到下面的N外延区域（44）基本线性地。可以在JFET区域（56）的所述控制部分上设置加厚的栅介质层区域（72）。

4. 发明申请

WO2006065531A2 CMOS NVM BITCELL AND INTEGRATED CIRCUIT 审中-公开
标题翻译： CMOS NVM BITCELL和集成电路
公开(公告)号：WO2006065531A2
公开(公告)日：2006-06-22
申请号：PCT/US2005043219
申请日：2005-11-30
申请人： FREESCALE SEMICONDUCTOR INC , PARRIS PATRICE , DE FRESART EDOUARD D , DE SOUZA RICHARD D , MORRISON JENNIFER H
发明人： PARRIS PATRICE , DE FRESART EDOUARD D , DE SOUZA RICHARD D , MORRISON JENNIFER H
IPC分类号： H01L21/336
CPC分类号： H01L27/101 , G11C16/02 , G11C16/0416 , H01L27/115 , H01L27/11517 , H01L27/11521
摘要： A non-volatile memory bitcell structure (10) is disclosed that includes a dual capacitor structure. A first metal-insulator-metal (MIM) capacitor (14) having a first capacitance value includes a first top plate (20), a first bottom plate (16), and a first dielectric (18) disposed in-between the first top plate and the first bottom plate. A second metal-insulator-metal (MIM) capacitor (22) having a second capacitance value includes a second top plate (26), a second bottom plate (16), and a second dielectric (24) disposed in-between the second top plate and the second bottom plate. An element (16) of the first MIM capacitor (14) is electrically coupled in common with an element (16) of the second MIM capacitor (22). In addition, the first capacitance value is greater than the second capacitance value.
摘要翻译：公开了一种包括双电容器结构的非易失性存储器位单元结构（10）。具有第一电容值的第一金属 - 绝缘体金属（MIM）电容器（14）包括第一顶板（20），第一底板（16）和设置在第一顶板板和第一底板。具有第二电容值的第二金属 - 绝缘体金属（MIM）电容器（22）包括第二顶板（26），第二底板（16）和设置在第二顶板板和第二底板。第一MIM电容器（14）的元件（16）与第二MIM电容器（22）的元件（16）共同地电耦合。此外，第一电容值大于第二电容值。

5. 发明申请

WO2006028793A1 METAL OXIDE SEMICONDUCTOR DEVICE INCLUDING A SHIELDING STRUCTURE FOR LOW GATE-DRAIN CAPACITANCE 审中-公开
标题翻译：金属氧化物半导体器件，包括用于低栅极电容的屏蔽结构
公开(公告)号：WO2006028793A1
公开(公告)日：2006-03-16
申请号：PCT/US2005/030772
申请日：2005-08-30
申请人： FREESCALE SEMICONDUCTOR, INC. , PARRIS, Patrice , DE FRESART, Edouard, D.
发明人： PARRIS, Patrice , DE FRESART, Edouard, D.
IPC分类号： H01L21/00 , H01L21/30 , H01L21/822 , H01L29/76 , H01L29/94
CPC分类号： H01L29/7802 , H01L29/0653 , H01L29/402 , H01L29/407 , H01L29/42368
摘要： A semiconductor MOSFET device (70, 100), and method of fabricating the device, including a shielding structure (86, 210) for decreasing the gate-drain capacitance (CGD) without simultaneously increasing the gate resistance or the total device ON-state resistance (RDSON). The shielding structure (86, 210) is formed between a drain region (76, 106) and an active gate electrode (88, 118) in the form of a separate dummy gate (87) or a trench (212) having a material (214) formed therein. The shielding structure (86, 210) forms a capacitance "shield" between the gate (88, 118) and drain region (76, 106). The MOSFET device (70, 100) further includes a semiconductor material (74, 104) defining therein a drain region (76, 106), at least one body region (78, 108) formed in the semiconductor material (74, 104), at least one source region (80, 110) formed in each body region (78, 108), and an active gate electrode (88, 118) formed over the semiconductor material (74, 104).
摘要翻译：一种半导体MOSFET器件（70,100）以及制造该器件的方法，包括用于降低栅极 - 漏极电容（CGD）而不同时增加栅极电阻或总器件导通电阻的屏蔽结构（86,210）（RDSON）。屏蔽结构（86,210）形成在漏极区域（76,106）和具有单独的虚拟栅极（87）形式的有源栅电极（88,118）或具有材料的沟槽（212） 214）。屏蔽结构（86,210）在栅极（88,118）和漏极区域（76,106）之间形成电容“屏蔽”。 MOSFET器件（70,100）还包括在其中限定漏极区域（76,106）的半导体材料（74,104），形成在半导体材料（74,104）中的至少一个体区（78,108）形成在每个主体区域（78,108）中的至少一个源极区域（80,110）以及形成在所述半导体材料（74,104）上方的有源栅电极（88,118）。

6. 发明申请

WO2015028838A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREFOR 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2015028838A1
公开(公告)日：2015-03-05
申请号：PCT/IB2013/002209
申请日：2013-08-27
申请人： FREESCALE SEMICONDUCTOR, INC. , STEFANOV, Evgueniy , DE FRESART, Edouard , DUPUY, Philippe
发明人： STEFANOV, Evgueniy , DE FRESART, Edouard , DUPUY, Philippe
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7811 , H01L27/088 , H01L29/0642 , H01L29/086 , H01L29/0865 , H01L29/0882 , H01L29/1095 , H01L29/404 , H01L29/407 , H01L29/4236 , H01L29/42376 , H01L29/66734 , H01L29/7813
摘要： A semiconductor device (100) comprises a first contact layer (102), a first drift layer (106) adjacent the first contact layer (102), a buried body layer (108) adjacent the first drift layer (106) and a second contact layer (112). A first vertical trench (114) and a second vertical trench (116) are provided, the first and second vertical trenches (114, 116, 118, 120) being spaced with respect to each other and extending from the second contact layer (112) to substantially beyond the buried body layer (108). A second drift layer (110) is also provided and sandwiched between the buried body layer (108) and the second contact layer (112).
摘要翻译：半导体器件（100）包括第一接触层（102），与第一接触层（102）相邻的第一漂移层（106），与第一漂移层（106）相邻的掩埋体层（108）层（112）。提供第一垂直沟槽（114）和第二垂直沟槽（116），所述第一和第二垂直沟槽（114,116,118,120）相对于彼此间隔开并且从所述第二接触层（112）延伸，基本上超过掩埋体层（108）。还提供第二漂移层（110）并夹在掩埋体层（108）和第二接触层（112）之间。

7. 发明申请

WO2007133280A3 SUPERJUNCTION POWER MOSFET 审中-公开
公开(公告)号：WO2007133280A3
公开(公告)日：2007-11-22
申请号：PCT/US2006/060826
申请日：2006-11-13
申请人： FREESCALE SEMICONDUCTOR INC. , DE FRESART, Edouard, D. , BAIRD, Robert, W. , QIN, Ganming
发明人： DE FRESART, Edouard, D. , BAIRD, Robert, W. , QIN, Ganming
IPC分类号： H01L29/80
摘要： Methods and apparatus are provided for TMOS devices (40), comprising multiple N-type source regions (50), electrically in parallel, located in multiple P-body regions (46) separated by N-type JFET regions (56) at a first surface. The gate (53) overlies the body channel regions (46) and the JFET region (56) lying between the body regions. The JFET region (56) communicates with an underlying drain region (42) via an N-epi region (44). Ion implantation and heat treatment are used to tailor the net active doping concentration N d in the JFET region (56) of length L acc and net active doping concentration N a in the P-body regions (46) of length L body so that a charge balance relationship (L body * N a ) = k 1 *(L acc * N d ) between P-body and JFET regions is satisfied, where k 1 is about 0.6 ≤ k 1 ≤ 1.4. The entire device (40) can be fabricated using planar technology and the charge balanced regions need not extend through the underlying N-epi region (44) to the drain (42).

8. 发明申请

WO2007133280A2 SUPERJUNCTION POWER MOSFET 审中-公开
标题翻译：超级功率MOSFET
公开(公告)号：WO2007133280A2
公开(公告)日：2007-11-22
申请号：PCT/US2006060826
申请日：2006-11-13
申请人： FREESCALE SEMICONDUCTOR INC , DE FRESART EDOUARD D , BAIRD ROBERT W , QIN GANMING
发明人： DE FRESART EDOUARD D , BAIRD ROBERT W , QIN GANMING
IPC分类号： H01L29/76
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0873 , H01L29/0878 , H01L29/1095 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/7809 , H01L29/7811
摘要： Methods and apparatus are provided for TMOS devices (40), comprising multiple N-type source regions (50), electrically in parallel, located in multiple P-body regions (46) separated by N-type JFET regions (56) at a first surface. The gate (53) overlies the body channel regions (46) and the JFET region (56) lying between the body regions. The JFET region (56) communicates with an underlying drain region (42) via an N-epi region (44). Ion implantation and heat treatment are used to tailor the net active doping concentration N d in the JFET region (56) of length L acc and net active doping concentration N a in the P-body regions (46) of length L body so that a charge balance relationship (L body * N a ) = k 1 *(L acc * N d ) between P-body and JFET regions is satisfied, where k 1 is about 0.6 = k 1 = 1.4. The entire device (40) can be fabricated using planar technology and the charge balanced regions need not extend through the underlying N-epi region (44) to the drain (42).
摘要翻译：提供了用于TMOS器件（40）的方法和装置，其包括多个并联的N型源极区（50），位于由N型JFET区域（56）分开的多个P体区域（46）中，第一表面。栅极（53）覆盖在身体区域（46）和位于身体区域之间的JFET区域（56）之间。 JFET区域（56）经由N-epi区域（44）与下面的漏极区域（42）连通。离子注入和热处理用于定制长度为L的JFET区域（56）中的净有源掺杂浓度N sub和净活性掺杂浓度N SUB 在长度为L本体的P体区域（46）中的一个，使得电荷平衡关系（L * N ]]>其中k≠1时，满足P体和JFET区域之间的距离（k）= k 1（N）约为0.6 = k 1 = 1.4。整个器件（40）可以使用平面技术制造，并且电荷平衡区域不需要延伸穿过下面的N外延区域（44）到漏极（42）。

9. 发明申请

WO2008024572A3 SUPERJUNCTION TRENCH DEVICE AND METHOD 审中-公开
标题翻译：超功能TRENCH装置和方法
公开(公告)号：WO2008024572A3
公开(公告)日：2008-04-17
申请号：PCT/US2007073837
申请日：2007-07-19
申请人： FREESCALE SEMICONDUCTOR INC , DE FRESART EDOUARD D , BAIRD ROBERT W
发明人： DE FRESART EDOUARD D , BAIRD ROBERT W
IPC分类号： H01L21/02 , H01L29/66
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/1054 , H01L29/165 , H01L29/42368 , H01L29/66734
摘要： Semiconductor structures and methods are provided for a semiconductor device (40) employing a superjunction structure (41) and overlying trench (91) with embedded control gate (48). The method comprises, forming (52-6, 52-9) interleaved first (70-1, 70-2, 70-3, 70-4, etc.) and second (74-1, 74-2, 74-3, etc.) spaced-apart regions of first (70) and second (74) semiconductor materials of different conductivity type and different mobilities so that, in a first embodiment, the second semiconductor material (74) has a higher mobility for the same carrier type than the first semiconductor material (70), and providing (52-14) an overlying third semiconductor material (82) in which a trench (90, 91) is formed with sidewalls (913) having thereon a fourth semiconductor material (87) that has a higher mobility than the third material (82), adapted to carry current (50) between source regions (86), through the fourth (87) semiconductor material in the trench (91) and the second semiconductor material (74) in the device drift space (42) to the drain (56). In a further embodiment, the first (70) and third (82) semiconductor materials are relaxed materials and the second (74) and fourth (87) semiconductor materials are strained semiconductor materials.
摘要翻译：为半导体器件（40）提供半导体结构和方法，该半导体器件采用超结构结构（41）和具有嵌入式控制栅极（48）的上覆沟槽（91）。该方法包括：首先（70-1,70-2,70-3,70-4等）和第二（74-1,74-2,74-3）交错形成（52-6,52-9）等等）具有不同导电类型和不同迁移率的第一（70）和第二（74）半导体材料的间隔开的区域，使得在第一实施例中，第二半导体材料（74）对于相同载体具有较高的迁移率并且提供（52-14）上覆第三半导体材料（82），其中沟槽（90,91）形成有其上具有第四半导体材料（87）的侧壁（913）其具有比第三材料（82）更高的迁移率，其适于在源极区域（86）之间通过沟槽（91）中的第四（87）半导体材料和第二半导体材料（74）中的载流子设备漂移空间（42）到排水管（56）。在另一实施例中，第一（70）和第三（82）半导体材料是松弛材料，第二（74）和第四（87）半导体材料是应变半导体材料。

10. 发明申请

WO2008024572A2 SUPERJUNCTION TRENCH DEVICE AND METHOD 审中-公开
标题翻译：超级接合装置和方法
公开(公告)号：WO2008024572A2
公开(公告)日：2008-02-28
申请号：PCT/US2007/073837
申请日：2007-07-19
申请人： FREESCALE SEMICONDUCTOR INC. , DE FRESART, Edouard D. , BAIRD, Robert W.
发明人： DE FRESART, Edouard D. , BAIRD, Robert W.
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/1054 , H01L29/165 , H01L29/42368 , H01L29/66734
摘要： Semiconductor structures and methods are provided for a semiconductor device (40) employing a superjunction structure (41) and overlying trench (91) with embedded control gate (48). The method comprises, forming (52-6, 52-9) interleaved first (70-1, 70-2, 70-3, 70-4, etc.) and second (74-1, 74-2, 74-3, etc.) spaced-apart regions of first (70) and second (74) semiconductor materials of different conductivity type and different mobilities so that, in a first embodiment, the second semiconductor material (74) has a higher mobility for the same carrier type than the first semiconductor material (70), and providing (52-14) an overlying third semiconductor material (82) in which a trench (90, 91) is formed with sidewalls (913) having thereon a fourth semiconductor material (87) that has a higher mobility than the third material (82), adapted to carry current (50) between source regions (86), through the fourth (87) semiconductor material in the trench (91) and the second semiconductor material (74) in the device drift space (42) to the drain (56). In a further embodiment, the first (70) and third (82) semiconductor materials are relaxed materials and the second (74) and fourth (87) semiconductor materials are strained semiconductor materials.
摘要翻译：半导体结构和方法被提供用于采用超级结结构（41）并覆盖具有嵌入式控制栅极（48）的沟槽（91）的半导体器件（40）。该方法包括：形成（52-6,52-9）交错的第一（70-1,70-2,70-3,70-4等）和第二（74-1,74-2,74-3）等）第一半导体材料（70）和第二半导体材料（74）的不同导电类型和不同迁移率的半导体材料的间隔开的区域，使得在第一实施例中，第二半导体材料（74）对于同一载体（70），以及提供（52-14）其中形成沟槽（90,91）的上覆的第三半导体材料（82），其上具有第四半导体材料（87）的侧壁（913），其具有比第三材料（82）更高的迁移率，适于在源极区域（86）之间，沟槽（91）中的第四（87）半导体材料和第二半导体材料（74）中承载电流（50）器件漂移空间（42）流向漏极（56）。在另一实施例中，第一（70）和第三（82）半导体材料是松弛材料，第二（74）和第四（87）半导体材料是应变半导体材料。

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