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1. 发明申请

WO2007001782A2 TUNABLE ANTIFUSE ELEMENT AND METHOD OF MANUFACTURE 审中-公开
标题翻译：可逆抗体元件及其制造方法
公开(公告)号：WO2007001782A2
公开(公告)日：2007-01-04
申请号：PCT/US2006022278
申请日：2006-06-08
申请人： FREESCALE SEMICONDUCTOR INC , MCKENNA JOHN M , PARRIS PATRICE M , CHEN WEIZE , MORRISON JENNIFER H , DE SOUZA RICHARD J
发明人： MCKENNA JOHN M , PARRIS PATRICE M , CHEN WEIZE , MORRISON JENNIFER H , DE SOUZA RICHARD J
IPC分类号： H01L29/04 , H01L21/82
CPC分类号： H01L27/112 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , Y10S438/981 , H01L2924/00
摘要： A tunable antifuse element (102, 202, 204, 504, 952) and method of fabricating the tunable antifuse element, including a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) including the fabrication of one of a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a plurality of rupture regions (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.
摘要翻译：一种可调谐反熔断元件（102,202,204,504,952）和制造可调谐反熔丝元件的方法，包括在表面上形成有源区（106）的基片材料（101），具有位于有源区域（106）上方的至少一部分，和设置在栅电极（104）和有源区域（106）之间的电介质层（110）。介电层（110）包括制造可调阶梯结构（127）之一。在操作期间，施加在栅极电极（104）和有源区域（106）之间的电压产生穿过介电层（110）的电流路径，并且多个断裂区域（130）中的电介质层（110）的破裂，。电介质层（110）可以通过改变阶梯层厚度和层的几何形状来调节。

2. 发明申请

WO2007001782A3 TUNABLE ANTIFUSE ELEMENT AND METHOD OF MANUFACTURE 审中-公开
公开(公告)号：WO2007001782A3
公开(公告)日：2007-01-04
申请号：PCT/US2006/022278
申请日：2006-06-08
申请人： FREESCALE SEMICONDUCTOR , MCKENNA, John, M. , PARRIS, Patrice, M. , CHEN, Weize , MORRISON, Jennifer, H. , DE SOUZA, Richard, J.
发明人： MCKENNA, John, M. , PARRIS, Patrice, M. , CHEN, Weize , MORRISON, Jennifer, H. , DE SOUZA, Richard, J.
IPC分类号： H01L21/82 , H01L21/8234 , H01L21/44 , H01L21/31
摘要： A tunable antifuse element (102, 202, 204, 504, 952) and method of fabricating the tunable antifuse element, including a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) including the fabrication of one of a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a plurality of rupture regions (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.

3. 发明申请

WO2006121564A2 HIGH VOLTAGE FIELD EFFECT DEVICE AND METHOD 审中-公开
标题翻译：高电压场效应器件及方法
公开(公告)号：WO2006121564A2
公开(公告)日：2006-11-16
申请号：PCT/US2006/013737
申请日：2006-04-07
申请人： FREESCALE SEMICONDUCTOR , DE FRESART, Edouard D. , DE SOUZA, Richard J. , LIN, Xin , MORRISON, Jennifer H. , PARRIS, Patrice M. , ZITOUNI, Moaniss
发明人： DE FRESART, Edouard D. , DE SOUZA, Richard J. , LIN, Xin , MORRISON, Jennifer H. , PARRIS, Patrice M. , ZITOUNI, Moaniss
IPC分类号： H01L31/00
CPC分类号： H01L29/0847 , H01L29/7833 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92') serially located between the channel (90) and the source (70, 70') or drain (76, 76'). A buried region (96, 96') of the same conductivity type as the drift space (92, 92') and the source (70, 70') or drain (76, 76') is provided below the drift space (92, 92'), separated therefrom in depth by a narrow gap (94, 94') and ohmically coupled to the source (70, 70') or drain (76, 76'). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94'). As the S-D voltage (Vo) and current (109, Io) increase, this difference (Vt) induces high field conduction between the drift space (92, 92') and the buried region (96, 96') and diverts part (112, It) of the S-D current (109, Io) through the buried region (96, 96') and away from the near surface portions of the drift space (92, 92') where breakdown generally occurs. Thus, BVdss is increased
摘要翻译：为具有增加的源 - 漏击穿电压（BVdss）的MOSFET（50,99,199）提供了方法和装置。源极（S）（70）和漏极（D）（76）通过栅极（84）下面的沟道（90）和串联地位于沟道（90）之间的一个或多个载流子漂移空间（92,92'）间隔开）和源极（70,70'）或漏极（76,76'）。与漂移空间（92,92'）和源极（70,70'）或漏极（76,76'）相同的导电类型的掩埋区域（96,96'）设置在漂移空间（92,92'）的下方， 92'），通过狭窄的间隙（94,94'）深度地分离，并且与欧姆耦合到源极（70,70'）或漏极（76,76'）。通过漂移空间的电流（110）在该间隙（94,94'）上产生电位差（Vt）。随着SD电压（Vo）和电流（109，Io）的增加，该差值（Vt）引起漂移空间（92,92'）和掩埋区域（96,96'）之间的高场导通，并且转移部分，It）通过掩埋区域（96,96'）并远离漂移空间（92,92'）的通常发生击穿的漂移空间（92,92'）的近表面部分的SD电流（109，Io）。因此，BVdss增加

4. 发明申请

WO2009142824A1 CIRCUIT FOR AND AN ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY CELL AND A PROCESS OF FORMING THE ELECTRONIC DEVICE 审中-公开
标题翻译：包括非易失性存储单元的电子设备和形成电子设备的方法
公开(公告)号：WO2009142824A1
公开(公告)日：2009-11-26
申请号：PCT/US2009/038500
申请日：2009-03-27
申请人： FREESCALE SEMICONDUCTOR INC. , CHEN, Weize , PARRIS, Patrice, M.
发明人： CHEN, Weize , PARRIS, Patrice, M.
IPC分类号： G11C16/04 , G11C16/10
CPC分类号： G11C16/0441 , G11C16/10 , H01L27/11519 , H01L27/11521
摘要： A circuit for a nonvolatile memory cell (10, 20, 30, 40, 50, 60, 70, 80, 90, 100) can include a charge-altering terminal (102, 202, 302, 402, 502, 602, 702, 802, 902, 1002) and an output terminal (108, 208, 308, 408, 508, 608, 708, 808, 908, 1008). The circuit can also include a first transistor (11, 21, 31, 41, 51, 61, 71, 81, 91, 1021) having a gate electrode that electrically floats and an active region including a current-carrying electrode, wherein the current-carrying electrode is coupled to the output terminal. The circuit can further include a second transistor (12, 22, 32, 42, 52, 62, 72, 82, 92, 1002) having a first electrode and a second electrode, wherein the first electrode is coupled to the gate electrode of the first transistor, and the second electrode is coupled to the charge-altering terminal. When changing the state of the memory cell, the second transistor can be active and no significant amount of charge carriers are transferred between the gate electrode of the first transistor and the active region of the first transistor. Other embodiments can include the electronic device itself and a process of forming the electronic device.
摘要翻译：用于非易失性存储单元（10,20,30,40,50,60,70,80,90,100）的电路可以包括电荷改变端子（102,202,302,402,502,602,702， 802,902,1002）和输出终端（108,208,308,408,508,608,708,808,908,1008）。电路还可以包括具有电浮置的栅电极和包括载流电极的有源区的第一晶体管（11,21,31,41,51,61,71,81,91,101,101），其中电流携带电极耦合到输出端子。电路还可以包括具有第一电极和第二电极的第二晶体管（12,22,32,42,52,62,72,82,92,1002），其中第一电极耦合到栅电极第一晶体管，并且第二电极耦合到电荷改变端子。当改变存储单元的状态时，第二晶体管可以是有效的，并且在第一晶体管的栅电极和第一晶体管的有源区之间不传输大量的电荷载流子。其他实施例可以包括电子设备本身和形成电子设备的过程。

5. 发明申请

WO2006121564A3 HIGH VOLTAGE FIELD EFFECT DEVICE AND METHOD 审中-公开
标题翻译：高电压场效应器件及方法
公开(公告)号：WO2006121564A3
公开(公告)日：2007-05-03
申请号：PCT/US2006013737
申请日：2006-04-07
申请人： FREESCALE SEMICONDUCTOR INC , DE FRESART EDOUARD D , DE SOUZA RICHARD J , LIN XIN , MORRISON JENNIFER H , PARRIS PATRICE M , ZITOUNI MOANISS
发明人： DE FRESART EDOUARD D , DE SOUZA RICHARD J , LIN XIN , MORRISON JENNIFER H , PARRIS PATRICE M , ZITOUNI MOANISS
IPC分类号： H01L29/76 , H01L21/336 , H01L21/8234 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7835 , H01L29/0847 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92') serially located between the channel (90) and the source (70, 70') or drain (76, 76'). A buried region (96, 96') of the same conductivity type as the drift space (92, 92') and the source (70, 70') or drain (76, 76') is provided below the drift space (92, 92'), separated therefrom in depth by a narrow gap (94, 94') and ohmically coupled to the source (70, 70') or drain (76, 76'). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94'). As the S-D voltage (Vo) and current (109, Io) increase, this difference (Vt) induces high field conduction between the drift space (92, 92') and the buried region (96, 96') and diverts part (112, It) of the S-D current (109, Io) through the buried region (96, 96') and away from the near surface portions of the drift space (92, 92') where breakdown generally occurs. Thus, BVdss is increased
摘要翻译：为具有增加的源 - 漏击穿电压（BVdss）的MOSFET（50,99,199）提供了方法和装置。源极（S）（70）和漏极（D）（76）通过栅极（84）下面的沟道（90）和串联地位于沟道（90）之间的一个或多个载流子漂移空间（92,92'）间隔开）和源极（70,70'）或漏极（76,76'）。与漂移空间（92,92'）和源极（70,70'）或漏极（76,76'）相同的导电类型的掩埋区域（96,96'）设置在漂移空间（92,92'）的下方， 92'），通过狭窄的间隙（94,94'）深度地分离，并且与欧姆耦合到源极（70,70'）或漏极（76,76'）。通过漂移空间的电流（110）在该间隙（94,94'）上产生电位差（Vt）。随着SD电压（Vo）和电流（109，Io）的增加，该差值（Vt）引起漂移空间（92,92'）和掩埋区域（96,96'）之间的高场导通，并且转移部分，It）通过掩埋区域（96,96'）并远离漂移空间（92,92'）的通常发生击穿的漂移空间（92,92'）的近表面部分的SD电流（109，Io）。因此，BVdss增加

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